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* [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
@ 2025-03-10  9:56 Jie Gan
  2025-03-14  6:48 ` Jie Gan
  2025-03-14 20:01 ` Bjorn Andersson
  0 siblings, 2 replies; 4+ messages in thread
From: Jie Gan @ 2025-03-10  9:56 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley
  Cc: Tingwei Zhang, Jinlong Mao, linux-arm-msm, devicetree,
	linux-kernel, Konrad Dybcio, Suzuki K Poulose

Add CTCU and ETR nodes in DT to enable related functionalities.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
---
Separate from the patch series: Coresight: Add Coresight TMC Control Unit driver

Changes in V16:
1. Add acked-by tag from Suzuki.
2. Rebased on next-20250307.
Link to V15 - https://lore.kernel.org/all/20250303032931.2500935-11-quic_jiegan@quicinc.com/
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++
 1 file changed, 153 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 23049cc58896..93ca37843990 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2418,6 +2418,35 @@ cryptobam: dma-controller@1dc4000 {
 				 <&apps_smmu 0x481 0x00>;
 		};
 
+		ctcu@4001000 {
+			compatible = "qcom,sa8775p-ctcu";
+			reg = <0x0 0x04001000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					ctcu_in0: endpoint {
+						remote-endpoint = <&etr0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					ctcu_in1: endpoint {
+						remote-endpoint = <&etr1_out>;
+					};
+				};
+			};
+		};
+
 		stm: stm@4002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x4002000 0x0 0x1000>,
@@ -2622,6 +2651,122 @@ qdss_funnel_in1: endpoint {
 			};
 		};
 
+		replicator@4046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x04046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					qdss_rep_in: endpoint {
+						remote-endpoint = <&swao_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_rep_out0: endpoint {
+						remote-endpoint = <&etr_rep_in>;
+					};
+				};
+			};
+		};
+
+		tmc_etr: tmc@4048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x04048000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			iommus = <&apps_smmu 0x04c0 0x00>;
+
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr0_in: endpoint {
+						remote-endpoint = <&etr_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etr0_out: endpoint {
+						remote-endpoint = <&ctcu_in0>;
+					};
+				};
+			};
+		};
+
+		replicator@404e000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x0404e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etr_rep_in: endpoint {
+						remote-endpoint = <&qdss_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					etr_rep_out0: endpoint {
+						remote-endpoint = <&etr0_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					etr_rep_out1: endpoint {
+						remote-endpoint = <&etr1_in>;
+					};
+				};
+			};
+		};
+
+		tmc_etr1: tmc@404f000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x0404f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			iommus = <&apps_smmu 0x04a0 0x40>;
+
+			arm,scatter-gather;
+			arm,buffer-size = <0x400000>;
+
+			in-ports {
+				port {
+					etr1_in: endpoint {
+						remote-endpoint = <&etr_rep_out1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etr1_out: endpoint {
+						remote-endpoint = <&ctcu_in1>;
+					};
+				};
+			};
+		};
+
 		funnel@4b04000 {
 			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 			reg = <0x0 0x4b04000 0x0 0x1000>;
@@ -2697,6 +2842,14 @@ out-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
+				port@0 {
+					reg = <0>;
+
+					swao_rep_out0: endpoint {
+						remote-endpoint = <&qdss_rep_in>;
+					};
+				};
+
 				port@1 {
 					reg = <1>;
 					swao_rep_out1: endpoint {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
  2025-03-10  9:56 [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
@ 2025-03-14  6:48 ` Jie Gan
  2025-03-14  7:09   ` Krzysztof Kozlowski
  2025-03-14 20:01 ` Bjorn Andersson
  1 sibling, 1 reply; 4+ messages in thread
From: Jie Gan @ 2025-03-14  6:48 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley
  Cc: Tingwei Zhang, Jinlong Mao, linux-arm-msm, devicetree,
	linux-kernel, Konrad Dybcio, Suzuki K Poulose



On 3/10/2025 5:56 PM, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable related functionalities.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
> ---
> Separate from the patch series: Coresight: Add Coresight TMC Control Unit driver
> 
> Changes in V16:
> 1. Add acked-by tag from Suzuki.
> 2. Rebased on next-20250307.
> Link to V15 - https://lore.kernel.org/all/20250303032931.2500935-11-quic_jiegan@quicinc.com/
> ---
>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++
>   1 file changed, 153 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 23049cc58896..93ca37843990 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi


Gentle ping. Can you please help to review the patch?

Thanks,
Jie

[...]

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
  2025-03-14  6:48 ` Jie Gan
@ 2025-03-14  7:09   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2025-03-14  7:09 UTC (permalink / raw)
  To: Jie Gan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley
  Cc: Tingwei Zhang, Jinlong Mao, linux-arm-msm, devicetree,
	linux-kernel, Konrad Dybcio, Suzuki K Poulose

On 14/03/2025 07:48, Jie Gan wrote:
> 
> 
> On 3/10/2025 5:56 PM, Jie Gan wrote:
>> Add CTCU and ETR nodes in DT to enable related functionalities.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
>> ---
>> Separate from the patch series: Coresight: Add Coresight TMC Control Unit driver
>>
>> Changes in V16:
>> 1. Add acked-by tag from Suzuki.
>> 2. Rebased on next-20250307.
>> Link to V15 - https://lore.kernel.org/all/20250303032931.2500935-11-quic_jiegan@quicinc.com/
>> ---
>>   arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++
>>   1 file changed, 153 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 23049cc58896..93ca37843990 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> 
> 
> Gentle ping. Can you please help to review the patch?
4 days? You gave us exactly four days and ping? This contribution is not
special and should not receive any special treatment.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
  2025-03-10  9:56 [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
  2025-03-14  6:48 ` Jie Gan
@ 2025-03-14 20:01 ` Bjorn Andersson
  1 sibling, 0 replies; 4+ messages in thread
From: Bjorn Andersson @ 2025-03-14 20:01 UTC (permalink / raw)
  To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Jie Gan
  Cc: Tingwei Zhang, Jinlong Mao, linux-arm-msm, devicetree,
	linux-kernel, Konrad Dybcio, Suzuki K Poulose


On Mon, 10 Mar 2025 17:56:25 +0800, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable related functionalities.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes
      commit: 05ed68070d7a061f62f502d07f883c05dc666990

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

^ permalink raw reply	[flat|nested] 4+ messages in thread

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2025-03-10  9:56 [PATCH v16] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
2025-03-14  6:48 ` Jie Gan
2025-03-14  7:09   ` Krzysztof Kozlowski
2025-03-14 20:01 ` Bjorn Andersson

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