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([2a02:810d:15c0:828:8fa0:9989:3f72:b14f]) by smtp.gmail.com with ESMTPSA id v5-20020ac25605000000b004b55ddeb7e3sm2964212lfd.309.2023.04.12.04.34.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Apr 2023 04:34:15 -0700 (PDT) Message-ID: <8dd0dc63-e0df-8764-f756-da032d9d671c@linaro.org> Date: Wed, 12 Apr 2023 13:34:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v4 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Content-Language: en-US To: Changhuang Liang , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel Cc: Jack Zhu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20230412084540.295411-1-changhuang.liang@starfivetech.com> <20230412084540.295411-2-changhuang.liang@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20230412084540.295411-2-changhuang.liang@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 12/04/2023 10:45, Changhuang Liang wrote: > StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on > a M31 IP. Add a binding for it. So this is D-PHY? Or the other patch is D-PHY? The naming is quite confusing and your commit msgs are not helping here. Also the power domain phandle here adds to the confusion. > > Signed-off-by: Changhuang Liang > --- > .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > new file mode 100644 > index 000000000000..5fb2f14af816 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive SoC MIPI D-PHY Rx Controller > + > +maintainers: > + - Jack Zhu > + - Changhuang Liang > + > +description: > + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer > + CSI camera data. > + > +properties: > + compatible: > + const: starfive,jh7110-dphy-rx > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: config clock > + - description: reference clock > + - description: escape mode transmit clock > + > + clock-names: > + items: > + - const: cfg > + - const: ref > + - const: tx > + > + resets: > + items: > + - description: DPHY_HW reset > + - description: DPHY_B09_ALWAYS_ON reset > + > + power-domains: > + maxItems: 1 > + > + lane_maps: Why did this appear? Underscores are not allowed. It looks like you re-implement some standard property. > + $ref: /schemas/types.yaml#/definitions/uint8-array > + description: > + D-PHY rx controller physical lanes and logic lanes mapping table. > + items: > + - description: logic lane index point to physical lane clock lane 0 > + - description: logic lane index point to physical lane data lane 0 > + - description: logic lane index point to physical lane data lane 1 > + - description: logic lane index point to physical lane data lane 2 > + - description: logic lane index point to physical lane data lane 3 > + - description: logic lane index point to physical lane clock lane 1 > + Best regards, Krzysztof