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([2001:a61:34c9:ea01:14b4:7ed9:5135:9381]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d081f7141sm3322495f8f.6.2024.10.04.06.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 06:41:45 -0700 (PDT) Message-ID: <8def18e29299ea220d684bb6c963831071fded68.camel@gmail.com> Subject: Re: [PATCH v4 07/11] iio: dac: adi-axi-dac: extend features From: Nuno =?ISO-8859-1?Q?S=E1?= To: Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno Sa , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mihail Chindris , Olivier Moysan Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , devicetree@vger.kernel.org, dlechner@baylibre.com, Mark Brown Date: Fri, 04 Oct 2024 15:41:44 +0200 In-Reply-To: <20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-7-ceb157487329@baylibre.com> References: <20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-0-ceb157487329@baylibre.com> <20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-7-ceb157487329@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2024-10-03 at 19:29 +0200, Angelo Dureghello wrote: > From: Angelo Dureghello >=20 > Extend AXI-DAC backend with new features required to interface > to the ad3552r DAC. Mainly, a new compatible string is added to > support the ad3552r-axi DAC IP, very similar to the generic DAC > IP but with some customizations to work with the ad3552r. >=20 > Then, a serie of generic functions has been added to match with > ad3552r needs. Function names has been kept generic as much as > possible, to allow re-utilization from other frontend drivers. >=20 > Signed-off-by: Angelo Dureghello > --- > =C2=A0drivers/iio/dac/adi-axi-dac.c | 278 +++++++++++++++++++++++++++++++= ++++++++--- > =C2=A01 file changed, 264 insertions(+), 14 deletions(-) >=20 >=20 ... > + > +static int axi_dac_read_raw(struct iio_backend *back, > + =C2=A0=C2=A0=C2=A0 struct iio_chan_spec const *chan, > + =C2=A0=C2=A0=C2=A0 int *val, int *val2, long mask) > +{ > + struct axi_dac_state *st =3D iio_backend_get_priv(back); > + int err; > + > + switch (mask) { > + case IIO_CHAN_INFO_FREQUENCY: { > + int clk_in, reg; > + > + if (!st->info->bus_controller) > + return -EOPNOTSUPP; Since we'll likely need a more explicitly flag for requesting the reference= clock, I think that can be used in here and so, replace this one. Sorry for suggesti= ng this one. More details below... > + > + /* > + * As from ad3552r AXI IP documentation, > + * returning the SCLK depending on the stream mode. > + */ > + err =3D regmap_read(st->regmap, AXI_DAC_CUSTOM_CTRL_REG, ®); > + if (err) > + return err; > + > + clk_in =3D clk_get_rate(st->clk); > + I don't think the rate is likely to change (at least for now it does not ri= ght?). So we can cache the rate during probe (and then no need to save the struct clk= ). > + if (reg & AXI_DAC_CUSTOM_CTRL_STREAM) > + *val =3D clk_in / 2; > + else > + *val =3D clk_in / 8; > + > + return IIO_VAL_INT; > + } > + default: > + return -EINVAL; > + } > +} > + >=20 ... > =C2=A0 > - clk =3D devm_clk_get_enabled(&pdev->dev, NULL); > - if (IS_ERR(clk)) > - return dev_err_probe(&pdev->dev, PTR_ERR(clk), > + st->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); > + if (IS_ERR(st->clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(st->clk), > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0 "failed to get clock\n"); I think this is wrong. If we look at the docs [1], the clock we want in ord= er to calculate SCLK is the dac_clk which should be the reference clock. The cloc= k we previously had in here is the axi clock (s_axi_aclk in the docs) which is t= he axi bus clock so we can read/write registers. So, before we had no clk_name before = we only had one clock but now you need proper names for the clocks. For the axi clk= , we can keep a local clock and just make sure we enable it. For the new dac_clk (as= named in the docs), you need to get it only if the IP needs one. And I'm not sure at= tach the clk need to the bus_controller flag is a great idea... So I would replace t= he bus_controller flag with an explicit has_clkin or has_dacclk (something alo= ng those lines) and use that to request (and enable) the extra clock conditionally. [1]: https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html - Nuno S=C3=A1