From: "Trevor Wu (吳文良)" <Trevor.Wu@mediatek.com>
To: "robh@kernel.org" <robh@kernel.org>
Cc: "linux-mediatek@lists.infradead.org"
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<angelogioacchino.delregno@collabora.com>
Subject: Re: [PATCH v2 10/12] dt-bindings: mediatek: mt8188: add audio afe document
Date: Mon, 31 Oct 2022 07:11:40 +0000 [thread overview]
Message-ID: <8e9650f61d22b6f1e4fa551be34e7316e3edf30c.camel@mediatek.com> (raw)
In-Reply-To: <20221024183357.GA2012388-robh@kernel.org>
On Mon, 2022-10-24 at 13:33 -0500, Rob Herring wrote:
> On Fri, Oct 21, 2022 at 04:27:17PM +0800, Trevor Wu wrote:
> > Add mt8188 audio afe document.
> >
> > Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
> > ---
> > .../bindings/sound/mt8188-afe-pcm.yaml | 187
> > ++++++++++++++++++
> > 1 file changed, 187 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/sound/mt8188-
> > afe-pcm.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/sound/mt8188-afe-
> > pcm.yaml b/Documentation/devicetree/bindings/sound/mt8188-afe-
> > pcm.yaml
> > new file mode 100644
> > index 000000000000..b2c548c31e4d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sound/mt8188-afe-pcm.yaml
> > @@ -0,0 +1,187 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> >
..snip
> >
> > +
> > +patternProperties:
> > + "^mediatek,etdm-in[1-2]-chn-disabled$":
> > + $ref: /schemas/types.yaml#/definitions/uint8-array
> > + maxItems: 16
> > + description: |
>
> Don't need '|'
>
> > + Specify which input channel should be disabled, so the data
> > of
> > + specified channel won't be outputted to memory.
>
> I'm not clear on what each of the 16 entries represents. What's index
> 0,
> 1, 2, etc.?
Hi Rob,
Ext Codec -> ETDM_IN -> MEMIF(DMA) -> Memory
The maximum channel number of etdm-in is 16.
The index matches to the input channel ID.
0 : CH0
1 : CH1
...
15: CH15
User can config the channel ID they don't want to be outputted to
memory in the property.
For example,
For 4 channels ETDM connection, and the following property is
configured.
"mediatek,etdm-in1-chn-disabled = <0>;"
Received etdm1 input data outputted to memory will be [d0_ch1, d0_ch2,
d0_ch3, d1_ch1, d1_ch2, d1_ch3, ...]. CH0 is dropped.
>
> > + items:
> > + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
>
> maximum: 15
>
>
> > +
> > + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
> > + description: Specify etdm in mclk output rate for always on
> > case.
> > +
> > + "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
> > + description: Specify etdm out mclk output rate for always on
> > case.
> > +
> > + "^mediatek,etdm-in[1-2]-multi-pin-mode$":
> > + type: boolean
> > + description: if present, the etdm data mode is I2S.
> > +
> > + "^mediatek,etdm-out[1-3]-multi-pin-mode$":
> > + type: boolean
> > + description: if present, the etdm data mode is I2S.
> > +
> > + "^mediatek,etdm-in[1-2]-cowork-source$":
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + etdm modules can share the same external clock pin. Specify
> > + which etdm clock source is required by this etdm in moudule.
> > + enum:
> > + - 0 # etdm1_in
> > + - 1 # etdm2_in
> > + - 2 # etdm1_out
> > + - 3 # etdm2_out
> > +
> > + "^mediatek,etdm-out[1-2]-cowork-source$":
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + etdm modules can share the same external clock pin. Specify
> > + which etdm clock source is required by this etdm out
> > moudule.
> > + enum:
> > + - 0 # etdm1_in
> > + - 1 # etdm2_in
> > + - 2 # etdm1_out
> > + - 3 # etdm2_out
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - resets
> > + - reset-names
> > + - mediatek,topckgen
> > + - power-domains
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + afe: afe@10b10000 {
> > + compatible = "mediatek,mt8188-afe";
> > + reg = <0x10b10000 0x10000>;
> > + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
> > + resets = <&watchdog 14>;
> > + reset-names = "audiosys";
> > + mediatek,topckgen = <&topckgen>;
> > + power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
> > + clocks = <&clk26m>,
> > + <&topckgen 72>, //CLK_TOP_APLL1
> > + <&topckgen 73>, //CLK_TOP_APLL2
> > + <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
> > + <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
> > + <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
> > + <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
> > + <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
> > + <&topckgen 83>, //CLK_TOP_A1SYS_HP
> > + <&topckgen 31>, //CLK_TOP_AUD_INTBUS
> > + <&topckgen 32>, //CLK_TOP_AUDIO_H
> > + <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS
> > + <&topckgen 81>, //CLK_TOP_DPTX
> > + <&topckgen 77>, //CLK_TOP_I2SO1
> > + <&topckgen 78>, //CLK_TOP_I2SO2
> > + <&topckgen 79>, //CLK_TOP_I2SI1
> > + <&topckgen 80>, //CLK_TOP_I2SI2
> > + <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
> > + clock-names = "clk26m",
> > + "apll1_ck",
> > + "apll2_ck",
> > + "apll12_div0",
> > + "apll12_div1",
> > + "apll12_div2",
> > + "apll12_div3",
> > + "apll12_div9",
> > + "a1sys_hp_sel",
> > + "aud_intbus_sel",
> > + "audio_h_sel",
> > + "audio_local_bus_sel",
> > + "dptx_m_sel",
> > + "i2so1_m_sel",
> > + "i2so2_m_sel",
> > + "i2si1_m_sel",
> > + "i2si2_m_sel",
> > + "adsp_audio_26m";
>
> It's good if the examples include optional properties so we at least
> have some validation the schema matches the DTS.
>
OK, I will put some optional properties in V3.
Thanks,
Trevor
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
> >
>
>
next prev parent reply other threads:[~2022-10-31 7:11 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-21 8:27 [PATCH v2 00/12] ASoC: mediatek: Add support for MT8188 SoC Trevor Wu
2022-10-21 8:27 ` [PATCH v2 01/12] ASoC: mediatek: common: add SMC ops and SMC CMD Trevor Wu
2022-10-21 8:27 ` [PATCH v2 02/12] ASoC: mediatek: mt8188: add common header Trevor Wu
2022-10-21 8:27 ` [PATCH v2 03/12] ASoC: mediatek: mt8188: support audsys clock Trevor Wu
2022-10-21 8:41 ` AngeloGioacchino Del Regno
2022-10-21 9:58 ` Trevor Wu (吳文良)
2022-10-25 10:18 ` AngeloGioacchino Del Regno
2022-10-26 4:10 ` Trevor Wu (吳文良)
2022-10-26 8:18 ` AngeloGioacchino Del Regno
2022-12-01 8:43 ` Trevor Wu (吳文良)
2022-12-01 9:42 ` AngeloGioacchino Del Regno
2022-10-21 8:27 ` [PATCH v2 04/12] ASoC: mediatek: mt8188: support adda in platform driver Trevor Wu
2022-10-21 8:41 ` AngeloGioacchino Del Regno
2022-10-21 8:27 ` [PATCH v2 05/12] ASoC: mediatek: mt8188: support etdm " Trevor Wu
2022-10-21 8:41 ` AngeloGioacchino Del Regno
2022-10-21 8:27 ` [PATCH v2 06/12] ASoC: mediatek: mt8188: support pcmif " Trevor Wu
2022-10-21 8:27 ` [PATCH v2 07/12] ASoC: mediatek: mt8188: support audio clock control Trevor Wu
2022-10-21 8:27 ` [PATCH v2 08/12] ASoC: mediatek: mt8188: add platform driver Trevor Wu
2022-10-21 11:55 ` kernel test robot
2022-10-21 8:27 ` [PATCH v2 09/12] ASoC: mediatek: mt8188: add control for timing select Trevor Wu
2022-10-21 8:27 ` [PATCH v2 10/12] dt-bindings: mediatek: mt8188: add audio afe document Trevor Wu
2022-10-24 18:33 ` Rob Herring
2022-10-31 7:11 ` Trevor Wu (吳文良) [this message]
2022-10-29 0:06 ` Krzysztof Kozlowski
2022-10-31 6:50 ` Trevor Wu (吳文良)
2022-10-21 8:27 ` [PATCH v2 11/12] ASoC: mediatek: mt8188: add machine driver with mt6359 Trevor Wu
2022-10-21 8:27 ` [PATCH v2 12/12] dt-bindings: mediatek: mt8188: add mt8188-mt6359 document Trevor Wu
2022-10-24 18:38 ` Rob Herring
2022-10-31 6:53 ` Trevor Wu (吳文良)
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