[PATCH 0/3] Add support for thermal mitigation for K3 J7200 SoC

[PATCH 0/3] Add support for thermal mitigation for K3 J7200 SoC

[Apurva Nandan]

Add support for thermal mitigation using the CPUFREQ for K3 J7200 SoC.
K3 J7200 SoC supports Dynamic Frequency Scaling(DFS) for A72 & this can
be used to drop the cpu frequency using cpufreq to produce a cooling
effect in the SoC.

Keerthy (3):
  thermal: k3_j72xx_bandgap: Add cooling device support
  arm64: dts: ti: k3-j7200: Add the supported frequencies for A72
  arm64: dts: ti: k3-j7200-thermal: Add cooling maps and cpu_alert trip
    at 75C

 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi |  14 +++
 arch/arm64/boot/dts/ti/k3-j7200.dtsi         |  28 +++++
 drivers/thermal/k3_j72xx_bandgap.c           | 121 +++++++++++++++++++
 3 files changed, 163 insertions(+)

-- 
2.34.1

[PATCH 1/3] thermal: k3_j72xx_bandgap: Add cooling device support

[Apurva Nandan]

From: Keerthy <j-keerthy@ti.com>

Add cpufreq as a cooling device, based on the inputs from the thermal
sensors.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
 drivers/thermal/k3_j72xx_bandgap.c | 121 +++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
index a5a0fc9b9356..c844cb527761 100644
--- a/drivers/thermal/k3_j72xx_bandgap.c
+++ b/drivers/thermal/k3_j72xx_bandgap.c
@@ -19,6 +19,9 @@
 #include <linux/of.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_cooling.h>
 
 #define K3_VTM_DEVINFO_PWR0_OFFSET		0x4
 #define K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK	0xf0
@@ -183,10 +186,28 @@ struct k3_j72xx_bandgap {
 /* common data structures */
 struct k3_thermal_data {
 	struct k3_j72xx_bandgap *bgp;
+	struct cpufreq_policy *policy;
+	struct thermal_zone_device *ti_thermal;
+	struct thermal_cooling_device *cool_dev;
+	struct work_struct thermal_wq;
 	u32 ctrl_offset;
 	u32 stat_offset;
+	enum thermal_device_mode mode;
+	int prev_temp;
+	int sensor_id;
 };
 
+static void k3_thermal_work(struct work_struct *work)
+{
+	struct k3_thermal_data *data = container_of(work,
+					struct k3_thermal_data, thermal_wq);
+
+	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
+
+	dev_info(&data->ti_thermal->device, "updated thermal zone %s\n",
+		 data->ti_thermal->type);
+}
+
 static int two_cmp(int tmp, int mask)
 {
 	tmp = ~(tmp);
@@ -251,8 +272,40 @@ static int k3_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
 	return k3_bgp_read_temp(thermal_zone_device_priv(tz), temp);
 }
 
+static int k3_thermal_get_trend(struct thermal_zone_device *tz, int trip, enum thermal_trend *trend)
+{
+	struct k3_thermal_data *data = tz->devdata;
+	struct k3_j72xx_bandgap *bgp;
+	u32 temp1, temp2;
+	int tr, ret = 0;
+
+	bgp = data->bgp;
+
+	ret = k3_thermal_get_temp(tz, &temp1);
+	if (ret)
+		return ret;
+	temp2 = data->prev_temp;
+
+	tr = temp1 - temp2;
+
+	data->prev_temp = temp1;
+
+	if (tr > 0)
+		*trend = THERMAL_TREND_RAISING;
+	else if (tr < 0)
+		*trend = THERMAL_TREND_DROPPING;
+	else
+		*trend = THERMAL_TREND_STABLE;
+
+	dev_dbg(bgp->dev, "The temperatures are t1 = %d and t2 = %d and trend =%d\n",
+		temp1, temp2, *trend);
+
+	return ret;
+}
+
 static const struct thermal_zone_device_ops k3_of_thermal_ops = {
 	.get_temp = k3_thermal_get_temp,
+	.get_trend = k3_thermal_get_trend,
 };
 
 static int k3_j72xx_bandgap_temp_to_adc_code(int temp)
@@ -342,6 +395,63 @@ struct k3_j72xx_bandgap_data {
 	const bool has_errata_i2128;
 };
 
+static int k3_thermal_register_cpu_cooling(struct k3_j72xx_bandgap *bgp, int id)
+{
+	struct k3_thermal_data *data;
+	struct device_node *np = bgp->dev->of_node;
+
+	/*
+	 * We are assuming here that if one deploys the zone
+	 * using DT, then it must be aware that the cooling device
+	 * loading has to happen via cpufreq driver.
+	 */
+	if (of_find_property(np, "#thermal-sensor-cells", NULL))
+		return 0;
+
+	data = bgp->ts_data[id];
+	if (!data)
+		return -EINVAL;
+
+	data->policy = cpufreq_cpu_get(0);
+	if (!data->policy) {
+		pr_debug("%s: CPUFreq policy not found\n", __func__);
+		return -EPROBE_DEFER;
+	}
+
+	/* Register cooling device */
+	data->cool_dev = cpufreq_cooling_register(data->policy);
+	if (IS_ERR(data->cool_dev)) {
+		int ret = PTR_ERR(data->cool_dev);
+
+		dev_err(bgp->dev, "Failed to register cpu cooling device %d\n",
+			ret);
+		cpufreq_cpu_put(data->policy);
+
+		return ret;
+	}
+
+	data->mode = THERMAL_DEVICE_ENABLED;
+
+	INIT_WORK(&data->thermal_wq, k3_thermal_work);
+
+	return 0;
+}
+
+static int k3_thermal_unregister_cpu_cooling(struct k3_j72xx_bandgap *bgp, int id)
+{
+	struct k3_thermal_data *data;
+
+	data = bgp->ts_data[id];
+
+	if (!IS_ERR_OR_NULL(data)) {
+		cpufreq_cooling_unregister(data->cool_dev);
+		if (data->policy)
+			cpufreq_cpu_put(data->policy);
+	}
+
+	return 0;
+}
+
 static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
 {
 	int ret = 0, cnt, val, id;
@@ -452,6 +562,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
 	/* Register the thermal sensors */
 	for (id = 0; id < cnt; id++) {
 		data[id].bgp = bgp;
+		data[id].sensor_id = id;
 		data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20;
 		data[id].stat_offset = data[id].ctrl_offset +
 					K3_VTM_TMPSENS_STAT_OFFSET;
@@ -477,6 +588,12 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
 		writel(val, data[id].bgp->cfg2_base + data[id].ctrl_offset);
 
 		bgp->ts_data[id] = &data[id];
+
+		if (id == 1)
+			ret = k3_thermal_register_cpu_cooling(bgp, 1);
+		if (ret)
+			goto err_alloc;
+
 		ti_thermal = devm_thermal_of_zone_register(bgp->dev, id, &data[id],
 							   &k3_of_thermal_ops);
 		if (IS_ERR(ti_thermal)) {
@@ -514,6 +631,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
 	return 0;
 
 err_free_ref_table:
+	k3_thermal_unregister_cpu_cooling(bgp, 1);
 	kfree(ref_table);
 
 err_alloc:
@@ -525,6 +643,9 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
 
 static int k3_j72xx_bandgap_remove(struct platform_device *pdev)
 {
+	struct k3_j72xx_bandgap *bgp = platform_get_drvdata(pdev);
+
+	k3_thermal_unregister_cpu_cooling(bgp, 1);
 	pm_runtime_put_sync(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 
-- 
2.34.1

Re: [PATCH 1/3] thermal: k3_j72xx_bandgap: Add cooling device support

[Daniel Lezcano]

On 09/08/2023 19:39, Apurva Nandan wrote:
> From: Keerthy <j-keerthy@ti.com>
> 
> Add cpufreq as a cooling device, based on the inputs from the thermal
> sensors.

I don't understand these changes.

By using the DT, it is all done automatically, no ?

> 
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
>   drivers/thermal/k3_j72xx_bandgap.c | 121 +++++++++++++++++++++++++++++
>   1 file changed, 121 insertions(+)
> 
> diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
> index a5a0fc9b9356..c844cb527761 100644
> --- a/drivers/thermal/k3_j72xx_bandgap.c
> +++ b/drivers/thermal/k3_j72xx_bandgap.c
> @@ -19,6 +19,9 @@
>   #include <linux/of.h>
>   #include <linux/delay.h>
>   #include <linux/slab.h>
> +#include <linux/cpufreq.h>
> +#include <linux/cpumask.h>
> +#include <linux/cpu_cooling.h>
>   
>   #define K3_VTM_DEVINFO_PWR0_OFFSET		0x4
>   #define K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK	0xf0
> @@ -183,10 +186,28 @@ struct k3_j72xx_bandgap {
>   /* common data structures */
>   struct k3_thermal_data {
>   	struct k3_j72xx_bandgap *bgp;
> +	struct cpufreq_policy *policy;
> +	struct thermal_zone_device *ti_thermal;
> +	struct thermal_cooling_device *cool_dev;
> +	struct work_struct thermal_wq;
>   	u32 ctrl_offset;
>   	u32 stat_offset;
> +	enum thermal_device_mode mode;
> +	int prev_temp;
> +	int sensor_id;
>   };
>   
> +static void k3_thermal_work(struct work_struct *work)
> +{
> +	struct k3_thermal_data *data = container_of(work,
> +					struct k3_thermal_data, thermal_wq);
> +
> +	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
> +
> +	dev_info(&data->ti_thermal->device, "updated thermal zone %s\n",
> +		 data->ti_thermal->type);
> +}
> +
>   static int two_cmp(int tmp, int mask)
>   {
>   	tmp = ~(tmp);
> @@ -251,8 +272,40 @@ static int k3_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
>   	return k3_bgp_read_temp(thermal_zone_device_priv(tz), temp);
>   }
>   
> +static int k3_thermal_get_trend(struct thermal_zone_device *tz, int trip, enum thermal_trend *trend)
> +{
> +	struct k3_thermal_data *data = tz->devdata;
> +	struct k3_j72xx_bandgap *bgp;
> +	u32 temp1, temp2;
> +	int tr, ret = 0;
> +
> +	bgp = data->bgp;
> +
> +	ret = k3_thermal_get_temp(tz, &temp1);
> +	if (ret)
> +		return ret;
> +	temp2 = data->prev_temp;
> +
> +	tr = temp1 - temp2;
> +
> +	data->prev_temp = temp1;
> +
> +	if (tr > 0)
> +		*trend = THERMAL_TREND_RAISING;
> +	else if (tr < 0)
> +		*trend = THERMAL_TREND_DROPPING;
> +	else
> +		*trend = THERMAL_TREND_STABLE;
> +
> +	dev_dbg(bgp->dev, "The temperatures are t1 = %d and t2 = %d and trend =%d\n",
> +		temp1, temp2, *trend);
> +
> +	return ret;
> +}
> +
>   static const struct thermal_zone_device_ops k3_of_thermal_ops = {
>   	.get_temp = k3_thermal_get_temp,
> +	.get_trend = k3_thermal_get_trend,
>   };
>   
>   static int k3_j72xx_bandgap_temp_to_adc_code(int temp)
> @@ -342,6 +395,63 @@ struct k3_j72xx_bandgap_data {
>   	const bool has_errata_i2128;
>   };
>   
> +static int k3_thermal_register_cpu_cooling(struct k3_j72xx_bandgap *bgp, int id)
> +{
> +	struct k3_thermal_data *data;
> +	struct device_node *np = bgp->dev->of_node;
> +
> +	/*
> +	 * We are assuming here that if one deploys the zone
> +	 * using DT, then it must be aware that the cooling device
> +	 * loading has to happen via cpufreq driver.
> +	 */
> +	if (of_find_property(np, "#thermal-sensor-cells", NULL))
> +		return 0;
> +
> +	data = bgp->ts_data[id];
> +	if (!data)
> +		return -EINVAL;
> +
> +	data->policy = cpufreq_cpu_get(0);
> +	if (!data->policy) {
> +		pr_debug("%s: CPUFreq policy not found\n", __func__);
> +		return -EPROBE_DEFER;
> +	}
> +
> +	/* Register cooling device */
> +	data->cool_dev = cpufreq_cooling_register(data->policy);
> +	if (IS_ERR(data->cool_dev)) {
> +		int ret = PTR_ERR(data->cool_dev);
> +
> +		dev_err(bgp->dev, "Failed to register cpu cooling device %d\n",
> +			ret);
> +		cpufreq_cpu_put(data->policy);
> +
> +		return ret;
> +	}
> +
> +	data->mode = THERMAL_DEVICE_ENABLED;
> +
> +	INIT_WORK(&data->thermal_wq, k3_thermal_work);
> +
> +	return 0;
> +}
> +
> +static int k3_thermal_unregister_cpu_cooling(struct k3_j72xx_bandgap *bgp, int id)
> +{
> +	struct k3_thermal_data *data;
> +
> +	data = bgp->ts_data[id];
> +
> +	if (!IS_ERR_OR_NULL(data)) {
> +		cpufreq_cooling_unregister(data->cool_dev);
> +		if (data->policy)
> +			cpufreq_cpu_put(data->policy);
> +	}
> +
> +	return 0;
> +}
> +
>   static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
>   {
>   	int ret = 0, cnt, val, id;
> @@ -452,6 +562,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
>   	/* Register the thermal sensors */
>   	for (id = 0; id < cnt; id++) {
>   		data[id].bgp = bgp;
> +		data[id].sensor_id = id;
>   		data[id].ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20;
>   		data[id].stat_offset = data[id].ctrl_offset +
>   					K3_VTM_TMPSENS_STAT_OFFSET;
> @@ -477,6 +588,12 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
>   		writel(val, data[id].bgp->cfg2_base + data[id].ctrl_offset);
>   
>   		bgp->ts_data[id] = &data[id];
> +
> +		if (id == 1)
> +			ret = k3_thermal_register_cpu_cooling(bgp, 1);
> +		if (ret)
> +			goto err_alloc;
> +
>   		ti_thermal = devm_thermal_of_zone_register(bgp->dev, id, &data[id],
>   							   &k3_of_thermal_ops);
>   		if (IS_ERR(ti_thermal)) {
> @@ -514,6 +631,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
>   	return 0;
>   
>   err_free_ref_table:
> +	k3_thermal_unregister_cpu_cooling(bgp, 1);
>   	kfree(ref_table);
>   
>   err_alloc:
> @@ -525,6 +643,9 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
>   
>   static int k3_j72xx_bandgap_remove(struct platform_device *pdev)
>   {
> +	struct k3_j72xx_bandgap *bgp = platform_get_drvdata(pdev);
> +
> +	k3_thermal_unregister_cpu_cooling(bgp, 1);
>   	pm_runtime_put_sync(&pdev->dev);
>   	pm_runtime_disable(&pdev->dev);
>   

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[PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72

[Apurva Nandan]

From: Keerthy <j-keerthy@ti.com>

Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72.
This enables support for Dynamic Frequency Scaling(DFS)

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index ef73e6d7e858..7222c453096f 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -48,6 +48,10 @@ cpu0: cpu@0 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&L2_0>;
+			clocks = <&k3_clks 202 2>;
+			clock-names = "cpu";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>; /* min followed by max */
 		};
 
 		cpu1: cpu@1 {
@@ -62,6 +66,30 @@ cpu1: cpu@1 {
 			d-cache-line-size = <64>;
 			d-cache-sets = <256>;
 			next-level-cache = <&L2_0>;
+			clocks = <&k3_clks 203 0>;
+			clock-names = "cpu";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+	};
+
+	cpu0_opp_table: opp-table {
+		compatible = "operating-points-v2";
+
+		opp4-2000000000 {
+			opp-hz = /bits/ 64 <2000000000>;
+		};
+
+		opp3-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+		};
+
+		opp2-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+
+		opp1-750000000 {
+			opp-hz = /bits/ 64 <750000000>;
 		};
 	};
 
-- 
2.34.1

Re: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72

[Nishanth Menon]

On 23:09-20230809, Apurva Nandan wrote:
> From: Keerthy <j-keerthy@ti.com>
> 
> Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72.
> This enables support for Dynamic Frequency Scaling(DFS)
> 
> Signed-off-by: Keerthy <j-keerthy@ti.com>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> index ef73e6d7e858..7222c453096f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -48,6 +48,10 @@ cpu0: cpu@0 {
>  			d-cache-line-size = <64>;
>  			d-cache-sets = <256>;
>  			next-level-cache = <&L2_0>;
> +			clocks = <&k3_clks 202 2>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu0_opp_table>;
> +			#cooling-cells = <2>; /* min followed by max */
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -62,6 +66,30 @@ cpu1: cpu@1 {
>  			d-cache-line-size = <64>;
>  			d-cache-sets = <256>;
>  			next-level-cache = <&L2_0>;
> +			clocks = <&k3_clks 203 0>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu0_opp_table>;
> +			#cooling-cells = <2>; /* min followed by max */
> +		};
> +	};
> +
> +	cpu0_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +
> +		opp4-2000000000 {
> +			opp-hz = /bits/ 64 <2000000000>;
> +		};
> +
> +		opp3-1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +		};
> +
> +		opp2-1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +		};
> +
> +		opp1-750000000 {
> +			opp-hz = /bits/ 64 <750000000>;
>  		};
>  	};
>  
> -- 
> 2.34.1
> 

Are you sure this is correct to enable all OPPs without efuse bit checks?

https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
7.5 Operating Performance Points
DRA821xC operates only upto 750MHz
DRA821xE at 1GHz
DRA821xL upto 1.5GHz and
DRA821xT upto 2GHz

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72

[Kumar, Udit]

On 8/10/2023 12:39 AM, Nishanth Menon wrote:
> On 23:09-20230809, Apurva Nandan wrote:
>> From: Keerthy <j-keerthy@ti.com>
>>
>> Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72.
>> This enables support for Dynamic Frequency Scaling(DFS)
>>
>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++
>>   1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
>> index ef73e6d7e858..7222c453096f 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
>> @@ -48,6 +48,10 @@ cpu0: cpu@0 {
>>   			d-cache-line-size = <64>;
>>   			d-cache-sets = <256>;
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&k3_clks 202 2>;
>> +			clock-names = "cpu";
>> +			operating-points-v2 = <&cpu0_opp_table>;
>> +			#cooling-cells = <2>; /* min followed by max */
>>   		};
>>   
>>   		cpu1: cpu@1 {
>> @@ -62,6 +66,30 @@ cpu1: cpu@1 {
>>   			d-cache-line-size = <64>;
>>   			d-cache-sets = <256>;
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&k3_clks 203 0>;
>> +			clock-names = "cpu";
>> +			operating-points-v2 = <&cpu0_opp_table>;
>> +			#cooling-cells = <2>; /* min followed by max */
>> +		};
>> +	};
>> +
>> +	cpu0_opp_table: opp-table {
>> +		compatible = "operating-points-v2";
>> +
>> +		opp4-2000000000 {
>> +			opp-hz = /bits/ 64 <2000000000>;
>> +		};
>> +
>> +		opp3-1500000000 {
>> +			opp-hz = /bits/ 64 <1500000000>;
>> +		};
>> +
>> +		opp2-1000000000 {
>> +			opp-hz = /bits/ 64 <1000000000>;
>> +		};
>> +
>> +		opp1-750000000 {
>> +			opp-hz = /bits/ 64 <750000000>;
>>   		};
>>   	};
>>   
>> -- 
>> 2.34.1
>>
> Are you sure this is correct to enable all OPPs without efuse bit checks?
>
> https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
> 7.5 Operating Performance Points
> DRA821xC operates only upto 750MHz
> DRA821xE at 1GHz
> DRA821xL upto 1.5GHz and
> DRA821xT upto 2GHz

Looks, top SKUs is considered here .

After detecting which SKU we are running (I hope TRM should have this 
information- through efuse or some other register)

I think, we can follow two approaches.

1) have OPP table for each SKU and select based SKUs type or

2) Do run time fixup by u-boot based upon SKU type

Re: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72

[Nishanth Menon]

On 17:23-20230810, Kumar, Udit wrote:
[..]
> > > +		opp1-750000000 {
> > > +			opp-hz = /bits/ 64 <750000000>;
> > >   		};
> > >   	};
> > > -- 
> > > 2.34.1
> > > 
> > Are you sure this is correct to enable all OPPs without efuse bit checks?
> > 
> > https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
> > 7.5 Operating Performance Points
> > DRA821xC operates only upto 750MHz
> > DRA821xE at 1GHz
> > DRA821xL upto 1.5GHz and
> > DRA821xT upto 2GHz
> 
> Looks, top SKUs is considered here .
> 
> After detecting which SKU we are running (I hope TRM should have this
> information- through efuse or some other register)
> 
> I think, we can follow two approaches.

Both of these are wrong approaches.

> 
> 1) have OPP table for each SKU and select based SKUs type or

This proliferates cpu dtsi to make it hard to manage

> 
> 2) Do run time fixup by u-boot based upon SKU type

This wont work:

a) in u-boot's falcon boot mode and puts unrelated responsibility to
bootloader (u-boot is not the only bootloader in the party here).
b) Further, the reason for doing the opp detection in the kernel is
due to the severity of consequence of attempting to run a lower rated
chip at higher frequency - PoH (Power on Hours) or physical damage can
result.
c) Finally, in a virtualized environment: TISCI will get DM (Device
Manager) to arbitrate between the each of the VM's request, but if
the VM's are'nt self sufficient, we will have DM making wrong choices
resulting in (b) condition again.

This is the reason why drivers/cpufreq/ti-cpufreq.c exists and all SoCs
that have OPPs from TI is handled in the kernel itself.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72

[Kumar, Udit]

On 8/10/2023 6:23 PM, Nishanth Menon wrote:
> On 17:23-20230810, Kumar, Udit wrote:
> [..]
>>>> +		opp1-750000000 {
>>>> +			opp-hz = /bits/ 64 <750000000>;
>>>>    		};
>>>>    	};
>>>> -- 
>>>> 2.34.1
>>>>
>>> [..]
>>> This wont work:
>>>
>>> a) in u-boot's falcon boot mode and puts unrelated responsibility to
>>> bootloader (u-boot is not the only bootloader in the party here).
>>> b) Further, the reason for doing the opp detection in the kernel is
>>> due to the severity of consequence of attempting to run a lower rated
>>> chip at higher frequency - PoH (Power on Hours) or physical damage can
>>> result.
>>> c) Finally, in a virtualized environment: TISCI will get DM (Device
>>> Manager) to arbitrate between the each of the VM's request, but if
>>> the VM's are'nt self sufficient, we will have DM making wrong choices
>>> resulting in (b) condition again.
>>>
>>> This is the reason why drivers/cpufreq/ti-cpufreq.c exists and all SoCs
>>> that have OPPs from TI is handled in the kernel itself.

Thanks to pointing to this driver.

[PATCH 3/3] arm64: dts: ti: k3-j7200-thermal: Add cooling maps and cpu_alert trip at 75C

[Apurva Nandan]

From: Keerthy <j-keerthy@ti.com>

Add cooling maps and mpu_alert trip at 75C

Note: mpu_alert trip value should adjusted based on the system load and
performance needs.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
index e7e3a643a6f0..eeb596727d48 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
@@ -28,6 +28,20 @@ mpu_crit: mpu-crit {
 				hysteresis = <2000>; /* milliCelsius */
 				type = "critical";
 			};
+
+			mpu_alert0: mpu_alert {
+				temperature = <75000>; /* millicelsius */
+				hysteresis = <5000>; /* millicelsius */
+				type = "passive";
+			};
+		};
+
+		cpu_cooling_maps: cooling-maps {
+			map0 {
+				trip = <&mpu_alert0>;
+				cooling-device =
+				<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
 		};
 	};
 
-- 
2.34.1