* [PATCH 00/10] Expand STM32MP2 family with new SoC and boards
@ 2025-02-10 15:20 Amelie Delaunay
2025-02-10 15:20 ` [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board Amelie Delaunay
` (9 more replies)
0 siblings, 10 replies; 24+ messages in thread
From: Amelie Delaunay @ 2025-02-10 15:20 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev,
Amelie Delaunay
Add STM32MP25 Discovery Kit board [1] STM32MP257F-DK. It is based on a
different package of STM32MP257 SoC than STM32MP257F-EV1, and has 4GB of
LPDDR4 instead of DDR4.
Introduce two new SoC families [2] with Arm Cortex-A35 and Cortex-M33,
in development:
- STM32MP23x SoCs family, with STM32MP231 (single Arm Cortex-A35),
STM32MP233 and STM32MP235 (dual Arm Cortex-A35) [3]. Add STM32MP235F-DK
board to demonstrate the differences with STM32MP257F-DK board;
- STM32MP21x SoCs family, based on Cortex-A35 single-core, with
STM32MP211, STM32MP213 and STM32MP215. Add STM32MP215F-DK board based on
STM32MP215 SoC, with 2GB of LPDDR4.
[1] https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
[2] https://www.st.com/en/microcontrollers-microprocessors/stm32-arm-cortex-mpus.html
[3] https://www.st.com/en/microcontrollers-microprocessors/stm32mp235.html
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
---
Alexandre Torgue (3):
arm64: dts: st: add stm32mp257f-dk board support
arm64: dts: st: introduce stm32mp23 SoCs family
arm64: dts: st: introduce stm32mp21 SoCs family
Amelie Delaunay (7):
dt-bindings: stm32: document stm32mp257f-dk board
arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP23 SoCs family
dt-bindings: stm32: document stm32mp235f-dk board
arm64: dts: st: add stm32mp235f-dk board support
arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family
dt-bindings: stm32: document stm32mp215f-dk board
arm64: dts: st: add stm32mp215f-dk board support
.../devicetree/bindings/arm/stm32/stm32.yaml | 13 +
arch/arm64/Kconfig.platforms | 4 +
arch/arm64/boot/dts/st/Makefile | 6 +-
arch/arm64/boot/dts/st/stm32mp211.dtsi | 130 +++
arch/arm64/boot/dts/st/stm32mp213.dtsi | 9 +
arch/arm64/boot/dts/st/stm32mp215.dtsi | 9 +
arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 49 +
arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp21xf.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp231.dtsi | 1216 ++++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp233.dtsi | 94 ++
arch/arm64/boot/dts/st/stm32mp235.dtsi | 16 +
arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 115 ++
arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp23xf.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 115 ++
16 files changed, 1807 insertions(+), 1 deletion(-)
---
base-commit: 8c6d469f524960a0f97ec74f1d9ac737a39c3f1e
change-id: 20250210-b4-stm32mp2_new_dts-8fddd389850a
Best regards,
--
Amelie Delaunay <amelie.delaunay@foss.st.com>
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay @ 2025-02-10 15:20 ` Amelie Delaunay 2025-02-11 18:19 ` Conor Dooley 2025-02-10 15:20 ` [PATCH 02/10] arm64: dts: st: add stm32mp257f-dk board support Amelie Delaunay ` (8 subsequent siblings) 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:20 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Add new entry for stm32mp257f-dk board. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 6825d965da3daf2b508fbd88e8c9d40e20ba1f59..7cf9c6be0388365e6bce5e34a00ccf0a0eaa89cf 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -180,6 +180,7 @@ properties: - description: ST STM32MP257 based Boards items: - enum: + - st,stm32mp257f-dk - st,stm32mp257f-ev1 - const: st,stm32mp257 -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board 2025-02-10 15:20 ` [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board Amelie Delaunay @ 2025-02-11 18:19 ` Conor Dooley 0 siblings, 0 replies; 24+ messages in thread From: Conor Dooley @ 2025-02-11 18:19 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev [-- Attachment #1: Type: text/plain, Size: 232 bytes --] On Mon, Feb 10, 2025 at 04:20:55PM +0100, Amelie Delaunay wrote: > Add new entry for stm32mp257f-dk board. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 02/10] arm64: dts: st: add stm32mp257f-dk board support 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay 2025-02-10 15:20 ` [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board Amelie Delaunay @ 2025-02-10 15:20 ` Amelie Delaunay 2025-02-10 15:20 ` [PATCH 03/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP23 SoCs family Amelie Delaunay ` (7 subsequent siblings) 9 siblings, 0 replies; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:20 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay From: Alexandre Torgue <alexandre.torgue@foss.st.com> Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/boot/dts/st/Makefile | 4 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 115 ++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 881fe1296c581621f1219dbfbb4b1e03179e0f6f..0cc12f2b1dfeea6510793ea26f599f767df77749 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb +dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp257f-dk.dtb \ + stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts new file mode 100644 index 0000000000000000000000000000000000000000..314c99a76654992ca094db56291ab73602712327 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-DK Discovery Board"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = <VOLTD_SCMI_STPMIC2_LDO7>; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 03/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP23 SoCs family 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay 2025-02-10 15:20 ` [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board Amelie Delaunay 2025-02-10 15:20 ` [PATCH 02/10] arm64: dts: st: add stm32mp257f-dk board support Amelie Delaunay @ 2025-02-10 15:20 ` Amelie Delaunay 2025-02-10 15:20 ` [PATCH 04/10] arm64: dts: st: introduce stm32mp23 " Amelie Delaunay ` (6 subsequent siblings) 9 siblings, 0 replies; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:20 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Expand config ARCH_STM32 with the new STM32MP23 SoCs family which is composed of STM32MP231, STM32MP233 and STM32MP235 SoCs. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84da36619ddb8dac55a4bfd96d65e3..844a39620cfea8bfc031a545d85e33894ef20994 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -323,6 +323,8 @@ config ARCH_STM32 STM32 family, including: - STM32MP25: - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. + - STM32MP23: + - STM32MP231, STM32MP233, STM32MP235. config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 04/10] arm64: dts: st: introduce stm32mp23 SoCs family 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (2 preceding siblings ...) 2025-02-10 15:20 ` [PATCH 03/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP23 SoCs family Amelie Delaunay @ 2025-02-10 15:20 ` Amelie Delaunay 2025-02-13 9:08 ` Krzysztof Kozlowski 2025-02-10 15:20 ` [PATCH 05/10] dt-bindings: stm32: document stm32mp235f-dk board Amelie Delaunay ` (5 subsequent siblings) 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:20 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay From: Alexandre Torgue <alexandre.torgue@foss.st.com> STM32MP23 family is composed of 3 SoCs defined as following: -STM32MP231: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS display. A second diversity layer exists for security features/ A35 frequency: -STM32MP23xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 1216 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp233.dtsi | 94 +++ arch/arm64/boot/dts/st/stm32mp235.dtsi | 16 + arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 + arch/arm64/boot/dts/st/stm32mp23xf.dtsi | 8 + 5 files changed, 1342 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..ee93f5412096a7cd30b228b85a5280a551fbfaf4 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -0,0 +1,1216 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/clock/st,stm32mp25-rcc.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/regulator/st,stm32mp25-regulator.h> +#include <dt-bindings/reset/st,stm32mp25-rcc.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clocks { + clk_dsi_txbyte: txbyteclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clk_rcbsec: clk-rcbsec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_vddio1: regulator@0 { + reg = <VOLTD_SCMI_VDDIO1>; + regulator-name = "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg = <VOLTD_SCMI_VDDIO2>; + regulator-name = "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg = <VOLTD_SCMI_VDDIO3>; + regulator-name = "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg = <VOLTD_SCMI_VDDIO4>; + regulator-name = "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg = <VOLTD_SCMI_UCPD>; + regulator-name = "vdd33ucpd"; + }; + scmi_vdda18adc: regulator@7 { + reg = <VOLTD_SCMI_ADC>; + regulator-name = "vdda18adc"; + }; + }; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&RET_PD>; + }; + + RET_PD: power-domain-retention { + #power-domain-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + hpdma: dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_HPDMA1>; + #dma-cells = <3>; + }; + + hpdma2: dma-controller@40410000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40410000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_HPDMA2>; + #dma-cells = <3>; + }; + + hpdma3: dma-controller@40420000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40420000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk CK_SCMI_HPDMA3>; + #dma-cells = <3>; + }; + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + i2s2: audio-controller@400b0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400b0000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x43 0x12>, + <&hpdma 52 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi2: spi@400b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x20 0x3012>, + <&hpdma 52 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + i2s3: audio-controller@400c0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400c0000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x43 0x12>, + <&hpdma 54 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x20 0x3012>, + <&hpdma 54 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spdifrx: audio-controller@400d0000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x400d0000 0x400>; + clocks = <&rcc CK_KER_SPDIFRX>; + clock-names = "kclk"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 71 0x43 0x212>, + <&hpdma 72 0x43 0x212>; + dma-names = "rx", "rx-ctrl"; + access-controllers = <&rifsc 30>; + status = "disabled"; + }; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART2>; + dmas = <&hpdma 11 0x20 0x10012>, + <&hpdma 12 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 32>; + status = "disabled"; + }; + + usart3: serial@400f0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400f0000 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART3>; + dmas = <&hpdma 13 0x20 0x10012>, + <&hpdma 14 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 33>; + status = "disabled"; + }; + + uart4: serial@40100000 { + compatible = "st,stm32h7-uart"; + reg = <0x40100000 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_UART4>; + dmas = <&hpdma 15 0x20 0x10012>, + <&hpdma 16 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 34>; + status = "disabled"; + }; + + uart5: serial@40110000 { + compatible = "st,stm32h7-uart"; + reg = <0x40110000 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_UART5>; + dmas = <&hpdma 17 0x20 0x10012>, + <&hpdma 18 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 35>; + status = "disabled"; + }; + + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&hpdma 27 0x20 0x3012>, + <&hpdma 28 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&hpdma 30 0x20 0x3012>, + <&hpdma 31 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&hpdma 45 0x20 0x3012>, + <&hpdma 46 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + usart6: serial@40220000 { + compatible = "st,stm32h7-uart"; + reg = <0x40220000 0x400>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART6>; + dmas = <&hpdma 19 0x20 0x10012>, + <&hpdma 20 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 36>; + status = "disabled"; + }; + + i2s1: audio-controller@40230000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x40230000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x43 0x12>, + <&hpdma 50 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi1: spi@40230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x20 0x3012>, + <&hpdma 50 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + dmas = <&hpdma 55 0x20 0x3012>, + <&hpdma 56 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + dmas = <&hpdma 57 0x20 0x3012>, + <&hpdma 58 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + sai1: sai@40290000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; + ranges = <0 0x40290000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI1>; + clock-names = "pclk"; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + access-controllers = <&rifsc 49>; + status = "disabled"; + + sai1a: audio-controller@40290004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 73 0x43 0x21>; + status = "disabled"; + }; + + sai1b: audio-controller@40290024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 74 0x43 0x12>; + status = "disabled"; + }; + }; + + sai2: sai@402a0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; + ranges = <0 0x402a0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI2>; + clock-names = "pclk"; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + access-controllers = <&rifsc 50>; + status = "disabled"; + + sai2a: audio-controller@402a0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 75 0x43 0x21>; + status = "disabled"; + }; + + sai2b: audio-controller@402a0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 76 0x43 0x12>; + status = "disabled"; + }; + }; + + sai3: sai@402b0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; + ranges = <0 0x402b0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI3>; + clock-names = "pclk"; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI3_R>; + access-controllers = <&rifsc 51>; + status = "disabled"; + + sai3a: audio-controller@402b0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 77 0x43 0x21>; + status = "disabled"; + }; + + sai3b: audio-controller@502b0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 78 0x43 0x12>; + status = "disabled"; + }; + }; + + usart1: serial@40330000 { + compatible = "st,stm32h7-uart"; + reg = <0x40330000 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_USART1>; + dmas = <&hpdma 9 0x20 0x10012>, + <&hpdma 10 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 31>; + status = "disabled"; + }; + + sai4: sai@40340000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; + ranges = <0 0x40340000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI4>; + clock-names = "pclk"; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI4_R>; + access-controllers = <&rifsc 52>; + status = "disabled"; + + sai4a: audio-controller@40340004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 79 0x63 0x21>; + status = "disabled"; + }; + + sai4b: audio-controller@40340024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 80 0x43 0x12>; + status = "disabled"; + }; + }; + + uart7: serial@40370000 { + compatible = "st,stm32h7-uart"; + reg = <0x40370000 0x400>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_UART7>; + dmas = <&hpdma 21 0x20 0x10012>, + <&hpdma 22 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 37>; + status = "disabled"; + }; + + rng: rng@42020000 { + compatible = "st,stm32mp25-rng"; + reg = <0x42020000 0x400>; + clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; + clock-names = "core", "bus"; + resets = <&rcc RNG_R>; + access-controllers = <&rifsc 92>; + status = "disabled"; + }; + + spi8: spi@46020000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + dmas = <&hpdma 171 0x20 0x3012>, + <&hpdma 172 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + interrupt-names = "event"; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&hpdma 168 0x20 0x3012>, + <&hpdma 169 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 48>; + status = "disabled"; + }; + + csi: csi@48020000 { + compatible = "st,stm32mp25-csi"; + reg = <0x48020000 0x2000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc CSI_R>; + clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, + <&rcc CK_KER_CSIPHY>; + clock-names = "pclk", "txesc", "csi2phy"; + access-controllers = <&rifsc 86>; + status = "disabled"; + }; + + dcmipp: dcmipp@48030000 { + compatible = "st,stm32mp25-dcmipp"; + reg = <0x48030000 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc DCMIPP_R>; + clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; + clock-names = "kclk", "mclk"; + access-controllers = <&rifsc 87>; + status = "disabled"; + }; + + sdmmc1: mmc@48220000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00353180>; + reg = <0x48220000 0x400>, <0x44230400 0x8>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SDMMC1 >; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + access-controllers = <&rifsc 76>; + status = "disabled"; + }; + + ethernet1: ethernet@482c0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482c0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH1_MAC>, + <&rcc CK_ETH1_TX>, + <&rcc CK_ETH1_RX>, + <&rcc CK_KER_ETH1PTP>, + <&rcc CK_ETH1_STP>, + <&rcc CK_KER_ETH1>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_1>; + snps,mtl-tx-config = <&mtl_tx_setup_1>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3000>; + access-controllers = <&rifsc 60>; + status = "disabled"; + + mtl_rx_setup_1: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_1: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + }; + + bsec: efuse@44000000 { + compatible = "st,stm32mp25-bsec"; + reg = <0x44000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp@24 { + reg = <0x24 0x4>; + }; + + package_otp@1e8 { + reg = <0x1e8 0x1>; + bits = <0 3>; + }; + }; + + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + access-controllers = <&rifsc 156>; + }; + + exti1: interrupt-controller@44220000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x44220000 0x400>; + interrupts-extended = + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ + <0>, + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_80 */ + <0>, + <0>, + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + rtc: rtc@46000000 { + compatible = "st,stm32mp25-rtc"; + reg = <0x46000000 0x400>; + clocks = <&scmi_clk CK_SCMI_RTC>, + <&scmi_clk CK_SCMI_RTCCK>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x46230000 0x400>; + interrupts-extended = + <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <0>, + <0>, + <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp233.dtsi b/arch/arm64/boot/dts/st/stm32mp233.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4723c3d1f2018f22c4891f427c165f99c0909cf9 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp233.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp231.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + }; + + timer { + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&optee { + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + +&rifsc { + ethernet2: ethernet@482d0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482d0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH2_MAC>, + <&rcc CK_ETH2_TX>, + <&rcc CK_ETH2_RX>, + <&rcc CK_KER_ETH2PTP>, + <&rcc CK_ETH2_STP>, + <&rcc CK_KER_ETH2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_2>; + snps,mtl-tx-config = <&mtl_tx_setup_2>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3400>; + access-controllers = <&rifsc 61>; + status = "disabled"; + + mtl_rx_setup_2: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_2: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..2719c088dd594ba90f683d8809b54fecf471ba40 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp233.dtsi" + +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_BUS_VDEC>; + access-controllers = <&rifsc 89>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e33b00b424e1207dc6212e75235785f8c61e5055 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xf.dtsi b/arch/arm64/boot/dts/st/stm32mp23xf.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e33b00b424e1207dc6212e75235785f8c61e5055 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 04/10] arm64: dts: st: introduce stm32mp23 SoCs family 2025-02-10 15:20 ` [PATCH 04/10] arm64: dts: st: introduce stm32mp23 " Amelie Delaunay @ 2025-02-13 9:08 ` Krzysztof Kozlowski 2025-02-14 14:12 ` Amelie Delaunay 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-13 9:08 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On Mon, Feb 10, 2025 at 04:20:58PM +0100, Amelie Delaunay wrote: > From: Alexandre Torgue <alexandre.torgue@foss.st.com> > > STM32MP23 family is composed of 3 SoCs defined as following: > > -STM32MP231: common part composed of 1*Cortex-A35, common peripherals > like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... > > -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. > > -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS > display. > > A second diversity layer exists for security features/ A35 frequency: > -STM32MP23xY, "Y" gives information: > -Y = A means A35@1.2GHz + no cryp IP and no secure boot. > -Y = C means A35@1.2GHz + cryp IP and secure boot. > -Y = D means A35@1.5GHz + no cryp IP and no secure boot. > -Y = F means A35@1.5GHz + cryp IP and secure boot. > > Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > arch/arm64/boot/dts/st/stm32mp231.dtsi | 1216 +++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/st/stm32mp233.dtsi | 94 +++ > arch/arm64/boot/dts/st/stm32mp235.dtsi | 16 + > arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 + > arch/arm64/boot/dts/st/stm32mp23xf.dtsi | 8 + > 5 files changed, 1342 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..ee93f5412096a7cd30b228b85a5280a551fbfaf4 > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi > @@ -0,0 +1,1216 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved > + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. > + */ > +#include <dt-bindings/clock/st,stm32mp25-rcc.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/regulator/st,stm32mp25-regulator.h> > +#include <dt-bindings/reset/st,stm32mp25-rcc.h> > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a35"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + power-domains = <&CPU_PD0>; > + power-domain-names = "psci"; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a35-pmu"; > + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>; > + interrupt-parent = <&intc>; > + }; > + > + arm_wdt: watchdog { > + compatible = "arm,smc-wdt"; > + arm,smc-id = <0xb200005a>; > + status = "disabled"; > + }; > + > + clocks { Drop > + clk_dsi_txbyte: txbyteclk { Use consistent naming style. Either prefix or suffix. Or better, use what is recommended. See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1 > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <0>; > + }; > + > + clk_rcbsec: clk-rcbsec { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <64000000>; > + }; > + }; > + > + firmware { > + optee: optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + interrupt-parent = <&intc>; > + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + scmi { > + compatible = "linaro,scmi-optee"; > + #address-cells = <1>; > + #size-cells = <0>; > + linaro,optee-channel-id = <0>; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > + > + scmi_reset: protocol@16 { > + reg = <0x16>; > + #reset-cells = <1>; > + }; > + > + scmi_voltd: protocol@17 { > + reg = <0x17>; > + > + scmi_regu: regulators { > + #address-cells = <1>; > + #size-cells = <0>; > + > + scmi_vddio1: regulator@0 { > + reg = <VOLTD_SCMI_VDDIO1>; > + regulator-name = "vddio1"; > + }; > + scmi_vddio2: regulator@1 { > + reg = <VOLTD_SCMI_VDDIO2>; > + regulator-name = "vddio2"; > + }; > + scmi_vddio3: regulator@2 { > + reg = <VOLTD_SCMI_VDDIO3>; > + regulator-name = "vddio3"; > + }; > + scmi_vddio4: regulator@3 { > + reg = <VOLTD_SCMI_VDDIO4>; > + regulator-name = "vddio4"; > + }; > + scmi_vdd33ucpd: regulator@5 { > + reg = <VOLTD_SCMI_UCPD>; > + regulator-name = "vdd33ucpd"; > + }; > + scmi_vdda18adc: regulator@7 { > + reg = <VOLTD_SCMI_ADC>; > + regulator-name = "vdda18adc"; > + }; > + }; > + }; > + }; > + }; > + > + intc: interrupt-controller@4ac00000 { Part of Soc most likely. > + compatible = "arm,cortex-a7-gic"; > + #interrupt-cells = <3>; > + #address-cells = <1>; > + interrupt-controller; > + reg = <0x0 0x4ac10000 0x0 0x1000>, > + <0x0 0x4ac20000 0x0 0x2000>, > + <0x0 0x4ac40000 0x0 0x2000>, > + <0x0 0x4ac60000 0x0 0x2000>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + > + CPU_PD0: power-domain-cpu0 { All labels are always lowercase. > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + }; > + > + CLUSTER_PD: power-domain-cluster { > + #power-domain-cells = <0>; > + power-domains = <&RET_PD>; > + }; > + > + RET_PD: power-domain-retention { > + #power-domain-cells = <0>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&intc>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > + always-on; > + }; > + > + soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&intc>; > + ranges = <0x0 0x0 0x0 0x80000000>; Same comments as for all other patches. > + > + hpdma: dma-controller@40400000 { > + compatible = "st,stm32mp25-dma3"; > + reg = <0x40400000 0x1000>; > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk CK_SCMI_HPDMA1>; > + #dma-cells = <3>; > + }; > + > + hpdma2: dma-controller@40410000 { > + compatible = "st,stm32mp25-dma3"; > + reg = <0x40410000 0x1000>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk CK_SCMI_HPDMA2>; > + #dma-cells = <3>; > + }; > + > + hpdma3: dma-controller@40420000 { > + compatible = "st,stm32mp25-dma3"; > + reg = <0x40420000 0x1000>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk CK_SCMI_HPDMA3>; > + #dma-cells = <3>; > + }; > + > + rifsc: bus@42080000 { > + compatible = "st,stm32mp25-rifsc", "simple-bus"; > + reg = <0x42080000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + #access-controller-cells = <1>; > + ranges; > + > + i2s2: audio-controller@400b0000 { Confusing: device has address outside of the bus. What does the bus address represent? > + compatible = "st,stm32mp25-i2s"; > + reg = <0x400b0000 0x400>; > + #sound-dai-cells = <0>; > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; > + clock-names = "pclk", "i2sclk"; > + resets = <&rcc SPI2_R>; > + dmas = <&hpdma 51 0x43 0x12>, > + <&hpdma 52 0x43 0x21>; > + dma-names = "rx", "tx"; > + access-controllers = <&rifsc 23>; > + status = "disabled"; > + }; > + ... > + sdmmc1: mmc@48220000 { > + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; > + arm,primecell-periphid = <0x00353180>; > + reg = <0x48220000 0x400>, <0x44230400 0x8>; > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&rcc CK_KER_SDMMC1 >; > + clock-names = "apb_pclk"; > + resets = <&rcc SDMMC1_R>; > + cap-sd-highspeed; > + cap-mmc-highspeed; > + max-frequency = <120000000>; > + access-controllers = <&rifsc 76>; > + status = "disabled"; > + }; > + > + ethernet1: ethernet@482c0000 { > + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; > + reg = <0x482c0000 0x4000>; > + reg-names = "stmmaceth"; > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; Why extended? > + interrupt-names = "macirq"; > + clock-names = "stmmaceth", > + "mac-clk-tx", > + "mac-clk-rx", > + "ptp_ref", > + "ethstp", > + "eth-ck"; ... > + rcc: clock-controller@44200000 { > + compatible = "st,stm32mp25-rcc"; > + reg = <0x44200000 0x10000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + clocks = <&scmi_clk CK_SCMI_HSE>, > + <&scmi_clk CK_SCMI_HSI>, > + <&scmi_clk CK_SCMI_MSI>, > + <&scmi_clk CK_SCMI_LSE>, > + <&scmi_clk CK_SCMI_LSI>, > + <&scmi_clk CK_SCMI_HSE_DIV2>, > + <&scmi_clk CK_SCMI_ICN_HS_MCU>, > + <&scmi_clk CK_SCMI_ICN_LS_MCU>, > + <&scmi_clk CK_SCMI_ICN_SDMMC>, > + <&scmi_clk CK_SCMI_ICN_DDR>, > + <&scmi_clk CK_SCMI_ICN_DISPLAY>, > + <&scmi_clk CK_SCMI_ICN_HSL>, > + <&scmi_clk CK_SCMI_ICN_NIC>, > + <&scmi_clk CK_SCMI_ICN_VID>, > + <&scmi_clk CK_SCMI_FLEXGEN_07>, > + <&scmi_clk CK_SCMI_FLEXGEN_08>, > + <&scmi_clk CK_SCMI_FLEXGEN_09>, > + <&scmi_clk CK_SCMI_FLEXGEN_10>, > + <&scmi_clk CK_SCMI_FLEXGEN_11>, > + <&scmi_clk CK_SCMI_FLEXGEN_12>, > + <&scmi_clk CK_SCMI_FLEXGEN_13>, > + <&scmi_clk CK_SCMI_FLEXGEN_14>, > + <&scmi_clk CK_SCMI_FLEXGEN_15>, > + <&scmi_clk CK_SCMI_FLEXGEN_16>, > + <&scmi_clk CK_SCMI_FLEXGEN_17>, > + <&scmi_clk CK_SCMI_FLEXGEN_18>, > + <&scmi_clk CK_SCMI_FLEXGEN_19>, > + <&scmi_clk CK_SCMI_FLEXGEN_20>, > + <&scmi_clk CK_SCMI_FLEXGEN_21>, > + <&scmi_clk CK_SCMI_FLEXGEN_22>, > + <&scmi_clk CK_SCMI_FLEXGEN_23>, > + <&scmi_clk CK_SCMI_FLEXGEN_24>, > + <&scmi_clk CK_SCMI_FLEXGEN_25>, > + <&scmi_clk CK_SCMI_FLEXGEN_26>, > + <&scmi_clk CK_SCMI_FLEXGEN_27>, > + <&scmi_clk CK_SCMI_FLEXGEN_28>, > + <&scmi_clk CK_SCMI_FLEXGEN_29>, > + <&scmi_clk CK_SCMI_FLEXGEN_30>, > + <&scmi_clk CK_SCMI_FLEXGEN_31>, > + <&scmi_clk CK_SCMI_FLEXGEN_32>, > + <&scmi_clk CK_SCMI_FLEXGEN_33>, > + <&scmi_clk CK_SCMI_FLEXGEN_34>, > + <&scmi_clk CK_SCMI_FLEXGEN_35>, > + <&scmi_clk CK_SCMI_FLEXGEN_36>, > + <&scmi_clk CK_SCMI_FLEXGEN_37>, > + <&scmi_clk CK_SCMI_FLEXGEN_38>, > + <&scmi_clk CK_SCMI_FLEXGEN_39>, > + <&scmi_clk CK_SCMI_FLEXGEN_40>, > + <&scmi_clk CK_SCMI_FLEXGEN_41>, > + <&scmi_clk CK_SCMI_FLEXGEN_42>, > + <&scmi_clk CK_SCMI_FLEXGEN_43>, > + <&scmi_clk CK_SCMI_FLEXGEN_44>, > + <&scmi_clk CK_SCMI_FLEXGEN_45>, > + <&scmi_clk CK_SCMI_FLEXGEN_46>, > + <&scmi_clk CK_SCMI_FLEXGEN_47>, > + <&scmi_clk CK_SCMI_FLEXGEN_48>, > + <&scmi_clk CK_SCMI_FLEXGEN_49>, > + <&scmi_clk CK_SCMI_FLEXGEN_50>, > + <&scmi_clk CK_SCMI_FLEXGEN_51>, > + <&scmi_clk CK_SCMI_FLEXGEN_52>, > + <&scmi_clk CK_SCMI_FLEXGEN_53>, > + <&scmi_clk CK_SCMI_FLEXGEN_54>, > + <&scmi_clk CK_SCMI_FLEXGEN_55>, > + <&scmi_clk CK_SCMI_FLEXGEN_56>, > + <&scmi_clk CK_SCMI_FLEXGEN_57>, > + <&scmi_clk CK_SCMI_FLEXGEN_58>, > + <&scmi_clk CK_SCMI_FLEXGEN_59>, > + <&scmi_clk CK_SCMI_FLEXGEN_60>, > + <&scmi_clk CK_SCMI_FLEXGEN_61>, > + <&scmi_clk CK_SCMI_FLEXGEN_62>, > + <&scmi_clk CK_SCMI_FLEXGEN_63>, > + <&scmi_clk CK_SCMI_ICN_APB1>, > + <&scmi_clk CK_SCMI_ICN_APB2>, > + <&scmi_clk CK_SCMI_ICN_APB3>, > + <&scmi_clk CK_SCMI_ICN_APB4>, > + <&scmi_clk CK_SCMI_ICN_APBDBG>, > + <&scmi_clk CK_SCMI_TIMG1>, > + <&scmi_clk CK_SCMI_TIMG2>, > + <&scmi_clk CK_SCMI_PLL3>, > + <&clk_dsi_txbyte>; > + access-controllers = <&rifsc 156>; > + }; > + > + exti1: interrupt-controller@44220000 { > + compatible = "st,stm32mp1-exti", "syscon"; > + interrupt-controller; > + #interrupt-cells = <2>; > + reg = <0x44220000 0x400>; > + interrupts-extended = Why extended? > + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ > + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ > + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, > + <0>, /* EXTI_20 */ > + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ > + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + <0>, > + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ > + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, > + <0>, /* EXTI_60 */ > + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, > + <0>, > + <0>, > + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, > + <0>, > + <0>, > + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <0>, > + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ > + <0>, > + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, > + <0>, /* EXTI_80 */ > + <0>, > + <0>, > + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + syscfg: syscon@44230000 { > + compatible = "st,stm32mp25-syscfg", "syscon"; > + reg = <0x44230000 0x10000>; > + }; > + > + pinctrl: pinctrl@44240000 { > + #address-cells = <1>; > + #size-cells = <1>; Please fix coding style everywhere here. > + compatible = "st,stm32mp257-pinctrl"; > + ranges = <0 0x44240000 0xa0400>; > + interrupt-parent = <&exti1>; > + st,syscfg = <&exti1 0x60 0xff>; > + pins-are-numbered; > + ... > diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..e33b00b424e1207dc6212e75235785f8c61e5055 > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved > + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. > + */ > + What is the point of this file? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 04/10] arm64: dts: st: introduce stm32mp23 SoCs family 2025-02-13 9:08 ` Krzysztof Kozlowski @ 2025-02-14 14:12 ` Amelie Delaunay 0 siblings, 0 replies; 24+ messages in thread From: Amelie Delaunay @ 2025-02-14 14:12 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On 2/13/25 10:08, Krzysztof Kozlowski wrote: > On Mon, Feb 10, 2025 at 04:20:58PM +0100, Amelie Delaunay wrote: >> From: Alexandre Torgue <alexandre.torgue@foss.st.com> >> >> STM32MP23 family is composed of 3 SoCs defined as following: >> >> -STM32MP231: common part composed of 1*Cortex-A35, common peripherals >> like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... >> >> -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. >> >> -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS >> display. >> >> A second diversity layer exists for security features/ A35 frequency: >> -STM32MP23xY, "Y" gives information: >> -Y = A means A35@1.2GHz + no cryp IP and no secure boot. >> -Y = C means A35@1.2GHz + cryp IP and secure boot. >> -Y = D means A35@1.5GHz + no cryp IP and no secure boot. >> -Y = F means A35@1.5GHz + cryp IP and secure boot. >> >> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> >> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> >> --- >> arch/arm64/boot/dts/st/stm32mp231.dtsi | 1216 +++++++++++++++++++++++++++++++ >> arch/arm64/boot/dts/st/stm32mp233.dtsi | 94 +++ >> arch/arm64/boot/dts/st/stm32mp235.dtsi | 16 + >> arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 + >> arch/arm64/boot/dts/st/stm32mp23xf.dtsi | 8 + >> 5 files changed, 1342 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi >> new file mode 100644 >> index 0000000000000000000000000000000000000000..ee93f5412096a7cd30b228b85a5280a551fbfaf4 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi >> @@ -0,0 +1,1216 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved >> + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. >> + */ >> +#include <dt-bindings/clock/st,stm32mp25-rcc.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/regulator/st,stm32mp25-regulator.h> >> +#include <dt-bindings/reset/st,stm32mp25-rcc.h> >> + >> +/ { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a35"; >> + device_type = "cpu"; >> + reg = <0>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD0>; >> + power-domain-names = "psci"; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a35-pmu"; >> + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>; >> + interrupt-parent = <&intc>; >> + }; >> + >> + arm_wdt: watchdog { >> + compatible = "arm,smc-wdt"; >> + arm,smc-id = <0xb200005a>; >> + status = "disabled"; >> + }; >> + >> + clocks { > > Drop > >> + clk_dsi_txbyte: txbyteclk { > > Use consistent naming style. Either prefix or suffix. Or better, use > what is recommended. > > See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1 > Will use the recommended style: clk_dsi_txbyte: clock-0 clk_rcbsec: clock-64000000 >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <0>; >> + }; >> + >> + clk_rcbsec: clk-rcbsec { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <64000000>; >> + }; >> + }; >> + >> + firmware { >> + optee: optee { >> + compatible = "linaro,optee-tz"; >> + method = "smc"; >> + interrupt-parent = <&intc>; >> + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; >> + }; >> + >> + scmi { >> + compatible = "linaro,scmi-optee"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + linaro,optee-channel-id = <0>; >> + >> + scmi_clk: protocol@14 { >> + reg = <0x14>; >> + #clock-cells = <1>; >> + }; >> + >> + scmi_reset: protocol@16 { >> + reg = <0x16>; >> + #reset-cells = <1>; >> + }; >> + >> + scmi_voltd: protocol@17 { >> + reg = <0x17>; >> + >> + scmi_regu: regulators { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + scmi_vddio1: regulator@0 { >> + reg = <VOLTD_SCMI_VDDIO1>; >> + regulator-name = "vddio1"; >> + }; >> + scmi_vddio2: regulator@1 { >> + reg = <VOLTD_SCMI_VDDIO2>; >> + regulator-name = "vddio2"; >> + }; >> + scmi_vddio3: regulator@2 { >> + reg = <VOLTD_SCMI_VDDIO3>; >> + regulator-name = "vddio3"; >> + }; >> + scmi_vddio4: regulator@3 { >> + reg = <VOLTD_SCMI_VDDIO4>; >> + regulator-name = "vddio4"; >> + }; >> + scmi_vdd33ucpd: regulator@5 { >> + reg = <VOLTD_SCMI_UCPD>; >> + regulator-name = "vdd33ucpd"; >> + }; >> + scmi_vdda18adc: regulator@7 { >> + reg = <VOLTD_SCMI_ADC>; >> + regulator-name = "vdda18adc"; >> + }; >> + }; >> + }; >> + }; >> + }; >> + >> + intc: interrupt-controller@4ac00000 { > > Part of Soc most likely. > Right. >> + compatible = "arm,cortex-a7-gic"; >> + #interrupt-cells = <3>; >> + #address-cells = <1>; >> + interrupt-controller; >> + reg = <0x0 0x4ac10000 0x0 0x1000>, >> + <0x0 0x4ac20000 0x0 0x2000>, >> + <0x0 0x4ac40000 0x0 0x2000>, >> + <0x0 0x4ac60000 0x0 0x2000>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + >> + CPU_PD0: power-domain-cpu0 { > > All labels are always lowercase. > Sure. Wrongly inspired by the examples of https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/psci.yaml >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + }; >> + >> + CLUSTER_PD: power-domain-cluster { >> + #power-domain-cells = <0>; >> + power-domains = <&RET_PD>; >> + }; >> + >> + RET_PD: power-domain-retention { >> + #power-domain-cells = <0>; >> + }; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupt-parent = <&intc>; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; >> + always-on; >> + }; >> + >> + soc@0 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupt-parent = <&intc>; >> + ranges = <0x0 0x0 0x0 0x80000000>; > > Same comments as for all other patches. > Ok. >> + >> + hpdma: dma-controller@40400000 { >> + compatible = "st,stm32mp25-dma3"; >> + reg = <0x40400000 0x1000>; >> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&scmi_clk CK_SCMI_HPDMA1>; >> + #dma-cells = <3>; >> + }; >> + >> + hpdma2: dma-controller@40410000 { >> + compatible = "st,stm32mp25-dma3"; >> + reg = <0x40410000 0x1000>; >> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&scmi_clk CK_SCMI_HPDMA2>; >> + #dma-cells = <3>; >> + }; >> + >> + hpdma3: dma-controller@40420000 { >> + compatible = "st,stm32mp25-dma3"; >> + reg = <0x40420000 0x1000>; >> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&scmi_clk CK_SCMI_HPDMA3>; >> + #dma-cells = <3>; >> + }; >> + >> + rifsc: bus@42080000 { >> + compatible = "st,stm32mp25-rifsc", "simple-bus"; >> + reg = <0x42080000 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + #access-controller-cells = <1>; >> + ranges; >> + >> + i2s2: audio-controller@400b0000 { > > Confusing: device has address outside of the bus. What does the bus > address represent? > RIFSC is a Resource Isolation Framework Security Controller, aka a firewall, on STM32 platforms. It manages isolation of STM32 hardware resources like memory and peripherals. The bus adresses of rifsc child nodes represent the address of the peripherals on the AHB bus, while the access-controllers propriety refers to RIFSC firewall ID. Firewall is already used in - arch/arm/boot/dts/st/stm32mp131.dtsi - arch/arm/boot/dts/st/stm32mp151.dtsi - arch/arm64/boot/dts/st/stm32mp251.dtsi This was discussed here: https://lore.kernel.org/linux-arm-kernel/20240105130404.301172-1-gatien.chevallier@foss.st.com/T/ >> + compatible = "st,stm32mp25-i2s"; >> + reg = <0x400b0000 0x400>; >> + #sound-dai-cells = <0>; >> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; >> + clock-names = "pclk", "i2sclk"; >> + resets = <&rcc SPI2_R>; >> + dmas = <&hpdma 51 0x43 0x12>, >> + <&hpdma 52 0x43 0x21>; >> + dma-names = "rx", "tx"; >> + access-controllers = <&rifsc 23>; >> + status = "disabled"; >> + }; >> + > > ... > >> + sdmmc1: mmc@48220000 { >> + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; >> + arm,primecell-periphid = <0x00353180>; >> + reg = <0x48220000 0x400>, <0x44230400 0x8>; >> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&rcc CK_KER_SDMMC1 >; >> + clock-names = "apb_pclk"; >> + resets = <&rcc SDMMC1_R>; >> + cap-sd-highspeed; >> + cap-mmc-highspeed; >> + max-frequency = <120000000>; >> + access-controllers = <&rifsc 76>; >> + status = "disabled"; >> + }; >> + >> + ethernet1: ethernet@482c0000 { >> + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; >> + reg = <0x482c0000 0x4000>; >> + reg-names = "stmmaceth"; >> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; > > Why extended? > ethernet could be a wakeup source, but for that, it requires using an interrupt from EXTI controller, not GIC. The use of interrupts-extended property is a bit too advanced here, should be interrupts, unless all wakeup stuff is added. >> + interrupt-names = "macirq"; >> + clock-names = "stmmaceth", >> + "mac-clk-tx", >> + "mac-clk-rx", >> + "ptp_ref", >> + "ethstp", >> + "eth-ck"; > > ... > >> + rcc: clock-controller@44200000 { >> + compatible = "st,stm32mp25-rcc"; >> + reg = <0x44200000 0x10000>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + clocks = <&scmi_clk CK_SCMI_HSE>, >> + <&scmi_clk CK_SCMI_HSI>, >> + <&scmi_clk CK_SCMI_MSI>, >> + <&scmi_clk CK_SCMI_LSE>, >> + <&scmi_clk CK_SCMI_LSI>, >> + <&scmi_clk CK_SCMI_HSE_DIV2>, >> + <&scmi_clk CK_SCMI_ICN_HS_MCU>, >> + <&scmi_clk CK_SCMI_ICN_LS_MCU>, >> + <&scmi_clk CK_SCMI_ICN_SDMMC>, >> + <&scmi_clk CK_SCMI_ICN_DDR>, >> + <&scmi_clk CK_SCMI_ICN_DISPLAY>, >> + <&scmi_clk CK_SCMI_ICN_HSL>, >> + <&scmi_clk CK_SCMI_ICN_NIC>, >> + <&scmi_clk CK_SCMI_ICN_VID>, >> + <&scmi_clk CK_SCMI_FLEXGEN_07>, >> + <&scmi_clk CK_SCMI_FLEXGEN_08>, >> + <&scmi_clk CK_SCMI_FLEXGEN_09>, >> + <&scmi_clk CK_SCMI_FLEXGEN_10>, >> + <&scmi_clk CK_SCMI_FLEXGEN_11>, >> + <&scmi_clk CK_SCMI_FLEXGEN_12>, >> + <&scmi_clk CK_SCMI_FLEXGEN_13>, >> + <&scmi_clk CK_SCMI_FLEXGEN_14>, >> + <&scmi_clk CK_SCMI_FLEXGEN_15>, >> + <&scmi_clk CK_SCMI_FLEXGEN_16>, >> + <&scmi_clk CK_SCMI_FLEXGEN_17>, >> + <&scmi_clk CK_SCMI_FLEXGEN_18>, >> + <&scmi_clk CK_SCMI_FLEXGEN_19>, >> + <&scmi_clk CK_SCMI_FLEXGEN_20>, >> + <&scmi_clk CK_SCMI_FLEXGEN_21>, >> + <&scmi_clk CK_SCMI_FLEXGEN_22>, >> + <&scmi_clk CK_SCMI_FLEXGEN_23>, >> + <&scmi_clk CK_SCMI_FLEXGEN_24>, >> + <&scmi_clk CK_SCMI_FLEXGEN_25>, >> + <&scmi_clk CK_SCMI_FLEXGEN_26>, >> + <&scmi_clk CK_SCMI_FLEXGEN_27>, >> + <&scmi_clk CK_SCMI_FLEXGEN_28>, >> + <&scmi_clk CK_SCMI_FLEXGEN_29>, >> + <&scmi_clk CK_SCMI_FLEXGEN_30>, >> + <&scmi_clk CK_SCMI_FLEXGEN_31>, >> + <&scmi_clk CK_SCMI_FLEXGEN_32>, >> + <&scmi_clk CK_SCMI_FLEXGEN_33>, >> + <&scmi_clk CK_SCMI_FLEXGEN_34>, >> + <&scmi_clk CK_SCMI_FLEXGEN_35>, >> + <&scmi_clk CK_SCMI_FLEXGEN_36>, >> + <&scmi_clk CK_SCMI_FLEXGEN_37>, >> + <&scmi_clk CK_SCMI_FLEXGEN_38>, >> + <&scmi_clk CK_SCMI_FLEXGEN_39>, >> + <&scmi_clk CK_SCMI_FLEXGEN_40>, >> + <&scmi_clk CK_SCMI_FLEXGEN_41>, >> + <&scmi_clk CK_SCMI_FLEXGEN_42>, >> + <&scmi_clk CK_SCMI_FLEXGEN_43>, >> + <&scmi_clk CK_SCMI_FLEXGEN_44>, >> + <&scmi_clk CK_SCMI_FLEXGEN_45>, >> + <&scmi_clk CK_SCMI_FLEXGEN_46>, >> + <&scmi_clk CK_SCMI_FLEXGEN_47>, >> + <&scmi_clk CK_SCMI_FLEXGEN_48>, >> + <&scmi_clk CK_SCMI_FLEXGEN_49>, >> + <&scmi_clk CK_SCMI_FLEXGEN_50>, >> + <&scmi_clk CK_SCMI_FLEXGEN_51>, >> + <&scmi_clk CK_SCMI_FLEXGEN_52>, >> + <&scmi_clk CK_SCMI_FLEXGEN_53>, >> + <&scmi_clk CK_SCMI_FLEXGEN_54>, >> + <&scmi_clk CK_SCMI_FLEXGEN_55>, >> + <&scmi_clk CK_SCMI_FLEXGEN_56>, >> + <&scmi_clk CK_SCMI_FLEXGEN_57>, >> + <&scmi_clk CK_SCMI_FLEXGEN_58>, >> + <&scmi_clk CK_SCMI_FLEXGEN_59>, >> + <&scmi_clk CK_SCMI_FLEXGEN_60>, >> + <&scmi_clk CK_SCMI_FLEXGEN_61>, >> + <&scmi_clk CK_SCMI_FLEXGEN_62>, >> + <&scmi_clk CK_SCMI_FLEXGEN_63>, >> + <&scmi_clk CK_SCMI_ICN_APB1>, >> + <&scmi_clk CK_SCMI_ICN_APB2>, >> + <&scmi_clk CK_SCMI_ICN_APB3>, >> + <&scmi_clk CK_SCMI_ICN_APB4>, >> + <&scmi_clk CK_SCMI_ICN_APBDBG>, >> + <&scmi_clk CK_SCMI_TIMG1>, >> + <&scmi_clk CK_SCMI_TIMG2>, >> + <&scmi_clk CK_SCMI_PLL3>, >> + <&clk_dsi_txbyte>; >> + access-controllers = <&rifsc 156>; >> + }; >> + >> + exti1: interrupt-controller@44220000 { >> + compatible = "st,stm32mp1-exti", "syscon"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + reg = <0x44220000 0x400>; >> + interrupts-extended = > > Why extended? > EXTI is an interrupt dispatcher that routes each client interrupt either to GIC or to a wakeup-parent interrupt controller (not upstream yet). The mapping between EXTI interrupts and parents interrupts is not linear and has holes; together with the incoming need to address multi-parents, all this matches with the use of interrupts-extended. It is already used in - arch/arm/boot/dts/st/stm32mp131.dtsi - arch/arm/boot/dts/st/stm32mp151.dtsi - arch/arm64/boot/dts/st/stm32mp251.dtsi and reported in example 2 of the EXTI bindings. https://lore.kernel.org/all/20240415134926.1254428-3-antonio.borneo@foss.st.com/ >> + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ >> + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ >> + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, /* EXTI_20 */ >> + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ >> + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, >> + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ >> + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, /* EXTI_60 */ >> + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, >> + <0>, >> + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, >> + <0>, >> + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, >> + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ >> + <0>, >> + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, >> + <0>, /* EXTI_80 */ >> + <0>, >> + <0>, >> + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, >> + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + syscfg: syscon@44230000 { >> + compatible = "st,stm32mp25-syscfg", "syscon"; >> + reg = <0x44230000 0x10000>; >> + }; >> + >> + pinctrl: pinctrl@44240000 { >> + #address-cells = <1>; >> + #size-cells = <1>; > > Please fix coding style everywhere here. > > Ok. >> + compatible = "st,stm32mp257-pinctrl"; >> + ranges = <0 0x44240000 0xa0400>; >> + interrupt-parent = <&exti1>; >> + st,syscfg = <&exti1 0x60 0xff>; >> + pins-are-numbered; >> + > > ... > >> diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi >> new file mode 100644 >> index 0000000000000000000000000000000000000000..e33b00b424e1207dc6212e75235785f8c61e5055 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi >> @@ -0,0 +1,8 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved >> + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. >> + */ >> + > > What is the point of this file? > stm32mp23xc.dtsi and stm32mp23xf.dtsi are skeleton files pending cryptographic support. Same split is used on other STM32 MPUs: ./arch/arm/boot/dts/st/stm32mp13xc.dtsi ./arch/arm/boot/dts/st/stm32mp13xf.dtsi ./arch/arm/boot/dts/st/stm32mp15xc.dtsi ./arch/arm/boot/dts/st/stm32mp15xf.dtsi ./arch/arm64/boot/dts/st/stm32mp25xc.dtsi ./arch/arm64/boot/dts/st/stm32mp25xf.dtsi Regards, Amelie ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 05/10] dt-bindings: stm32: document stm32mp235f-dk board 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (3 preceding siblings ...) 2025-02-10 15:20 ` [PATCH 04/10] arm64: dts: st: introduce stm32mp23 " Amelie Delaunay @ 2025-02-10 15:20 ` Amelie Delaunay 2025-02-11 18:19 ` Conor Dooley 2025-02-10 15:21 ` [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support Amelie Delaunay ` (4 subsequent siblings) 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:20 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Add new entry for stm32mp235-dk board. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 7cf9c6be0388365e6bce5e34a00ccf0a0eaa89cf..9ffcba51c9207b5a1386c025f850bc594c915c8c 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -184,6 +184,12 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 + - description: ST STM32MP235 based Boards + items: + - enum: + - st,stm32mp235f-dk + - const: st,stm32mp235 + additionalProperties: true ... -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 05/10] dt-bindings: stm32: document stm32mp235f-dk board 2025-02-10 15:20 ` [PATCH 05/10] dt-bindings: stm32: document stm32mp235f-dk board Amelie Delaunay @ 2025-02-11 18:19 ` Conor Dooley 0 siblings, 0 replies; 24+ messages in thread From: Conor Dooley @ 2025-02-11 18:19 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev [-- Attachment #1: Type: text/plain, Size: 231 bytes --] On Mon, Feb 10, 2025 at 04:20:59PM +0100, Amelie Delaunay wrote: > Add new entry for stm32mp235-dk board. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (4 preceding siblings ...) 2025-02-10 15:20 ` [PATCH 05/10] dt-bindings: stm32: document stm32mp235f-dk board Amelie Delaunay @ 2025-02-10 15:21 ` Amelie Delaunay 2025-02-13 9:03 ` Krzysztof Kozlowski 2025-02-10 15:21 ` [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family Amelie Delaunay ` (3 subsequent siblings) 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Add STM32MP235F Discovery Kit board support. It embeds a STM32MP235FAK SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/boot/dts/st/Makefile | 1 + arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 115 ++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 0cc12f2b1dfeea6510793ea26f599f767df77749..06364152206997863d0991c25589de73c63494fb 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp235f-dk.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts new file mode 100644 index 0000000000000000000000000000000000000000..08e330d310749506c5b0e7a1fb2f80dfa134400a --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "stm32mp235.dtsi" +#include "stm32mp23xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP235F-DK Discovery Board"; + compatible = "st,stm32mp235f-dk", "st,stm32mp235"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = <BTN_1>; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + button-user-2 { + label = "User-2"; + linux,code = <BTN_2>; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = <VOLTD_SCMI_STPMIC2_LDO7>; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support 2025-02-10 15:21 ` [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support Amelie Delaunay @ 2025-02-13 9:03 ` Krzysztof Kozlowski 2025-02-14 14:13 ` Amelie Delaunay 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-13 9:03 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On Mon, Feb 10, 2025 at 04:21:00PM +0100, Amelie Delaunay wrote: > Add STM32MP235F Discovery Kit board support. It embeds a STM32MP235FAK > SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT > combo, DSI HDMI, LVDS connector ... > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > arch/arm64/boot/dts/st/Makefile | 1 + > arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 115 ++++++++++++++++++++++++++++++ > 2 files changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile > index 0cc12f2b1dfeea6510793ea26f599f767df77749..06364152206997863d0991c25589de73c63494fb 100644 > --- a/arch/arm64/boot/dts/st/Makefile > +++ b/arch/arm64/boot/dts/st/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0-only > dtb-$(CONFIG_ARCH_STM32) += \ > + stm32mp235f-dk.dtb \ > stm32mp257f-dk.dtb \ > stm32mp257f-ev1.dtb > diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts > new file mode 100644 > index 0000000000000000000000000000000000000000..08e330d310749506c5b0e7a1fb2f80dfa134400a > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts > @@ -0,0 +1,115 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved > + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/leds/common.h> > +#include "stm32mp235.dtsi" > +#include "stm32mp23xf.dtsi" > +#include "stm32mp25-pinctrl.dtsi" > +#include "stm32mp25xxak-pinctrl.dtsi" > + > +/ { > + model = "STMicroelectronics STM32MP235F-DK Discovery Board"; > + compatible = "st,stm32mp235f-dk", "st,stm32mp235"; > + > + aliases { > + serial0 = &usart2; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + > + button-user-1 { > + label = "User-1"; > + linux,code = <BTN_1>; > + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; > + status = "okay"; Where is it disabled? > + }; > + > + button-user-2 { > + label = "User-2"; > + linux,code = <BTN_2>; > + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; > + status = "okay"; Same question > + }; > + }; Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support 2025-02-13 9:03 ` Krzysztof Kozlowski @ 2025-02-14 14:13 ` Amelie Delaunay 0 siblings, 0 replies; 24+ messages in thread From: Amelie Delaunay @ 2025-02-14 14:13 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On 2/13/25 10:03, Krzysztof Kozlowski wrote: > On Mon, Feb 10, 2025 at 04:21:00PM +0100, Amelie Delaunay wrote: >> Add STM32MP235F Discovery Kit board support. It embeds a STM32MP235FAK >> SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT >> combo, DSI HDMI, LVDS connector ... >> >> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> >> --- >> arch/arm64/boot/dts/st/Makefile | 1 + >> arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 115 ++++++++++++++++++++++++++++++ >> 2 files changed, 116 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile >> index 0cc12f2b1dfeea6510793ea26f599f767df77749..06364152206997863d0991c25589de73c63494fb 100644 >> --- a/arch/arm64/boot/dts/st/Makefile >> +++ b/arch/arm64/boot/dts/st/Makefile >> @@ -1,4 +1,5 @@ >> # SPDX-License-Identifier: GPL-2.0-only >> dtb-$(CONFIG_ARCH_STM32) += \ >> + stm32mp235f-dk.dtb \ >> stm32mp257f-dk.dtb \ >> stm32mp257f-ev1.dtb >> diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts >> new file mode 100644 >> index 0000000000000000000000000000000000000000..08e330d310749506c5b0e7a1fb2f80dfa134400a >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts >> @@ -0,0 +1,115 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved >> + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. >> + */ >> + >> +/dts-v1/; >> + >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/input/input.h> >> +#include <dt-bindings/leds/common.h> >> +#include "stm32mp235.dtsi" >> +#include "stm32mp23xf.dtsi" >> +#include "stm32mp25-pinctrl.dtsi" >> +#include "stm32mp25xxak-pinctrl.dtsi" >> + >> +/ { >> + model = "STMicroelectronics STM32MP235F-DK Discovery Board"; >> + compatible = "st,stm32mp235f-dk", "st,stm32mp235"; >> + >> + aliases { >> + serial0 = &usart2; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + gpio-keys { >> + compatible = "gpio-keys"; >> + >> + button-user-1 { >> + label = "User-1"; >> + linux,code = <BTN_1>; >> + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; >> + status = "okay"; > > Where is it disabled? > >> + }; >> + >> + button-user-2 { >> + label = "User-2"; >> + linux,code = <BTN_2>; >> + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; >> + status = "okay"; > > Same question > >> + }; >> + }; > > Best regards, > Krzysztof > Will drop status property. Regards, Amelie ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (5 preceding siblings ...) 2025-02-10 15:21 ` [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support Amelie Delaunay @ 2025-02-10 15:21 ` Amelie Delaunay 2025-02-13 9:02 ` Krzysztof Kozlowski 2025-02-10 15:21 ` [PATCH 08/10] arm64: dts: st: introduce stm32mp21 " Amelie Delaunay ` (2 subsequent siblings) 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Expand config ARCH_STM32 with the new STM32MP21 SoCs family which is composed of STM32MP211, STM32MP213 and STM32MP215 SoCs. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 844a39620cfea8bfc031a545d85e33894ef20994..f788dbc09c9eb6f5801758ccf6b0ffe50a96090e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -325,6 +325,8 @@ config ARCH_STM32 - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. - STM32MP23: - STM32MP231, STM32MP233, STM32MP235. + - STM32MP21: + - STM32MP211, STM32MP213, STM32MP215. config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family 2025-02-10 15:21 ` [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family Amelie Delaunay @ 2025-02-13 9:02 ` Krzysztof Kozlowski 2025-02-14 15:06 ` Amelie Delaunay 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-13 9:02 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On Mon, Feb 10, 2025 at 04:21:01PM +0100, Amelie Delaunay wrote: > Expand config ARCH_STM32 with the new STM32MP21 SoCs family which is > composed of STM32MP211, STM32MP213 and STM32MP215 SoCs. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > arch/arm64/Kconfig.platforms | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 844a39620cfea8bfc031a545d85e33894ef20994..f788dbc09c9eb6f5801758ccf6b0ffe50a96090e 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -325,6 +325,8 @@ config ARCH_STM32 > - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. > - STM32MP23: > - STM32MP231, STM32MP233, STM32MP235. > + - STM32MP21: Squash it with previous patch and keep some sort of order. > + - STM32MP211, STM32MP213, STM32MP215. > > config ARCH_SYNQUACER > bool "Socionext SynQuacer SoC Family" > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family 2025-02-13 9:02 ` Krzysztof Kozlowski @ 2025-02-14 15:06 ` Amelie Delaunay 2025-02-15 11:14 ` Krzysztof Kozlowski 0 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-14 15:06 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On 2/13/25 10:02, Krzysztof Kozlowski wrote: > On Mon, Feb 10, 2025 at 04:21:01PM +0100, Amelie Delaunay wrote: >> Expand config ARCH_STM32 with the new STM32MP21 SoCs family which is >> composed of STM32MP211, STM32MP213 and STM32MP215 SoCs. >> >> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> >> --- >> arch/arm64/Kconfig.platforms | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms >> index 844a39620cfea8bfc031a545d85e33894ef20994..f788dbc09c9eb6f5801758ccf6b0ffe50a96090e 100644 >> --- a/arch/arm64/Kconfig.platforms >> +++ b/arch/arm64/Kconfig.platforms >> @@ -325,6 +325,8 @@ config ARCH_STM32 >> - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. >> - STM32MP23: >> - STM32MP231, STM32MP233, STM32MP235. >> + - STM32MP21: > > Squash it with previous patch and keep some sort of order. > Ok for squashing with patch 3. Do you mean to keep the current chronological order used here or to change the order because "chronological" is not an appropriate order? In this case, would the alphanumeric order be fine? >> + - STM32MP211, STM32MP213, STM32MP215. >> >> config ARCH_SYNQUACER >> bool "Socionext SynQuacer SoC Family" >> >> -- >> 2.25.1 >> Regards, Amelie ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family 2025-02-14 15:06 ` Amelie Delaunay @ 2025-02-15 11:14 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-15 11:14 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On 14/02/2025 16:06, Amelie Delaunay wrote: > On 2/13/25 10:02, Krzysztof Kozlowski wrote: >> On Mon, Feb 10, 2025 at 04:21:01PM +0100, Amelie Delaunay wrote: >>> Expand config ARCH_STM32 with the new STM32MP21 SoCs family which is >>> composed of STM32MP211, STM32MP213 and STM32MP215 SoCs. >>> >>> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> >>> --- >>> arch/arm64/Kconfig.platforms | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms >>> index 844a39620cfea8bfc031a545d85e33894ef20994..f788dbc09c9eb6f5801758ccf6b0ffe50a96090e 100644 >>> --- a/arch/arm64/Kconfig.platforms >>> +++ b/arch/arm64/Kconfig.platforms >>> @@ -325,6 +325,8 @@ config ARCH_STM32 >>> - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. >>> - STM32MP23: >>> - STM32MP231, STM32MP233, STM32MP235. >>> + - STM32MP21: >> >> Squash it with previous patch and keep some sort of order. >> > > Ok for squashing with patch 3. > Do you mean to keep the current chronological order used here or to chronological of what? Adding it? That's the worse of possible orders, because it is basically random invitation to conflicts. If chronological of market release, that's tricky to any contributor to figure out. > change the order because "chronological" is not an appropriate order? In > this case, would the alphanumeric order be fine? Many lists go alphanumerical because it is most obvious and avoids conflicts. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 08/10] arm64: dts: st: introduce stm32mp21 SoCs family 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (6 preceding siblings ...) 2025-02-10 15:21 ` [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family Amelie Delaunay @ 2025-02-10 15:21 ` Amelie Delaunay 2025-02-13 9:02 ` Krzysztof Kozlowski 2025-02-10 15:21 ` [PATCH 09/10] dt-bindings: stm32: document stm32mp215f-dk board Amelie Delaunay 2025-02-10 15:21 ` [PATCH 10/10] arm64: dts: st: add stm32mp215f-dk board support Amelie Delaunay 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay From: Alexandre Torgue <alexandre.torgue@foss.st.com> STM32MP21 family is composed of 3 SoCs defined as following: -STM32MP211: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP213: STM32MP211 + a second ETH, CAN-FD. -STM32MP215: STM32MP213 + Display and CSI2. A second diversity layer exists for security features/ A35 frequency: -STM32MP21xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 130 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp213.dtsi | 9 +++ arch/arm64/boot/dts/st/stm32mp215.dtsi | 9 +++ arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 ++ arch/arm64/boot/dts/st/stm32mp21xf.dtsi | 8 ++ 5 files changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d384359e0ea16e2593795ff48d4a699324c8ca75 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + arm,no-tick-in-suspend; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <2>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x0 0x80000000>; + dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; + + rifsc: bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <2>; + ranges; + dma-ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x0 0x400>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x0 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp213.dtsi b/arch/arm64/boot/dts/st/stm32mp213.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..22cdedd9abbf4efac2334d497618daa6cc76727b --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp213.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp211.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp215.dtsi b/arch/arm64/boot/dts/st/stm32mp215.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d2c63e92b3cc15ec64898374fd2e745a9c71eb6d --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp213.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..39507a7564c8488647a3276eb227eb5f446359e6 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xf.dtsi b/arch/arm64/boot/dts/st/stm32mp21xf.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..39507a7564c8488647a3276eb227eb5f446359e6 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 08/10] arm64: dts: st: introduce stm32mp21 SoCs family 2025-02-10 15:21 ` [PATCH 08/10] arm64: dts: st: introduce stm32mp21 " Amelie Delaunay @ 2025-02-13 9:02 ` Krzysztof Kozlowski 2025-02-14 15:18 ` Amelie Delaunay 0 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-13 9:02 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On Mon, Feb 10, 2025 at 04:21:02PM +0100, Amelie Delaunay wrote: > From: Alexandre Torgue <alexandre.torgue@foss.st.com> > > STM32MP21 family is composed of 3 SoCs defined as following: > > -STM32MP211: common part composed of 1*Cortex-A35, common peripherals > like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... > > -STM32MP213: STM32MP211 + a second ETH, CAN-FD. > > -STM32MP215: STM32MP213 + Display and CSI2. > > A second diversity layer exists for security features/ A35 frequency: > -STM32MP21xY, "Y" gives information: > -Y = A means A35@1.2GHz + no cryp IP and no secure boot. > -Y = C means A35@1.2GHz + cryp IP and secure boot. > -Y = D means A35@1.5GHz + no cryp IP and no secure boot. > -Y = F means A35@1.5GHz + cryp IP and secure boot. > > Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > arch/arm64/boot/dts/st/stm32mp211.dtsi | 130 ++++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/st/stm32mp213.dtsi | 9 +++ > arch/arm64/boot/dts/st/stm32mp215.dtsi | 9 +++ > arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 ++ > arch/arm64/boot/dts/st/stm32mp21xf.dtsi | 8 ++ > 5 files changed, 164 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..d384359e0ea16e2593795ff48d4a699324c8ca75 > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi > @@ -0,0 +1,130 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved > + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. > + */ > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a35"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a35-pmu"; > + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>; > + interrupt-parent = <&intc>; > + }; > + > + arm_wdt: watchdog { > + compatible = "arm,smc-wdt"; > + arm,smc-id = <0xbc000000>; > + status = "disabled"; > + }; > + > + clocks { > + ck_flexgen_08: ck-flexgen-08 { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <64000000>; > + }; > + > + ck_flexgen_51: ck-flexgen-51 { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <200000000>; > + }; > + }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + > + scmi: scmi { > + compatible = "linaro,scmi-optee"; > + #address-cells = <1>; > + #size-cells = <0>; > + linaro,optee-channel-id = <0>; > + > + scmi_clk: protocol@14 { > + reg = <0x14>; > + #clock-cells = <1>; > + }; > + > + scmi_reset: protocol@16 { > + reg = <0x16>; > + #reset-cells = <1>; > + }; > + }; > + }; > + > + intc: interrupt-controller@4ac00000 { MMIO nodes belong to the soc. > + compatible = "arm,cortex-a7-gic"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x0 0x4ac10000 0x0 0x1000>, > + <0x0 0x4ac20000 0x0 0x2000>, > + <0x0 0x4ac40000 0x0 0x2000>, > + <0x0 0x4ac60000 0x0 0x2000>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&intc>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; > + arm,no-tick-in-suspend; > + }; > + > + soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <2>; > + interrupt-parent = <&intc>; > + ranges = <0x0 0x0 0x0 0x0 0x80000000>; ranges is the second property. See DTS coding style. > + dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; > + > + rifsc: bus@42080000 { > + compatible = "simple-bus"; > + reg = <0x42080000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <2>; > + ranges; and here is third. > + dma-ranges; > + > + usart2: serial@400e0000 { Although addresses seem wrong. How bus could start at 0x4208 but device at 0x400e? > + compatible = "st,stm32h7-uart"; > + reg = <0x400e0000 0x0 0x400>; > + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ck_flexgen_08>; > + status = "disabled"; > + }; > + }; > + > + syscfg: syscon@44230000 { > + compatible = "st,stm32mp25-syscfg", "syscon"; Which soc is this? DTSI says stm32mp211, commit STM32MP21, but compatible xxx25? > + reg = <0x44230000 0x0 0x10000>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/st/stm32mp213.dtsi b/arch/arm64/boot/dts/st/stm32mp213.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..22cdedd9abbf4efac2334d497618daa6cc76727b > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp213.dtsi > @@ -0,0 +1,9 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved > + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. > + */ > +#include "stm32mp211.dtsi" > + > +/ { > +}; > diff --git a/arch/arm64/boot/dts/st/stm32mp215.dtsi b/arch/arm64/boot/dts/st/stm32mp215.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..d2c63e92b3cc15ec64898374fd2e745a9c71eb6d > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp215.dtsi > @@ -0,0 +1,9 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved > + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. > + */ > +#include "stm32mp213.dtsi" > + > +/ { > +}; What is the point of this file exactly? > diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..39507a7564c8488647a3276eb227eb5f446359e6 > --- /dev/null > +++ b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved > + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. > + */ > + > +/ { > +}; And this and others. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 08/10] arm64: dts: st: introduce stm32mp21 SoCs family 2025-02-13 9:02 ` Krzysztof Kozlowski @ 2025-02-14 15:18 ` Amelie Delaunay 0 siblings, 0 replies; 24+ messages in thread From: Amelie Delaunay @ 2025-02-14 15:18 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On 2/13/25 10:02, Krzysztof Kozlowski wrote: > On Mon, Feb 10, 2025 at 04:21:02PM +0100, Amelie Delaunay wrote: >> From: Alexandre Torgue <alexandre.torgue@foss.st.com> >> >> STM32MP21 family is composed of 3 SoCs defined as following: >> >> -STM32MP211: common part composed of 1*Cortex-A35, common peripherals >> like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... >> >> -STM32MP213: STM32MP211 + a second ETH, CAN-FD. >> >> -STM32MP215: STM32MP213 + Display and CSI2. >> >> A second diversity layer exists for security features/ A35 frequency: >> -STM32MP21xY, "Y" gives information: >> -Y = A means A35@1.2GHz + no cryp IP and no secure boot. >> -Y = C means A35@1.2GHz + cryp IP and secure boot. >> -Y = D means A35@1.5GHz + no cryp IP and no secure boot. >> -Y = F means A35@1.5GHz + cryp IP and secure boot. >> >> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> >> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> >> --- >> arch/arm64/boot/dts/st/stm32mp211.dtsi | 130 ++++++++++++++++++++++++++++++++ >> arch/arm64/boot/dts/st/stm32mp213.dtsi | 9 +++ >> arch/arm64/boot/dts/st/stm32mp215.dtsi | 9 +++ >> arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 ++ >> arch/arm64/boot/dts/st/stm32mp21xf.dtsi | 8 ++ >> 5 files changed, 164 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi >> new file mode 100644 >> index 0000000000000000000000000000000000000000..d384359e0ea16e2593795ff48d4a699324c8ca75 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi >> @@ -0,0 +1,130 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved >> + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. >> + */ >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a35"; >> + device_type = "cpu"; >> + reg = <0>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a35-pmu"; >> + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>; >> + interrupt-parent = <&intc>; >> + }; >> + >> + arm_wdt: watchdog { >> + compatible = "arm,smc-wdt"; >> + arm,smc-id = <0xbc000000>; >> + status = "disabled"; >> + }; >> + >> + clocks { >> + ck_flexgen_08: ck-flexgen-08 { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <64000000>; >> + }; >> + >> + ck_flexgen_51: ck-flexgen-51 { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <200000000>; >> + }; >> + }; >> + >> + firmware { >> + optee { >> + compatible = "linaro,optee-tz"; >> + method = "smc"; >> + }; >> + >> + scmi: scmi { >> + compatible = "linaro,scmi-optee"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + linaro,optee-channel-id = <0>; >> + >> + scmi_clk: protocol@14 { >> + reg = <0x14>; >> + #clock-cells = <1>; >> + }; >> + >> + scmi_reset: protocol@16 { >> + reg = <0x16>; >> + #reset-cells = <1>; >> + }; >> + }; >> + }; >> + >> + intc: interrupt-controller@4ac00000 { > > MMIO nodes belong to the soc. > Indeed. >> + compatible = "arm,cortex-a7-gic"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + reg = <0x0 0x4ac10000 0x0 0x1000>, >> + <0x0 0x4ac20000 0x0 0x2000>, >> + <0x0 0x4ac40000 0x0 0x2000>, >> + <0x0 0x4ac60000 0x0 0x2000>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupt-parent = <&intc>; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; >> + arm,no-tick-in-suspend; >> + }; >> + >> + soc@0 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <2>; >> + interrupt-parent = <&intc>; >> + ranges = <0x0 0x0 0x0 0x0 0x80000000>; > > ranges is the second property. See DTS coding style. > Ok. >> + dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; >> + >> + rifsc: bus@42080000 { >> + compatible = "simple-bus"; >> + reg = <0x42080000 0x0 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <2>; >> + ranges; > > and here is third. > >> + dma-ranges; >> + >> + usart2: serial@400e0000 { > > Although addresses seem wrong. How bus could start at 0x4208 but device > at 0x400e? > >> + compatible = "st,stm32h7-uart"; >> + reg = <0x400e0000 0x0 0x400>; >> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ck_flexgen_08>; >> + status = "disabled"; >> + }; >> + }; >> + >> + syscfg: syscon@44230000 { >> + compatible = "st,stm32mp25-syscfg", "syscon"; > > Which soc is this? DTSI says stm32mp211, commit STM32MP21, but > compatible xxx25? > Looks like a new compatible is needed, and I guess it is also true for stm32mp231. >> + reg = <0x44230000 0x0 0x10000>; >> + }; >> + }; >> +}; >> diff --git a/arch/arm64/boot/dts/st/stm32mp213.dtsi b/arch/arm64/boot/dts/st/stm32mp213.dtsi >> new file mode 100644 >> index 0000000000000000000000000000000000000000..22cdedd9abbf4efac2334d497618daa6cc76727b >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp213.dtsi >> @@ -0,0 +1,9 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved >> + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. >> + */ >> +#include "stm32mp211.dtsi" >> + >> +/ { >> +}; >> diff --git a/arch/arm64/boot/dts/st/stm32mp215.dtsi b/arch/arm64/boot/dts/st/stm32mp215.dtsi >> new file mode 100644 >> index 0000000000000000000000000000000000000000..d2c63e92b3cc15ec64898374fd2e745a9c71eb6d >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp215.dtsi >> @@ -0,0 +1,9 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved >> + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. >> + */ >> +#include "stm32mp213.dtsi" >> + >> +/ { >> +}; > > What is the point of this file exactly? > Skeleton file for upcoming second ethernet and can-fd peripherals, not available on stm32mp211. >> diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi >> new file mode 100644 >> index 0000000000000000000000000000000000000000..39507a7564c8488647a3276eb227eb5f446359e6 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi >> @@ -0,0 +1,8 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) >> +/* >> + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved >> + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. >> + */ >> + >> +/ { >> +}; > > And this and others. > Skeleton file for upcoming cryptographic support, not available on stm32mp21xa and stm32mp21xd. As said previously, same split is used on other STM32 MPUs. Regards, Amelie ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 09/10] dt-bindings: stm32: document stm32mp215f-dk board 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (7 preceding siblings ...) 2025-02-10 15:21 ` [PATCH 08/10] arm64: dts: st: introduce stm32mp21 " Amelie Delaunay @ 2025-02-10 15:21 ` Amelie Delaunay 2025-02-13 8:59 ` Krzysztof Kozlowski 2025-02-10 15:21 ` [PATCH 10/10] arm64: dts: st: add stm32mp215f-dk board support Amelie Delaunay 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Add new entry for stm32mp215-dk board. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 9ffcba51c9207b5a1386c025f850bc594c915c8c..9db52e5d09ac1d963e79bd937eef6cb33313f343 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -190,6 +190,12 @@ properties: - st,stm32mp235f-dk - const: st,stm32mp235 + - description: ST STM32MP215 based Boards + items: + - enum: + - st,stm32mp215f-dk + - const: st,stm32mp215 + additionalProperties: true ... -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 09/10] dt-bindings: stm32: document stm32mp215f-dk board 2025-02-10 15:21 ` [PATCH 09/10] dt-bindings: stm32: document stm32mp215f-dk board Amelie Delaunay @ 2025-02-13 8:59 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-13 8:59 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On Mon, Feb 10, 2025 at 04:21:03PM +0100, Amelie Delaunay wrote: > Add new entry for stm32mp215-dk board. > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 10/10] arm64: dts: st: add stm32mp215f-dk board support 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay ` (8 preceding siblings ...) 2025-02-10 15:21 ` [PATCH 09/10] dt-bindings: stm32: document stm32mp215f-dk board Amelie Delaunay @ 2025-02-10 15:21 ` Amelie Delaunay 2025-02-13 8:59 ` Krzysztof Kozlowski 9 siblings, 1 reply; 24+ messages in thread From: Amelie Delaunay @ 2025-02-10 15:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev, Amelie Delaunay Add STM32MP215F Discovery Kit board support. It embeds a STM32MP235FAN SoC, with 2GB of LPDDR4, 1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT combo, LCD 18bit connector, CSI camera connector, ... Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> --- arch/arm64/boot/dts/st/Makefile | 1 + arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 49 +++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 06364152206997863d0991c25589de73c63494fb..63908113ae36ba19378ac1fedc0309ef46555f17 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts new file mode 100644 index 0000000000000000000000000000000000000000..7bdaeaa5ab0fbe99a7e39b623d5e7a0e469d3e50 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp215.dtsi" +#include "stm32mp21xf.dtsi" + +/ { + model = "STMicroelectronics STM32MP215F-DK Discovery Board"; + compatible = "st,stm32mp215f-dk", "st,stm32mp215"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 10/10] arm64: dts: st: add stm32mp215f-dk board support 2025-02-10 15:21 ` [PATCH 10/10] arm64: dts: st: add stm32mp215f-dk board support Amelie Delaunay @ 2025-02-13 8:59 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2025-02-13 8:59 UTC (permalink / raw) To: Amelie Delaunay Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue, Catalin Marinas, Will Deacon, Richard Cochran, devicetree, linux-stm32, linux-arm-kernel, linux-kernel, netdev On Mon, Feb 10, 2025 at 04:21:04PM +0100, Amelie Delaunay wrote: > Add STM32MP215F Discovery Kit board support. It embeds a STM32MP235FAN SoC, > with 2GB of LPDDR4, 1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT > combo, LCD 18bit connector, CSI camera connector, ... > > Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> > --- > arch/arm64/boot/dts/st/Makefile | 1 + > arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 49 +++++++++++++++++++++++++++++++ > 2 files changed, 50 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2025-02-15 11:14 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-02-10 15:20 [PATCH 00/10] Expand STM32MP2 family with new SoC and boards Amelie Delaunay 2025-02-10 15:20 ` [PATCH 01/10] dt-bindings: stm32: document stm32mp257f-dk board Amelie Delaunay 2025-02-11 18:19 ` Conor Dooley 2025-02-10 15:20 ` [PATCH 02/10] arm64: dts: st: add stm32mp257f-dk board support Amelie Delaunay 2025-02-10 15:20 ` [PATCH 03/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP23 SoCs family Amelie Delaunay 2025-02-10 15:20 ` [PATCH 04/10] arm64: dts: st: introduce stm32mp23 " Amelie Delaunay 2025-02-13 9:08 ` Krzysztof Kozlowski 2025-02-14 14:12 ` Amelie Delaunay 2025-02-10 15:20 ` [PATCH 05/10] dt-bindings: stm32: document stm32mp235f-dk board Amelie Delaunay 2025-02-11 18:19 ` Conor Dooley 2025-02-10 15:21 ` [PATCH 06/10] arm64: dts: st: add stm32mp235f-dk board support Amelie Delaunay 2025-02-13 9:03 ` Krzysztof Kozlowski 2025-02-14 14:13 ` Amelie Delaunay 2025-02-10 15:21 ` [PATCH 07/10] arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21 SoCs family Amelie Delaunay 2025-02-13 9:02 ` Krzysztof Kozlowski 2025-02-14 15:06 ` Amelie Delaunay 2025-02-15 11:14 ` Krzysztof Kozlowski 2025-02-10 15:21 ` [PATCH 08/10] arm64: dts: st: introduce stm32mp21 " Amelie Delaunay 2025-02-13 9:02 ` Krzysztof Kozlowski 2025-02-14 15:18 ` Amelie Delaunay 2025-02-10 15:21 ` [PATCH 09/10] dt-bindings: stm32: document stm32mp215f-dk board Amelie Delaunay 2025-02-13 8:59 ` Krzysztof Kozlowski 2025-02-10 15:21 ` [PATCH 10/10] arm64: dts: st: add stm32mp215f-dk board support Amelie Delaunay 2025-02-13 8:59 ` Krzysztof Kozlowski
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