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([2a01:e0a:106d:1080:405b:6cdd:f27a:d661]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488a91686f9sm302095365e9.10.2026.04.07.10.38.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Apr 2026 10:38:54 -0700 (PDT) Message-ID: <8ed5aeb8-98fb-4b87-a6a9-983e4fa91db5@linaro.org> Date: Tue, 7 Apr 2026 19:38:54 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v2 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions To: Joe Sandom , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com> <20260407-rb5gen2-dts-v2-1-d0c7f447ee73@axon.com> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260407-rb5gen2-dts-v2-1-d0c7f447ee73@axon.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/7/26 17:46, Joe Sandom wrote: > Add the MHI register regions to the pcie0 and pcie1 controller nodes > so that the MHI bus layer can access controller registers directly. Can you elaborate more on that ? Looking at the current implementation, the pcie host driver only uses the mhi memory zone to show the transition count in debugfs. Neil > > Signed-off-by: Joe Sandom > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++---- > 1 file changed, 16 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..055ca931c04859f3a312eb9921aeb7a8cc676822 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1964,8 +1964,14 @@ pcie0: pcie@1c00000 { > <0 0x60000000 0 0xf1d>, > <0 0x60000f20 0 0xa8>, > <0 0x60001000 0 0x1000>, > - <0 0x60100000 0 0x100000>; > - reg-names = "parf", "dbi", "elbi", "atu", "config"; > + <0 0x60100000 0 0x100000>, > + <0 0x01c03000 0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > #address-cells = <3>; > #size-cells = <2>; > ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, > @@ -2138,8 +2144,14 @@ pcie1: pcie@1c08000 { > <0x0 0x40000000 0x0 0xf1d>, > <0x0 0x40000f20 0x0 0xa8>, > <0x0 0x40001000 0x0 0x1000>, > - <0x0 0x40100000 0x0 0x100000>; > - reg-names = "parf", "dbi", "elbi", "atu", "config"; > + <0x0 0x40100000 0x0 0x100000>, > + <0x0 0x01c0b000 0x0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > #address-cells = <3>; > #size-cells = <2>; > ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, >