* [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC
@ 2024-10-01 6:23 Drew Fustini
2024-10-01 6:23 ` [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support Drew Fustini
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Drew Fustini @ 2024-10-01 6:23 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue,
Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin,
Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Drew Fustini
Cc: netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv
This series is based on 6.12-rc1 and depends on this pinctrl series:
20240930-th1520-pinctrl-v3-0-32cea2bdbecb@tenstorrent.com
I have a branch with this series and the dependencies:
https://github.com/pdp7/linux/tree/b4/th1520-dwmac
Regarding clocks, the gmac nodes in th1520.dtsi have the "stmmac_clk"
clock set to CLK_GMAC_AXI in the AP_SUBSYS clock controller. This
corresponds to the enable bit for the GMAC axi4_clk gate which is
handled by the clk-th1520-ap driver. thead_dwmac_fix_speed() does not
modify anything in the AP_SUBSYS clock controller. It only writes to
GMAC APB registers. It seems unnecessary to create a new clock driver
just for the GMAC APB registers. Refer to section 1.6.2 in the TH1520
Peripheral Interface User Manual [1].
I've removed the properties that I added in v2: thead,rx-internal-delay
and thead,tx-internal-delay. The units for the delay field in the rgmii
delay control registers are not documented. Andrew Lunn suggested I
just hard code the delay field to 0 since I don't know the units and
the boards work with the hardware reset value of 0.
[1] https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Changes in v3:
- Rebase on v6.12-rc1
- Remove thead,rx-internal-delay and thead,tx-internal-delay properties
- Remove unneeded call to thead_dwmac_fix_speed() during probe
- Fix filename for the yaml file in MAINTAINERS patch
Changes in v2:
- Drop the first patch as it is no longer needed due to upstream commit
d01e0e98de31 ("dt-bindings: net: dwmac: Validate PBL for all IP-cores")
- Rename compatible from "thead,th1520-dwmac" to "thead,th1520-gmac"
- Add thead,rx-internal-delay and thead,tx-internal-delay properties
and check that it does not exceed the maximum value
- Convert from stmmac_dvr_probe() to devm_stmmac_pltfr_probe() and
delete the .remove_new hook as it is no longer needed
- Handle return value of regmap_write() in case it fails
- Add phy reset delay properties to the BeagleV Ahead device tree
- Link: https://lore.kernel.org/linux-riscv/20240926-th1520-dwmac-v2-0-f34f28ad1dc9@tenstorrent.com/
Changes in v1:
- remove thead,gmacapb that references syscon for APB registers
- add a second memory region to gmac nodes for the APB registers
- Link: https://lore.kernel.org/all/20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com/
---
Emil Renner Berthing (1):
riscv: dts: thead: Add TH1520 ethernet nodes
Jisheng Zhang (2):
dt-bindings: net: Add T-HEAD dwmac support
net: stmmac: Add glue layer for T-HEAD TH1520 SoC
.../devicetree/bindings/net/snps,dwmac.yaml | 1 +
.../devicetree/bindings/net/thead,th1520-gmac.yaml | 97 +++++++
MAINTAINERS | 2 +
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 91 +++++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 129 +++++++++
arch/riscv/boot/dts/thead/th1520.dtsi | 50 ++++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 291 +++++++++++++++++++++
9 files changed, 673 insertions(+)
---
base-commit: 6b16e599500bd0002164d9edcb8bf7652d9888fa
change-id: 20240930-th1520-dwmac-34f5dd0cccf8
Best regards,
--
Drew Fustini <dfustini@tenstorrent.com>
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support 2024-10-01 6:23 [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Drew Fustini @ 2024-10-01 6:23 ` Drew Fustini 2024-10-01 6:58 ` Krzysztof Kozlowski 2024-10-01 6:23 ` [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC Drew Fustini ` (2 subsequent siblings) 3 siblings, 1 reply; 10+ messages in thread From: Drew Fustini @ 2024-10-01 6:23 UTC (permalink / raw) To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Drew Fustini Cc: netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv From: Jisheng Zhang <jszhang@kernel.org> Add documentation to describe the DesginWare-based GMAC controllers in the T-HEAD TH1520 SoC. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [drew: rename compatible, add apb registers as second reg of gmac node] Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> --- .../devicetree/bindings/net/snps,dwmac.yaml | 1 + .../devicetree/bindings/net/thead,th1520-gmac.yaml | 97 ++++++++++++++++++++++ MAINTAINERS | 1 + 3 files changed, 99 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 4e2ba1bf788c..474ade185033 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -99,6 +99,7 @@ properties: - snps,dwxgmac-2.10 - starfive,jh7100-dwmac - starfive,jh7110-dwmac + - thead,th1520-gmac reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml new file mode 100644 index 000000000000..fef1810b10c4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 GMAC Ethernet controller + +maintainers: + - Drew Fustini <dfustini@tenstorrent.com> + +description: | + The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual + https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs + + Features include + - Compliant with IEEE802.3 Specification + - IEEE 1588-2008 standard for precision networked clock synchronization + - Supports 10/100/1000Mbps data transfer rate + - Supports RGMII/MII interface + - Preamble and start of frame data (SFD) insertion in Transmit path + - Preamble and SFD deletion in the Receive path + - Automatic CRC and pad generation options for receive frames + - MDIO master interface for PHY device configuration and management + + The GMAC Registers consists of two parts + - APB registers are used to configure clock frequency/clock enable/clock + direction/PHY interface type. + - AHB registers are use to configure GMAC core (DesignWare Core part). + GMAC core register consists of DMA registers and GMAC registers. + +select: + properties: + compatible: + contains: + enum: + - thead,th1520-gmac + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - enum: + - thead,th1520-gmac + - const: snps,dwmac-3.70a + + reg: + items: + - description: DesignWare GMAC IP core registers + - description: GMAC APB registers + + reg-names: + items: + - const: dwmac + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + +unevaluatedProperties: false + +examples: + - | + gmac0: ethernet@e7070000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xe7070000 0x2000>, <0xec003000 0x1000>; + reg-names = "dwmac", "apb"; + clocks = <&clk 1>, <&clk 2>; + clock-names = "stmmaceth", "pclk"; + interrupts = <66>; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + snps,fixed-burst; + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 67634f0ea30e..9e50107efb37 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19942,6 +19942,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support 2024-10-01 6:23 ` [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support Drew Fustini @ 2024-10-01 6:58 ` Krzysztof Kozlowski 2024-10-02 19:08 ` Drew Fustini 0 siblings, 1 reply; 10+ messages in thread From: Krzysztof Kozlowski @ 2024-10-01 6:58 UTC (permalink / raw) To: Drew Fustini Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv On Mon, Sep 30, 2024 at 11:23:24PM -0700, Drew Fustini wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Add documentation to describe the DesginWare-based GMAC controllers in > the T-HEAD TH1520 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > [drew: rename compatible, add apb registers as second reg of gmac node] > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> > --- > .../devicetree/bindings/net/snps,dwmac.yaml | 1 + > .../devicetree/bindings/net/thead,th1520-gmac.yaml | 97 ++++++++++++++++++++++ > MAINTAINERS | 1 + > 3 files changed, 99 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > index 4e2ba1bf788c..474ade185033 100644 > --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml > +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > @@ -99,6 +99,7 @@ properties: > - snps,dwxgmac-2.10 > - starfive,jh7100-dwmac > - starfive,jh7110-dwmac > + - thead,th1520-gmac > > reg: > minItems: 1 > diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml > new file mode 100644 > index 000000000000..fef1810b10c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml > @@ -0,0 +1,97 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: T-HEAD TH1520 GMAC Ethernet controller > + > +maintainers: > + - Drew Fustini <dfustini@tenstorrent.com> > + > +description: | > + The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual > + https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs > + > + Features include > + - Compliant with IEEE802.3 Specification > + - IEEE 1588-2008 standard for precision networked clock synchronization > + - Supports 10/100/1000Mbps data transfer rate > + - Supports RGMII/MII interface > + - Preamble and start of frame data (SFD) insertion in Transmit path > + - Preamble and SFD deletion in the Receive path > + - Automatic CRC and pad generation options for receive frames > + - MDIO master interface for PHY device configuration and management > + > + The GMAC Registers consists of two parts > + - APB registers are used to configure clock frequency/clock enable/clock > + direction/PHY interface type. > + - AHB registers are use to configure GMAC core (DesignWare Core part). > + GMAC core register consists of DMA registers and GMAC registers. > + > +select: > + properties: > + compatible: > + contains: > + enum: > + - thead,th1520-gmac > + required: > + - compatible > + > +allOf: > + - $ref: snps,dwmac.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - thead,th1520-gmac > + - const: snps,dwmac-3.70a > + > + reg: > + items: > + - description: DesignWare GMAC IP core registers > + - description: GMAC APB registers > + > + reg-names: > + items: > + - const: dwmac > + - const: apb I don't get why none of snps,dwmac properties are restricted. How many interrupts do you have here? How many clocks? resets? > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts Drop > + - interrupt-names Drop > + - phy-mode > + > +unevaluatedProperties: false Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support 2024-10-01 6:58 ` Krzysztof Kozlowski @ 2024-10-02 19:08 ` Drew Fustini 2024-10-03 10:42 ` Krzysztof Kozlowski 0 siblings, 1 reply; 10+ messages in thread From: Drew Fustini @ 2024-10-02 19:08 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv On Tue, Oct 01, 2024 at 08:58:34AM +0200, Krzysztof Kozlowski wrote: > On Mon, Sep 30, 2024 at 11:23:24PM -0700, Drew Fustini wrote: > > From: Jisheng Zhang <jszhang@kernel.org> > > > > Add documentation to describe the DesginWare-based GMAC controllers in > > the T-HEAD TH1520 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > [drew: rename compatible, add apb registers as second reg of gmac node] > > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> > > --- > > .../devicetree/bindings/net/snps,dwmac.yaml | 1 + > > .../devicetree/bindings/net/thead,th1520-gmac.yaml | 97 ++++++++++++++++++++++ > > MAINTAINERS | 1 + > > 3 files changed, 99 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > index 4e2ba1bf788c..474ade185033 100644 > > --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml > > @@ -99,6 +99,7 @@ properties: > > - snps,dwxgmac-2.10 > > - starfive,jh7100-dwmac > > - starfive,jh7110-dwmac > > + - thead,th1520-gmac > > > > reg: > > minItems: 1 > > diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml > > new file mode 100644 > > index 000000000000..fef1810b10c4 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml > > @@ -0,0 +1,97 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: T-HEAD TH1520 GMAC Ethernet controller > > + > > +maintainers: > > + - Drew Fustini <dfustini@tenstorrent.com> > > + > > +description: | > > + The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual > > + https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs > > + > > + Features include > > + - Compliant with IEEE802.3 Specification > > + - IEEE 1588-2008 standard for precision networked clock synchronization > > + - Supports 10/100/1000Mbps data transfer rate > > + - Supports RGMII/MII interface > > + - Preamble and start of frame data (SFD) insertion in Transmit path > > + - Preamble and SFD deletion in the Receive path > > + - Automatic CRC and pad generation options for receive frames > > + - MDIO master interface for PHY device configuration and management > > + > > + The GMAC Registers consists of two parts > > + - APB registers are used to configure clock frequency/clock enable/clock > > + direction/PHY interface type. > > + - AHB registers are use to configure GMAC core (DesignWare Core part). > > + GMAC core register consists of DMA registers and GMAC registers. > > + > > +select: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - thead,th1520-gmac > > + required: > > + - compatible > > + > > +allOf: > > + - $ref: snps,dwmac.yaml# > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - thead,th1520-gmac > > + - const: snps,dwmac-3.70a > > + > > + reg: > > + items: > > + - description: DesignWare GMAC IP core registers > > + - description: GMAC APB registers > > + > > + reg-names: > > + items: > > + - const: dwmac > > + - const: apb > > I don't get why none of snps,dwmac properties are restricted. How many > interrupts do you have here? How many clocks? resets? Thanks for pointing this out. Yes, I forgot to document the clocks, interrupts and resets. There needs to be 2 clocks (stmmaceth and pclk). There also needs to be 2 resets: each GMAC has a reset plus a seperate reset for the GMAC AXI interface. There is 1 interrupt (macirq) but it is optional. The BeagleV Ahead uses it but the LicheePi 4A does not use the interrupt. However, I'm uncertain about how to restrict the snps,dwmac properties. I see that starfive,jh7110-dwmac.yaml has the following logic. Should I be adding something like this to restrict the snps,dwmac properties? --------------------------------------------------------------------- allOf: - $ref: snps,dwmac.yaml# - if: properties: compatible: contains: const: starfive,jh7100-dwmac then: properties: interrupts: minItems: 2 maxItems: 2 interrupt-names: minItems: 2 maxItems: 2 resets: maxItems: 1 reset-names: const: ahb <snip> --------------------------------------------------------------------- > > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > Drop Will do. > > > + - interrupt-names > > Drop Will do. > > > + - phy-mode > > + > > +unevaluatedProperties: false > > Best regards, > Krzysztof Thanks for your review, Drew ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support 2024-10-02 19:08 ` Drew Fustini @ 2024-10-03 10:42 ` Krzysztof Kozlowski 0 siblings, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2024-10-03 10:42 UTC (permalink / raw) To: Drew Fustini Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv On 02/10/2024 21:08, Drew Fustini wrote: > On Tue, Oct 01, 2024 at 08:58:34AM +0200, Krzysztof Kozlowski wrote: >> On Mon, Sep 30, 2024 at 11:23:24PM -0700, Drew Fustini wrote: >>> From: Jisheng Zhang <jszhang@kernel.org> >>> >>> Add documentation to describe the DesginWare-based GMAC controllers in >>> the T-HEAD TH1520 SoC. >>> >>> Signed-off-by: Jisheng Zhang <jszhang@kernel.org> >>> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> >>> [drew: rename compatible, add apb registers as second reg of gmac node] >>> Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> >>> --- >>> .../devicetree/bindings/net/snps,dwmac.yaml | 1 + >>> .../devicetree/bindings/net/thead,th1520-gmac.yaml | 97 ++++++++++++++++++++++ >>> MAINTAINERS | 1 + >>> 3 files changed, 99 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml >>> index 4e2ba1bf788c..474ade185033 100644 >>> --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml >>> +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml >>> @@ -99,6 +99,7 @@ properties: >>> - snps,dwxgmac-2.10 >>> - starfive,jh7100-dwmac >>> - starfive,jh7110-dwmac >>> + - thead,th1520-gmac >>> >>> reg: >>> minItems: 1 >>> diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml >>> new file mode 100644 >>> index 000000000000..fef1810b10c4 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml >>> @@ -0,0 +1,97 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: T-HEAD TH1520 GMAC Ethernet controller >>> + >>> +maintainers: >>> + - Drew Fustini <dfustini@tenstorrent.com> >>> + >>> +description: | >>> + The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual >>> + https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs >>> + >>> + Features include >>> + - Compliant with IEEE802.3 Specification >>> + - IEEE 1588-2008 standard for precision networked clock synchronization >>> + - Supports 10/100/1000Mbps data transfer rate >>> + - Supports RGMII/MII interface >>> + - Preamble and start of frame data (SFD) insertion in Transmit path >>> + - Preamble and SFD deletion in the Receive path >>> + - Automatic CRC and pad generation options for receive frames >>> + - MDIO master interface for PHY device configuration and management >>> + >>> + The GMAC Registers consists of two parts >>> + - APB registers are used to configure clock frequency/clock enable/clock >>> + direction/PHY interface type. >>> + - AHB registers are use to configure GMAC core (DesignWare Core part). >>> + GMAC core register consists of DMA registers and GMAC registers. >>> + >>> +select: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - thead,th1520-gmac >>> + required: >>> + - compatible >>> + >>> +allOf: >>> + - $ref: snps,dwmac.yaml# >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>> + - thead,th1520-gmac >>> + - const: snps,dwmac-3.70a >>> + >>> + reg: >>> + items: >>> + - description: DesignWare GMAC IP core registers >>> + - description: GMAC APB registers >>> + >>> + reg-names: >>> + items: >>> + - const: dwmac >>> + - const: apb >> >> I don't get why none of snps,dwmac properties are restricted. How many >> interrupts do you have here? How many clocks? resets? > > Thanks for pointing this out. Yes, I forgot to document the clocks, > interrupts and resets. > > There needs to be 2 clocks (stmmaceth and pclk). There also needs to be > 2 resets: each GMAC has a reset plus a seperate reset for the GMAC AXI > interface. There is 1 interrupt (macirq) but it is optional. The BeagleV > Ahead uses it but the LicheePi 4A does not use the interrupt. > > However, I'm uncertain about how to restrict the snps,dwmac properties. > > I see that starfive,jh7110-dwmac.yaml has the following logic. Should I > be adding something like this to restrict the snps,dwmac properties? > > --------------------------------------------------------------------- > allOf: > - $ref: snps,dwmac.yaml# > > - if: > properties: > compatible: > contains: > const: starfive,jh7100-dwmac > then: > properties: > interrupts: > minItems: 2 > maxItems: 2 > > interrupt-names: > minItems: 2 > maxItems: 2 > > resets: > maxItems: 1 > > reset-names: > const: ahb No, that's not necessary. You have one device in this binding, so in top-level should define how each such property looks like. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC 2024-10-01 6:23 [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Drew Fustini 2024-10-01 6:23 ` [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support Drew Fustini @ 2024-10-01 6:23 ` Drew Fustini 2024-10-01 9:48 ` Emil Renner Berthing 2024-10-01 6:23 ` [PATCH v3 3/3] riscv: dts: thead: Add TH1520 ethernet nodes Drew Fustini 2024-10-02 15:34 ` [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Andrew Lunn 3 siblings, 1 reply; 10+ messages in thread From: Drew Fustini @ 2024-10-01 6:23 UTC (permalink / raw) To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Drew Fustini Cc: netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv From: Jisheng Zhang <jszhang@kernel.org> Add dwmac glue driver to support the DesignWare-based GMAC controllers on the T-HEAD TH1520 SoC. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> [esmil: rename plat->interface -> plat->mac_interface, use devm_stmmac_probe_config_dt()] Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [drew: convert from stmmac_dvr_probe() to devm_stmmac_pltfr_probe()] Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> --- MAINTAINERS | 1 + drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 291 ++++++++++++++++++++++ 4 files changed, 304 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9e50107efb37..1d24863c01df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19946,6 +19946,7 @@ F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 05cc07b8f48c..82030adaf16e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -228,6 +228,17 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. +config DWMAC_THEAD + tristate "T-HEAD dwmac support" + depends on OF && (ARCH_THEAD || COMPILE_TEST) + select MFD_SYSCON + help + Support for ethernet controllers on T-HEAD RISC-V SoCs + + This selects the T-HEAD platform specific glue layer support for + the stmmac device driver. This driver is used for T-HEAD TH1520 + ethernet controller. + config DWMAC_IMX8 tristate "NXP IMX8 DWMAC support" default ARCH_MXC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index c2f0e91f6bf8..d065634c6223 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o +obj-$(CONFIG_DWMAC_THEAD) += dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o obj-$(CONFIG_DWMAC_LOONGSON1) += dwmac-loongson1.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c new file mode 100644 index 000000000000..f2f94539c0d2 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD DWMAC platform driver + * + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * + */ + +#include <linux/bitfield.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_net.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "stmmac_platform.h" + +#define GMAC_CLK_EN 0x00 +#define GMAC_TX_CLK_EN BIT(1) +#define GMAC_TX_CLK_N_EN BIT(2) +#define GMAC_TX_CLK_OUT_EN BIT(3) +#define GMAC_RX_CLK_EN BIT(4) +#define GMAC_RX_CLK_N_EN BIT(5) +#define GMAC_EPHY_REF_CLK_EN BIT(6) +#define GMAC_RXCLK_DELAY_CTRL 0x04 +#define GMAC_RXCLK_BYPASS BIT(15) +#define GMAC_RXCLK_INVERT BIT(14) +#define GMAC_RXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_RXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_TXCLK_DELAY_CTRL 0x08 +#define GMAC_TXCLK_BYPASS BIT(15) +#define GMAC_TXCLK_INVERT BIT(14) +#define GMAC_TXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_TXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_PLLCLK_DIV 0x0c +#define GMAC_PLLCLK_DIV_EN BIT(31) +#define GMAC_PLLCLK_DIV_MASK GENMASK(7, 0) +#define GMAC_PLLCLK_DIV_NUM(x) FIELD_PREP(GMAC_PLLCLK_DIV_MASK, (x)) +#define GMAC_GTXCLK_SEL 0x18 +#define GMAC_GTXCLK_SEL_PLL BIT(0) +#define GMAC_INTF_CTRL 0x1c +#define PHY_INTF_MASK BIT(0) +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) +#define GMAC_TXCLK_OEN 0x20 +#define TXCLK_DIR_MASK BIT(0) +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) + +#define GMAC_GMII_RGMII_RATE 125000000 +#define GMAC_MII_RATE 25000000 + +static const struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +struct thead_dwmac { + struct plat_stmmacenet_data *plat; + struct regmap *apb_regmap; + struct device *dev; +}; + +static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac = plat->bsp_priv; + u32 phyif; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + phyif = PHY_INTF_MII_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + phyif = PHY_INTF_RGMII; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + return regmap_write(dwmac->apb_regmap, GMAC_INTF_CTRL, phyif); +} + +static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac = plat->bsp_priv; + u32 txclk_dir; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + txclk_dir = TXCLK_DIR_INPUT; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + txclk_dir = TXCLK_DIR_OUTPUT; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + return regmap_write(dwmac->apb_regmap, GMAC_TXCLK_OEN, txclk_dir); +} + +static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode) +{ + struct plat_stmmacenet_data *plat; + struct thead_dwmac *dwmac = priv; + unsigned long rate; + u32 div; + + plat = dwmac->plat; + + switch (plat->mac_interface) { + /* For MII, rxc/txc is provided by phy */ + case PHY_INTERFACE_MODE_MII: + return; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + rate = clk_get_rate(plat->stmmac_clk); + if (!rate || rate % GMAC_GMII_RGMII_RATE != 0 || + rate % GMAC_MII_RATE != 0) { + dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate); + return; + } + + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, GMAC_PLLCLK_DIV_EN, 0); + + switch (speed) { + case SPEED_1000: + div = rate / GMAC_GMII_RGMII_RATE; + break; + case SPEED_100: + div = rate / GMAC_MII_RATE; + break; + case SPEED_10: + div = rate * 10 / GMAC_MII_RATE; + break; + default: + dev_err(dwmac->dev, "invalid speed %u\n", speed); + return; + } + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, + GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); + + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, + GMAC_PLLCLK_DIV_EN, GMAC_PLLCLK_DIV_EN); + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return; + } +} + +static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac = plat->bsp_priv; + int err; + u32 reg; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* use pll */ + err = regmap_write(dwmac->apb_regmap, GMAC_GTXCLK_SEL, GMAC_GTXCLK_SEL_PLL); + if (err) + return dev_err_probe(dwmac->dev, err, + "failed to set phy interface\n"); + + reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; + break; + + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + } + + return regmap_write(dwmac->apb_regmap, GMAC_CLK_EN, reg); +} + +static int thead_dwmac_init(struct platform_device *pdev, void *priv) +{ + struct thead_dwmac *dwmac = priv; + int ret; + + ret = thead_dwmac_set_phy_if(dwmac->plat); + if (ret) + return ret; + + ret = thead_dwmac_set_txclk_dir(dwmac->plat); + if (ret) + return ret; + + ret = regmap_write(dwmac->apb_regmap, GMAC_RXCLK_DELAY_CTRL, + GMAC_RXCLK_DELAY_VAL(0)); + if (ret) + return dev_err_probe(dwmac->dev, ret, + "failed to set GMAC RX clock delay\n"); + + ret = regmap_write(dwmac->apb_regmap, GMAC_TXCLK_DELAY_CTRL, + GMAC_TXCLK_DELAY_VAL(0)); + if (ret) + return dev_err_probe(dwmac->dev, ret, + "failed to set GMAC TX clock delay\n"); + + return thead_dwmac_enable_clk(dwmac->plat); +} + +static int thead_dwmac_probe(struct platform_device *pdev) +{ + struct stmmac_resources stmmac_res; + struct plat_stmmacenet_data *plat; + struct thead_dwmac *dwmac; + void __iomem *apb; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get resources\n"); + + plat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat), + "dt configuration failed\n"); + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + apb = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(apb)) + return dev_err_probe(&pdev->dev, PTR_ERR(apb), + "Failed to remap gmac apb registers\n"); + + dwmac->apb_regmap = devm_regmap_init_mmio(&pdev->dev, apb, ®map_config); + if (IS_ERR(dwmac->apb_regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->apb_regmap), + "Failed to access gmac apb registers\n"); + + dwmac->dev = &pdev->dev; + dwmac->plat = plat; + plat->bsp_priv = dwmac; + plat->fix_mac_speed = thead_dwmac_fix_speed; + plat->init = thead_dwmac_init; + + return devm_stmmac_pltfr_probe(pdev, plat, &stmmac_res); +} + +static const struct of_device_id thead_dwmac_match[] = { + { .compatible = "thead,th1520-gmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, thead_dwmac_match); + +static struct platform_driver thead_dwmac_driver = { + .probe = thead_dwmac_probe, + .driver = { + .name = "thead-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = thead_dwmac_match, + }, +}; +module_platform_driver(thead_dwmac_driver); + +MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); +MODULE_AUTHOR("Drew Fustini <drew@pdp7.com>"); +MODULE_DESCRIPTION("T-HEAD DWMAC platform driver"); +MODULE_LICENSE("GPL"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC 2024-10-01 6:23 ` [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC Drew Fustini @ 2024-10-01 9:48 ` Emil Renner Berthing 2024-10-03 5:52 ` Drew Fustini 0 siblings, 1 reply; 10+ messages in thread From: Emil Renner Berthing @ 2024-10-01 9:48 UTC (permalink / raw) To: Drew Fustini, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv Drew Fustini wrote: > From: Jisheng Zhang <jszhang@kernel.org> > > Add dwmac glue driver to support the DesignWare-based GMAC controllers > on the T-HEAD TH1520 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > [esmil: rename plat->interface -> plat->mac_interface, > use devm_stmmac_probe_config_dt()] > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > [drew: convert from stmmac_dvr_probe() to devm_stmmac_pltfr_probe()] > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> > --- > MAINTAINERS | 1 + > drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + > drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + > drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 291 ++++++++++++++++++++++ > 4 files changed, 304 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9e50107efb37..1d24863c01df 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -19946,6 +19946,7 @@ F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml > F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > F: arch/riscv/boot/dts/thead/ > F: drivers/clk/thead/clk-th1520-ap.c > +F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > F: drivers/pinctrl/pinctrl-th1520.c > F: include/dt-bindings/clock/thead,th1520-clk-ap.h > > diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig > index 05cc07b8f48c..82030adaf16e 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig > +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig > @@ -228,6 +228,17 @@ config DWMAC_SUN8I > stmmac device driver. This driver is used for H3/A83T/A64 > EMAC ethernet controller. > > +config DWMAC_THEAD > + tristate "T-HEAD dwmac support" > + depends on OF && (ARCH_THEAD || COMPILE_TEST) > + select MFD_SYSCON > + help > + Support for ethernet controllers on T-HEAD RISC-V SoCs > + > + This selects the T-HEAD platform specific glue layer support for > + the stmmac device driver. This driver is used for T-HEAD TH1520 > + ethernet controller. > + > config DWMAC_IMX8 > tristate "NXP IMX8 DWMAC support" > default ARCH_MXC > diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile > index c2f0e91f6bf8..d065634c6223 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/Makefile > +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o > obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o > obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o > obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o > +obj-$(CONFIG_DWMAC_THEAD) += dwmac-thead.o > obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o > obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o > obj-$(CONFIG_DWMAC_LOONGSON1) += dwmac-loongson1.o > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > new file mode 100644 > index 000000000000..f2f94539c0d2 > --- /dev/null > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > @@ -0,0 +1,291 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * T-HEAD DWMAC platform driver > + * > + * Copyright (C) 2021 Alibaba Group Holding Limited. > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > + * > + */ > + > +#include <linux/bitfield.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/of_net.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +#include "stmmac_platform.h" > + > +#define GMAC_CLK_EN 0x00 > +#define GMAC_TX_CLK_EN BIT(1) > +#define GMAC_TX_CLK_N_EN BIT(2) > +#define GMAC_TX_CLK_OUT_EN BIT(3) > +#define GMAC_RX_CLK_EN BIT(4) > +#define GMAC_RX_CLK_N_EN BIT(5) > +#define GMAC_EPHY_REF_CLK_EN BIT(6) > +#define GMAC_RXCLK_DELAY_CTRL 0x04 > +#define GMAC_RXCLK_BYPASS BIT(15) > +#define GMAC_RXCLK_INVERT BIT(14) > +#define GMAC_RXCLK_DELAY_MASK GENMASK(4, 0) > +#define GMAC_RXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) > +#define GMAC_TXCLK_DELAY_CTRL 0x08 > +#define GMAC_TXCLK_BYPASS BIT(15) > +#define GMAC_TXCLK_INVERT BIT(14) > +#define GMAC_TXCLK_DELAY_MASK GENMASK(4, 0) > +#define GMAC_TXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) > +#define GMAC_PLLCLK_DIV 0x0c > +#define GMAC_PLLCLK_DIV_EN BIT(31) > +#define GMAC_PLLCLK_DIV_MASK GENMASK(7, 0) > +#define GMAC_PLLCLK_DIV_NUM(x) FIELD_PREP(GMAC_PLLCLK_DIV_MASK, (x)) > +#define GMAC_GTXCLK_SEL 0x18 > +#define GMAC_GTXCLK_SEL_PLL BIT(0) > +#define GMAC_INTF_CTRL 0x1c > +#define PHY_INTF_MASK BIT(0) > +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) > +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) > +#define GMAC_TXCLK_OEN 0x20 > +#define TXCLK_DIR_MASK BIT(0) > +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) > +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) > + > +#define GMAC_GMII_RGMII_RATE 125000000 > +#define GMAC_MII_RATE 25000000 > + > +static const struct regmap_config regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > +}; > + > +struct thead_dwmac { > + struct plat_stmmacenet_data *plat; > + struct regmap *apb_regmap; > + struct device *dev; > +}; > + > +static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) > +{ > + struct thead_dwmac *dwmac = plat->bsp_priv; > + u32 phyif; > + > + switch (plat->mac_interface) { > + case PHY_INTERFACE_MODE_MII: > + phyif = PHY_INTF_MII_GMII; > + break; > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + phyif = PHY_INTF_RGMII; > + break; > + default: > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > + plat->mac_interface); > + return -EINVAL; > + }; > + > + return regmap_write(dwmac->apb_regmap, GMAC_INTF_CTRL, phyif); > +} > + > +static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) > +{ > + struct thead_dwmac *dwmac = plat->bsp_priv; > + u32 txclk_dir; > + > + switch (plat->mac_interface) { > + case PHY_INTERFACE_MODE_MII: > + txclk_dir = TXCLK_DIR_INPUT; > + break; > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + txclk_dir = TXCLK_DIR_OUTPUT; > + break; > + default: > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > + plat->mac_interface); > + return -EINVAL; > + }; > + > + return regmap_write(dwmac->apb_regmap, GMAC_TXCLK_OEN, txclk_dir); > +} > + > +static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode) > +{ > + struct plat_stmmacenet_data *plat; > + struct thead_dwmac *dwmac = priv; > + unsigned long rate; > + u32 div; > + > + plat = dwmac->plat; > + > + switch (plat->mac_interface) { > + /* For MII, rxc/txc is provided by phy */ > + case PHY_INTERFACE_MODE_MII: > + return; > + > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + rate = clk_get_rate(plat->stmmac_clk); > + if (!rate || rate % GMAC_GMII_RGMII_RATE != 0 || > + rate % GMAC_MII_RATE != 0) { > + dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate); > + return; > + } > + > + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, GMAC_PLLCLK_DIV_EN, 0); > + > + switch (speed) { > + case SPEED_1000: > + div = rate / GMAC_GMII_RGMII_RATE; > + break; > + case SPEED_100: > + div = rate / GMAC_MII_RATE; > + break; > + case SPEED_10: > + div = rate * 10 / GMAC_MII_RATE; > + break; > + default: > + dev_err(dwmac->dev, "invalid speed %u\n", speed); > + return; > + } > + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, > + GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); > + > + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, > + GMAC_PLLCLK_DIV_EN, GMAC_PLLCLK_DIV_EN); > + break; > + default: > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > + plat->mac_interface); > + return; > + } > +} > + > +static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) > +{ > + struct thead_dwmac *dwmac = plat->bsp_priv; > + int err; > + u32 reg; > + > + switch (plat->mac_interface) { > + case PHY_INTERFACE_MODE_MII: > + reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; > + break; > + > + case PHY_INTERFACE_MODE_RGMII: > + case PHY_INTERFACE_MODE_RGMII_ID: > + case PHY_INTERFACE_MODE_RGMII_RXID: > + case PHY_INTERFACE_MODE_RGMII_TXID: > + /* use pll */ > + err = regmap_write(dwmac->apb_regmap, GMAC_GTXCLK_SEL, GMAC_GTXCLK_SEL_PLL); > + if (err) > + return dev_err_probe(dwmac->dev, err, > + "failed to set phy interface\n"); > + > + reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | > + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; > + break; > + > + default: > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > + plat->mac_interface); > + return -EINVAL; > + } > + > + return regmap_write(dwmac->apb_regmap, GMAC_CLK_EN, reg); > +} > + > +static int thead_dwmac_init(struct platform_device *pdev, void *priv) > +{ > + struct thead_dwmac *dwmac = priv; > + int ret; > + > + ret = thead_dwmac_set_phy_if(dwmac->plat); > + if (ret) > + return ret; > + > + ret = thead_dwmac_set_txclk_dir(dwmac->plat); > + if (ret) > + return ret; > + > + ret = regmap_write(dwmac->apb_regmap, GMAC_RXCLK_DELAY_CTRL, > + GMAC_RXCLK_DELAY_VAL(0)); > + if (ret) > + return dev_err_probe(dwmac->dev, ret, > + "failed to set GMAC RX clock delay\n"); > + > + ret = regmap_write(dwmac->apb_regmap, GMAC_TXCLK_DELAY_CTRL, > + GMAC_TXCLK_DELAY_VAL(0)); > + if (ret) > + return dev_err_probe(dwmac->dev, ret, > + "failed to set GMAC TX clock delay\n"); > + > + return thead_dwmac_enable_clk(dwmac->plat); > +} > + > +static int thead_dwmac_probe(struct platform_device *pdev) > +{ > + struct stmmac_resources stmmac_res; > + struct plat_stmmacenet_data *plat; > + struct thead_dwmac *dwmac; > + void __iomem *apb; > + int ret; > + > + ret = stmmac_get_platform_resources(pdev, &stmmac_res); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "failed to get resources\n"); > + > + plat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); > + if (IS_ERR(plat)) > + return dev_err_probe(&pdev->dev, PTR_ERR(plat), > + "dt configuration failed\n"); > + > + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); > + if (!dwmac) > + return -ENOMEM; > + > + apb = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(apb)) > + return dev_err_probe(&pdev->dev, PTR_ERR(apb), > + "Failed to remap gmac apb registers\n"); > + > + dwmac->apb_regmap = devm_regmap_init_mmio(&pdev->dev, apb, ®map_config); > + if (IS_ERR(dwmac->apb_regmap)) > + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->apb_regmap), > + "Failed to access gmac apb registers\n"); Why do you need to convert the APB range to a regmap? As far as I can tell it's just regular 32bit memory mapped registers, so should work fine with just readl()/writel() /Emil > + > + dwmac->dev = &pdev->dev; > + dwmac->plat = plat; > + plat->bsp_priv = dwmac; > + plat->fix_mac_speed = thead_dwmac_fix_speed; > + plat->init = thead_dwmac_init; > + > + return devm_stmmac_pltfr_probe(pdev, plat, &stmmac_res); > +} > + > +static const struct of_device_id thead_dwmac_match[] = { > + { .compatible = "thead,th1520-gmac" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, thead_dwmac_match); > + > +static struct platform_driver thead_dwmac_driver = { > + .probe = thead_dwmac_probe, > + .driver = { > + .name = "thead-dwmac", > + .pm = &stmmac_pltfr_pm_ops, > + .of_match_table = thead_dwmac_match, > + }, > +}; > +module_platform_driver(thead_dwmac_driver); > + > +MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); > +MODULE_AUTHOR("Drew Fustini <drew@pdp7.com>"); > +MODULE_DESCRIPTION("T-HEAD DWMAC platform driver"); > +MODULE_LICENSE("GPL"); > > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC 2024-10-01 9:48 ` Emil Renner Berthing @ 2024-10-03 5:52 ` Drew Fustini 0 siblings, 0 replies; 10+ messages in thread From: Drew Fustini @ 2024-10-03 5:52 UTC (permalink / raw) To: Emil Renner Berthing Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv On Tue, Oct 01, 2024 at 02:48:13AM -0700, Emil Renner Berthing wrote: > Drew Fustini wrote: > > From: Jisheng Zhang <jszhang@kernel.org> > > > > Add dwmac glue driver to support the DesignWare-based GMAC controllers > > on the T-HEAD TH1520 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > [esmil: rename plat->interface -> plat->mac_interface, > > use devm_stmmac_probe_config_dt()] > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > [drew: convert from stmmac_dvr_probe() to devm_stmmac_pltfr_probe()] > > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> > > --- > > MAINTAINERS | 1 + > > drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + > > drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + > > drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 291 ++++++++++++++++++++++ > > 4 files changed, 304 insertions(+) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 9e50107efb37..1d24863c01df 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -19946,6 +19946,7 @@ F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml > > F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml > > F: arch/riscv/boot/dts/thead/ > > F: drivers/clk/thead/clk-th1520-ap.c > > +F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > > F: drivers/pinctrl/pinctrl-th1520.c > > F: include/dt-bindings/clock/thead,th1520-clk-ap.h > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig > > index 05cc07b8f48c..82030adaf16e 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig > > +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig > > @@ -228,6 +228,17 @@ config DWMAC_SUN8I > > stmmac device driver. This driver is used for H3/A83T/A64 > > EMAC ethernet controller. > > > > +config DWMAC_THEAD > > + tristate "T-HEAD dwmac support" > > + depends on OF && (ARCH_THEAD || COMPILE_TEST) > > + select MFD_SYSCON > > + help > > + Support for ethernet controllers on T-HEAD RISC-V SoCs > > + > > + This selects the T-HEAD platform specific glue layer support for > > + the stmmac device driver. This driver is used for T-HEAD TH1520 > > + ethernet controller. > > + > > config DWMAC_IMX8 > > tristate "NXP IMX8 DWMAC support" > > default ARCH_MXC > > diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile > > index c2f0e91f6bf8..d065634c6223 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/Makefile > > +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile > > @@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o > > obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o > > obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o > > obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o > > +obj-$(CONFIG_DWMAC_THEAD) += dwmac-thead.o > > obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o > > obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o > > obj-$(CONFIG_DWMAC_LOONGSON1) += dwmac-loongson1.o > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > > new file mode 100644 > > index 000000000000..f2f94539c0d2 > > --- /dev/null > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c > > @@ -0,0 +1,291 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * T-HEAD DWMAC platform driver > > + * > > + * Copyright (C) 2021 Alibaba Group Holding Limited. > > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> > > + * > > + */ > > + > > +#include <linux/bitfield.h> > > +#include <linux/module.h> > > +#include <linux/of.h> > > +#include <linux/of_device.h> > > +#include <linux/of_net.h> > > +#include <linux/platform_device.h> > > +#include <linux/regmap.h> > > + > > +#include "stmmac_platform.h" > > + > > +#define GMAC_CLK_EN 0x00 > > +#define GMAC_TX_CLK_EN BIT(1) > > +#define GMAC_TX_CLK_N_EN BIT(2) > > +#define GMAC_TX_CLK_OUT_EN BIT(3) > > +#define GMAC_RX_CLK_EN BIT(4) > > +#define GMAC_RX_CLK_N_EN BIT(5) > > +#define GMAC_EPHY_REF_CLK_EN BIT(6) > > +#define GMAC_RXCLK_DELAY_CTRL 0x04 > > +#define GMAC_RXCLK_BYPASS BIT(15) > > +#define GMAC_RXCLK_INVERT BIT(14) > > +#define GMAC_RXCLK_DELAY_MASK GENMASK(4, 0) > > +#define GMAC_RXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) > > +#define GMAC_TXCLK_DELAY_CTRL 0x08 > > +#define GMAC_TXCLK_BYPASS BIT(15) > > +#define GMAC_TXCLK_INVERT BIT(14) > > +#define GMAC_TXCLK_DELAY_MASK GENMASK(4, 0) > > +#define GMAC_TXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) > > +#define GMAC_PLLCLK_DIV 0x0c > > +#define GMAC_PLLCLK_DIV_EN BIT(31) > > +#define GMAC_PLLCLK_DIV_MASK GENMASK(7, 0) > > +#define GMAC_PLLCLK_DIV_NUM(x) FIELD_PREP(GMAC_PLLCLK_DIV_MASK, (x)) > > +#define GMAC_GTXCLK_SEL 0x18 > > +#define GMAC_GTXCLK_SEL_PLL BIT(0) > > +#define GMAC_INTF_CTRL 0x1c > > +#define PHY_INTF_MASK BIT(0) > > +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) > > +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) > > +#define GMAC_TXCLK_OEN 0x20 > > +#define TXCLK_DIR_MASK BIT(0) > > +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) > > +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) > > + > > +#define GMAC_GMII_RGMII_RATE 125000000 > > +#define GMAC_MII_RATE 25000000 > > + > > +static const struct regmap_config regmap_config = { > > + .reg_bits = 32, > > + .val_bits = 32, > > + .reg_stride = 4, > > +}; > > + > > +struct thead_dwmac { > > + struct plat_stmmacenet_data *plat; > > + struct regmap *apb_regmap; > > + struct device *dev; > > +}; > > + > > +static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) > > +{ > > + struct thead_dwmac *dwmac = plat->bsp_priv; > > + u32 phyif; > > + > > + switch (plat->mac_interface) { > > + case PHY_INTERFACE_MODE_MII: > > + phyif = PHY_INTF_MII_GMII; > > + break; > > + case PHY_INTERFACE_MODE_RGMII: > > + case PHY_INTERFACE_MODE_RGMII_ID: > > + case PHY_INTERFACE_MODE_RGMII_TXID: > > + case PHY_INTERFACE_MODE_RGMII_RXID: > > + phyif = PHY_INTF_RGMII; > > + break; > > + default: > > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > > + plat->mac_interface); > > + return -EINVAL; > > + }; > > + > > + return regmap_write(dwmac->apb_regmap, GMAC_INTF_CTRL, phyif); > > +} > > + > > +static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) > > +{ > > + struct thead_dwmac *dwmac = plat->bsp_priv; > > + u32 txclk_dir; > > + > > + switch (plat->mac_interface) { > > + case PHY_INTERFACE_MODE_MII: > > + txclk_dir = TXCLK_DIR_INPUT; > > + break; > > + case PHY_INTERFACE_MODE_RGMII: > > + case PHY_INTERFACE_MODE_RGMII_ID: > > + case PHY_INTERFACE_MODE_RGMII_TXID: > > + case PHY_INTERFACE_MODE_RGMII_RXID: > > + txclk_dir = TXCLK_DIR_OUTPUT; > > + break; > > + default: > > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > > + plat->mac_interface); > > + return -EINVAL; > > + }; > > + > > + return regmap_write(dwmac->apb_regmap, GMAC_TXCLK_OEN, txclk_dir); > > +} > > + > > +static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode) > > +{ > > + struct plat_stmmacenet_data *plat; > > + struct thead_dwmac *dwmac = priv; > > + unsigned long rate; > > + u32 div; > > + > > + plat = dwmac->plat; > > + > > + switch (plat->mac_interface) { > > + /* For MII, rxc/txc is provided by phy */ > > + case PHY_INTERFACE_MODE_MII: > > + return; > > + > > + case PHY_INTERFACE_MODE_RGMII: > > + case PHY_INTERFACE_MODE_RGMII_ID: > > + case PHY_INTERFACE_MODE_RGMII_RXID: > > + case PHY_INTERFACE_MODE_RGMII_TXID: > > + rate = clk_get_rate(plat->stmmac_clk); > > + if (!rate || rate % GMAC_GMII_RGMII_RATE != 0 || > > + rate % GMAC_MII_RATE != 0) { > > + dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate); > > + return; > > + } > > + > > + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, GMAC_PLLCLK_DIV_EN, 0); > > + > > + switch (speed) { > > + case SPEED_1000: > > + div = rate / GMAC_GMII_RGMII_RATE; > > + break; > > + case SPEED_100: > > + div = rate / GMAC_MII_RATE; > > + break; > > + case SPEED_10: > > + div = rate * 10 / GMAC_MII_RATE; > > + break; > > + default: > > + dev_err(dwmac->dev, "invalid speed %u\n", speed); > > + return; > > + } > > + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, > > + GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); > > + > > + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, > > + GMAC_PLLCLK_DIV_EN, GMAC_PLLCLK_DIV_EN); > > + break; > > + default: > > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > > + plat->mac_interface); > > + return; > > + } > > +} > > + > > +static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) > > +{ > > + struct thead_dwmac *dwmac = plat->bsp_priv; > > + int err; > > + u32 reg; > > + > > + switch (plat->mac_interface) { > > + case PHY_INTERFACE_MODE_MII: > > + reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; > > + break; > > + > > + case PHY_INTERFACE_MODE_RGMII: > > + case PHY_INTERFACE_MODE_RGMII_ID: > > + case PHY_INTERFACE_MODE_RGMII_RXID: > > + case PHY_INTERFACE_MODE_RGMII_TXID: > > + /* use pll */ > > + err = regmap_write(dwmac->apb_regmap, GMAC_GTXCLK_SEL, GMAC_GTXCLK_SEL_PLL); > > + if (err) > > + return dev_err_probe(dwmac->dev, err, > > + "failed to set phy interface\n"); > > + > > + reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | > > + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; > > + break; > > + > > + default: > > + dev_err(dwmac->dev, "unsupported phy interface %d\n", > > + plat->mac_interface); > > + return -EINVAL; > > + } > > + > > + return regmap_write(dwmac->apb_regmap, GMAC_CLK_EN, reg); > > +} > > + > > +static int thead_dwmac_init(struct platform_device *pdev, void *priv) > > +{ > > + struct thead_dwmac *dwmac = priv; > > + int ret; > > + > > + ret = thead_dwmac_set_phy_if(dwmac->plat); > > + if (ret) > > + return ret; > > + > > + ret = thead_dwmac_set_txclk_dir(dwmac->plat); > > + if (ret) > > + return ret; > > + > > + ret = regmap_write(dwmac->apb_regmap, GMAC_RXCLK_DELAY_CTRL, > > + GMAC_RXCLK_DELAY_VAL(0)); > > + if (ret) > > + return dev_err_probe(dwmac->dev, ret, > > + "failed to set GMAC RX clock delay\n"); > > + > > + ret = regmap_write(dwmac->apb_regmap, GMAC_TXCLK_DELAY_CTRL, > > + GMAC_TXCLK_DELAY_VAL(0)); > > + if (ret) > > + return dev_err_probe(dwmac->dev, ret, > > + "failed to set GMAC TX clock delay\n"); > > + > > + return thead_dwmac_enable_clk(dwmac->plat); > > +} > > + > > +static int thead_dwmac_probe(struct platform_device *pdev) > > +{ > > + struct stmmac_resources stmmac_res; > > + struct plat_stmmacenet_data *plat; > > + struct thead_dwmac *dwmac; > > + void __iomem *apb; > > + int ret; > > + > > + ret = stmmac_get_platform_resources(pdev, &stmmac_res); > > + if (ret) > > + return dev_err_probe(&pdev->dev, ret, > > + "failed to get resources\n"); > > + > > + plat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); > > + if (IS_ERR(plat)) > > + return dev_err_probe(&pdev->dev, PTR_ERR(plat), > > + "dt configuration failed\n"); > > + > > + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); > > + if (!dwmac) > > + return -ENOMEM; > > + > > + apb = devm_platform_ioremap_resource(pdev, 1); > > + if (IS_ERR(apb)) > > + return dev_err_probe(&pdev->dev, PTR_ERR(apb), > > + "Failed to remap gmac apb registers\n"); > > + > > + dwmac->apb_regmap = devm_regmap_init_mmio(&pdev->dev, apb, ®map_config); > > + if (IS_ERR(dwmac->apb_regmap)) > > + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->apb_regmap), > > + "Failed to access gmac apb registers\n"); > > Why do you need to convert the APB range to a regmap? As far as I can tell it's > just regular 32bit memory mapped registers, so should work fine with just > readl()/writel() Good point, I don't think there is any benefit to using regmap. I will change the next revision to use writel() instead. I just tested this and the network interface still works okay. Thanks, Drew diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c index f2f94539c0d2..df2fe0fdd128 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c @@ -13,7 +13,6 @@ #include <linux/of_device.h> #include <linux/of_net.h> #include <linux/platform_device.h> -#include <linux/regmap.h> #include "stmmac_platform.h" @@ -52,15 +51,9 @@ #define GMAC_GMII_RGMII_RATE 125000000 #define GMAC_MII_RATE 25000000 -static const struct regmap_config regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, -}; - struct thead_dwmac { struct plat_stmmacenet_data *plat; - struct regmap *apb_regmap; + void __iomem *apb_base; struct device *dev; }; @@ -85,7 +78,8 @@ static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) return -EINVAL; }; - return regmap_write(dwmac->apb_regmap, GMAC_INTF_CTRL, phyif); + writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL); + return 0; } static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) @@ -109,7 +103,8 @@ static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) return -EINVAL; }; - return regmap_write(dwmac->apb_regmap, GMAC_TXCLK_OEN, txclk_dir); + writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN); + return 0; } static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode) @@ -117,7 +112,7 @@ static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int m struct plat_stmmacenet_data *plat; struct thead_dwmac *dwmac = priv; unsigned long rate; - u32 div; + u32 div, reg; plat = dwmac->plat; @@ -137,7 +132,7 @@ static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int m return; } - regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, GMAC_PLLCLK_DIV_EN, 0); + writel(FIELD_PREP(GMAC_PLLCLK_DIV_EN, 0), dwmac->apb_base + GMAC_PLLCLK_DIV); switch (speed) { case SPEED_1000: @@ -153,11 +148,10 @@ static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int m dev_err(dwmac->dev, "invalid speed %u\n", speed); return; } - regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, - GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); - regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, - GMAC_PLLCLK_DIV_EN, GMAC_PLLCLK_DIV_EN); + reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) | + FIELD_PREP(GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); + writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV); break; default: dev_err(dwmac->dev, "unsupported phy interface %d\n", @@ -169,7 +163,6 @@ static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int m static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) { struct thead_dwmac *dwmac = plat->bsp_priv; - int err; u32 reg; switch (plat->mac_interface) { @@ -182,11 +175,7 @@ static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: /* use pll */ - err = regmap_write(dwmac->apb_regmap, GMAC_GTXCLK_SEL, GMAC_GTXCLK_SEL_PLL); - if (err) - return dev_err_probe(dwmac->dev, err, - "failed to set phy interface\n"); - + writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL); reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; break; @@ -197,7 +186,8 @@ static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) return -EINVAL; } - return regmap_write(dwmac->apb_regmap, GMAC_CLK_EN, reg); + writel(reg, dwmac->apb_base + GMAC_CLK_EN); + return 0; } static int thead_dwmac_init(struct platform_device *pdev, void *priv) @@ -213,17 +203,8 @@ static int thead_dwmac_init(struct platform_device *pdev, void *priv) if (ret) return ret; - ret = regmap_write(dwmac->apb_regmap, GMAC_RXCLK_DELAY_CTRL, - GMAC_RXCLK_DELAY_VAL(0)); - if (ret) - return dev_err_probe(dwmac->dev, ret, - "failed to set GMAC RX clock delay\n"); - - ret = regmap_write(dwmac->apb_regmap, GMAC_TXCLK_DELAY_CTRL, - GMAC_TXCLK_DELAY_VAL(0)); - if (ret) - return dev_err_probe(dwmac->dev, ret, - "failed to set GMAC TX clock delay\n"); + writel(GMAC_RXCLK_DELAY_VAL(0), dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL); + writel(GMAC_TXCLK_DELAY_VAL(0), dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL); return thead_dwmac_enable_clk(dwmac->plat); } @@ -255,13 +236,9 @@ static int thead_dwmac_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(apb), "Failed to remap gmac apb registers\n"); - dwmac->apb_regmap = devm_regmap_init_mmio(&pdev->dev, apb, ®map_config); - if (IS_ERR(dwmac->apb_regmap)) - return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->apb_regmap), - "Failed to access gmac apb registers\n"); - dwmac->dev = &pdev->dev; dwmac->plat = plat; + dwmac->apb_base = apb; plat->bsp_priv = dwmac; plat->fix_mac_speed = thead_dwmac_fix_speed; plat->init = thead_dwmac_init; ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 3/3] riscv: dts: thead: Add TH1520 ethernet nodes 2024-10-01 6:23 [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Drew Fustini 2024-10-01 6:23 ` [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support Drew Fustini 2024-10-01 6:23 ` [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC Drew Fustini @ 2024-10-01 6:23 ` Drew Fustini 2024-10-02 15:34 ` [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Andrew Lunn 3 siblings, 0 replies; 10+ messages in thread From: Drew Fustini @ 2024-10-01 6:23 UTC (permalink / raw) To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, Drew Fustini Cc: netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv From: Emil Renner Berthing <emil.renner.berthing@canonical.com> Add gmac, mdio, and phy nodes to enable the gigabit Ethernet ports on the BeagleV Ahead and Sipeed Lichee Pi 4a boards. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [drew: change apb registers from syscon to second reg of gmac node, add phy reset delay properties for beaglev ahead] Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 91 +++++++++++++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 129 +++++++++++++++++++++ arch/riscv/boot/dts/thead/th1520.dtsi | 50 ++++++++ 3 files changed, 270 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 5a5888f4eda6..ddcee6298939 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -15,6 +15,7 @@ / { compatible = "beagle,beaglev-ahead", "thead,th1520"; aliases { + ethernet0 = &gmac0; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -108,6 +109,25 @@ &sdio0 { status = "okay"; }; +&gmac0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_pins>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <50000>; + }; +}; + &padctrl_aosys { led_pins: led-0 { led-pins { @@ -127,6 +147,77 @@ led-pins { }; &padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins = "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mdc-pins { + pins = "GMAC0_MDC"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mdio-pins { + pins = "GMAC0_MDIO"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + + phy-reset-pins { + pins = "GMAC0_COL"; /* GPIO3_21 */ + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + phy-interrupt-pins { + pins = "GMAC0_CRS"; /* GPIO3_22 */ + function = "gpio"; + bias-pull-up; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins = "UART0_TXD"; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index ca84bc2039ef..6e3260eb53f4 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -11,6 +11,11 @@ / { model = "Sipeed Lichee Module 4A"; compatible = "sipeed,lichee-module-4a", "thead,th1520"; + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; @@ -25,6 +30,16 @@ &osc_32k { clock-frequency = <32768>; }; +&dmac0 { + status = "okay"; +}; + +&aogpio { + gpio-line-names = "", "", "", + "GPIO00", + "GPIO04"; +}; + &aonsys_clk { clock-frequency = <73728000>; }; @@ -55,6 +70,22 @@ &sdio0 { status = "okay"; }; +&gmac0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + &gpio0 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -87,3 +118,101 @@ &gpio3 { "GPIO09", "GPIO10"; }; + +&mdio0 { + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + }; +}; + +&padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins = "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + gmac1_pins: gmac1-0 { + tx-pins { + pins = "GPIO2_18", /* GMAC1_TX_CLK */ + "GPIO2_20", /* GMAC1_TXEN */ + "GPIO2_21", /* GMAC1_TXD0 */ + "GPIO2_22", /* GMAC1_TXD1 */ + "GPIO2_23", /* GMAC1_TXD2 */ + "GPIO2_24"; /* GMAC1_TXD3 */ + function = "gmac1"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GPIO2_19", /* GMAC1_RX_CLK */ + "GPIO2_25", /* GMAC1_RXDV */ + "GPIO2_30", /* GMAC1_RXD0 */ + "GPIO2_31", /* GMAC1_RXD1 */ + "GPIO3_0", /* GMAC1_RXD2 */ + "GPIO3_1"; /* GMAC1_RXD3 */ + function = "gmac1"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + mdio0_pins: mdio0-0 { + mdc-pins { + pins = "GMAC0_MDC"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mdio-pins { + pins = "GMAC0_MDIO"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index b958f249930e..1228c7dd80c6 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -222,6 +222,12 @@ aonsys_clk: aonsys-clk { #clock-cells = <0>; }; + stmmac_axi_config: stmmac-axi-config { + snps,wr_osr_lmt = <15>; + snps,rd_osr_lmt = <15>; + snps,blen = <0 0 64 32 0 0 0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -273,6 +279,50 @@ uart0: serial@ffe7014000 { status = "disabled"; }; + gmac1: ethernet@ffe7060000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; + reg-names = "dwmac", "apb"; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; + clock-names = "stmmaceth", "pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,axi-config = <&stmmac_axi_config>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gmac0: ethernet@ffe7070000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; + reg-names = "dwmac", "apb"; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; + clock-names = "stmmaceth", "pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,axi-config = <&stmmac_axi_config>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + emmc: mmc@ffe7080000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7080000 0x0 0x10000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC 2024-10-01 6:23 [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Drew Fustini ` (2 preceding siblings ...) 2024-10-01 6:23 ` [PATCH v3 3/3] riscv: dts: thead: Add TH1520 ethernet nodes Drew Fustini @ 2024-10-02 15:34 ` Andrew Lunn 3 siblings, 0 replies; 10+ messages in thread From: Andrew Lunn @ 2024-10-02 15:34 UTC (permalink / raw) To: Drew Fustini Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alexandre Torgue, Giuseppe Cavallaro, Jose Abreu, Jisheng Zhang, Maxime Coquelin, Emil Renner Berthing, Drew Fustini, Guo Ren, Fu Wei, Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou, netdev, devicetree, linux-kernel, linux-arm-kernel, linux-riscv On Mon, Sep 30, 2024 at 11:23:23PM -0700, Drew Fustini wrote: > This series is based on 6.12-rc1 and depends on this pinctrl series: This is a network driver, so should be based on net-next/main. https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html > 20240930-th1520-pinctrl-v3-0-32cea2bdbecb@tenstorrent.com Everything should meet up in linux-next, where it should work since all the dependencies are there. Andrew --- pw-bot: cr ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-10-03 10:42 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-10-01 6:23 [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Drew Fustini 2024-10-01 6:23 ` [PATCH v3 1/3] dt-bindings: net: Add T-HEAD dwmac support Drew Fustini 2024-10-01 6:58 ` Krzysztof Kozlowski 2024-10-02 19:08 ` Drew Fustini 2024-10-03 10:42 ` Krzysztof Kozlowski 2024-10-01 6:23 ` [PATCH v3 2/3] net: stmmac: Add glue layer for T-HEAD TH1520 SoC Drew Fustini 2024-10-01 9:48 ` Emil Renner Berthing 2024-10-03 5:52 ` Drew Fustini 2024-10-01 6:23 ` [PATCH v3 3/3] riscv: dts: thead: Add TH1520 ethernet nodes Drew Fustini 2024-10-02 15:34 ` [PATCH v3 0/3] Add the dwmac driver support for T-HEAD TH1520 SoC Andrew Lunn
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