[PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This series aims to add PCS support for the Renesas RZ/T2H and RZ/N2H SoCs
These SoCs include a MII converter (MIIC) that converts MII to RMII/RGMII
or can be set in pass-through mode for MII similar to the RZ/N1 SoC. The
MIIC is used in conjunction with the Ethernet switch (ETHSW) available on
these SoCs.

v1->v2:
- Dropped regx in title and description in patch 1/9.
- As done for other IPs used T2H compatible as a fallback for N2H.
- Renamed pcs-rzt2h-miic.h -> renesas,r9a09g077-pcs-miic.h
- Added matrix table in the new header file.
- Corrected the resets check for RZ/N1.
- Updated the commit message in patch 1/9.
- Dropped regx in config description in patch 9/9.
- Dropped patch "net: pcs: rzn1-miic: Add PCS validate callback
  for RZ/T2H MIIC" is this already taken care in commit 508df2de7b3e
  as pointed by Russell King.

Cheers,
Prabhakar

Lad Prabhakar (9):
  dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H
    support
  net: pcs: rzn1-miic: Drop trailing comma from of_device_id table
  net: pcs: rzn1-miic: Add missing include files
  net: pcs: rzn1-miic: Move configuration data to SoC-specific struct
  net: pcs: rzn1-miic: move port range handling into SoC data
  net: pcs: rzn1-miic: Make switch mode mask SoC-specific
  net: pcs: rzn1-miic: Add support to handle resets
  net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock
  net: pcs: rzn1-miic: Add RZ/T2H MIIC support

 .../bindings/net/pcs/renesas,rzn1-miic.yaml   | 177 ++++++++---
 drivers/net/pcs/Kconfig                       |  11 +-
 drivers/net/pcs/pcs-rzn1-miic.c               | 296 +++++++++++++++---
 .../net/renesas,r9a09g077-pcs-miic.h          |  36 +++
 4 files changed, 419 insertions(+), 101 deletions(-)
 create mode 100644 include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h

-- 
2.51.0

[PATCH net-next v2 1/9] dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add device tree binding support for RZ/T2H and RZ/N2H SoCs to the
existing RZ/N1 MIIC converter binding. These SoCs share similar MIIC
functionality but have architectural differences that require schema
updates.

Add new compatible strings "renesas,r9a09g077-miic" for RZ/T2H and
"renesas,r9a09g087-miic" for RZ/N2H, with the latter falling back to
the RZ/T2H variant. The new SoCs require reset support with two reset
lines for converter register reset and converter reset, which are not
present on RZ/N1.

Update port configurations to accommodate the different architectures.
RZ/N1 supports 5 ports numbered 1-5 with complex input mappings
covering indices 0-13, while RZ/T2H and RZ/N2H support 4 ports
numbered 0-3 with simplified input mappings covering indices 0-8.
Extend the switch port configuration property to support value 0 for
the new SoCs.

Add a new dt-bindings header file with media interface connection
matrix constants that map GMAC, ESC, and ETHSW ports to numeric
identifiers for use with RZ/T2H and RZ/N2H device trees.

Update DT schema validation to ensure proper port numbering and input
mappings per SoC variant.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- Dropped regx in title and description.
- As done for other IPs used T2H compatible as a fallback for N2H.
- Renamed pcs-rzt2h-miic.h -> renesas,r9a09g077-pcs-miic.h
- Added matrix table in the new header file.
- Corrected the resets check for RZ/N1.
- Updated the commit message.
---
 .../bindings/net/pcs/renesas,rzn1-miic.yaml   | 177 +++++++++++++-----
 .../net/renesas,r9a09g077-pcs-miic.h          |  36 ++++
 2 files changed, 165 insertions(+), 48 deletions(-)
 create mode 100644 include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h

diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
index 2d33bbab7163..3adbcf56d2be 100644
--- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
+++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
@@ -4,14 +4,15 @@
 $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/N1 MII converter
+title: Renesas RZ/N1, RZ/N2H and RZ/T2H MII converter
 
 maintainers:
   - Clément Léger <clement.leger@bootlin.com>
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description: |
-  This MII converter is present on the Renesas RZ/N1 SoC family. It is
-  responsible to do MII passthrough or convert it to RMII/RGMII.
+  This MII converter is present on the Renesas RZ/N1, RZ/N2H and RZ/T2H SoC
+  families. It is responsible to do MII passthrough or convert it to RMII/RGMII.
 
 properties:
   '#address-cells':
@@ -21,10 +22,16 @@ properties:
     const: 0
 
   compatible:
-    items:
-      - enum:
-          - renesas,r9a06g032-miic
-      - const: renesas,rzn1-miic
+    oneOf:
+      - items:
+          - enum:
+              - renesas,r9a06g032-miic
+          - const: renesas,rzn1-miic
+      - items:
+          - const: renesas,r9a09g077-miic # RZ/T2H
+      - items:
+          - const: renesas,r9a09g087-miic # RZ/N2H
+          - const: renesas,r9a09g077-miic
 
   reg:
     maxItems: 1
@@ -43,11 +50,22 @@ properties:
       - const: rmii_ref
       - const: hclk
 
+  resets:
+    items:
+      - description: Converter register reset
+      - description: Converter reset
+
+  reset-names:
+    items:
+      - const: rst
+      - const: crst
+
   renesas,miic-switch-portin:
     description: MII Switch PORTIN configuration. This value should use one of
-      the values defined in dt-bindings/net/pcs-rzn1-miic.h.
+      the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC and
+      include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [1, 2]
+    enum: [0, 1, 2]
 
   power-domains:
     maxItems: 1
@@ -60,11 +78,12 @@ patternProperties:
     properties:
       reg:
         description: MII Converter port number.
-        enum: [1, 2, 3, 4, 5]
+        enum: [0, 1, 2, 3, 4, 5]
 
       renesas,miic-input:
         description: Converter input port configuration. This value should use
-          one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
+          one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC
+          and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
         $ref: /schemas/types.yaml#/definitions/uint32
 
     required:
@@ -73,47 +92,109 @@ patternProperties:
 
     additionalProperties: false
 
-    allOf:
-      - if:
-          properties:
-            reg:
-              const: 1
-        then:
-          properties:
-            renesas,miic-input:
-              const: 0
-      - if:
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,rzn1-miic
+    then:
+      properties:
+        renesas,miic-switch-portin:
+          enum: [1, 2]
+        resets: false
+        reset-names: false
+      patternProperties:
+        "^mii-conv@[0-5]$":
           properties:
             reg:
-              const: 2
-        then:
-          properties:
-            renesas,miic-input:
-              enum: [1, 11]
-      - if:
-          properties:
-            reg:
-              const: 3
-        then:
-          properties:
-            renesas,miic-input:
-              enum: [7, 10]
-      - if:
+              enum: [1, 2, 3, 4, 5]
+          allOf:
+            - if:
+                properties:
+                  reg:
+                    const: 1
+              then:
+                properties:
+                  renesas,miic-input:
+                    const: 0
+            - if:
+                properties:
+                  reg:
+                    const: 2
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [1, 11]
+            - if:
+                properties:
+                  reg:
+                    const: 3
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [7, 10]
+            - if:
+                properties:
+                  reg:
+                    const: 4
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [4, 6, 9, 13]
+            - if:
+                properties:
+                  reg:
+                    const: 5
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [3, 5, 8, 12]
+    else:
+      properties:
+        renesas,miic-switch-portin:
+          const: 0
+      required:
+        - resets
+        - reset-names
+      patternProperties:
+        "^mii-conv@[0-5]$":
           properties:
             reg:
-              const: 4
-        then:
-          properties:
-            renesas,miic-input:
-              enum: [4, 6, 9, 13]
-      - if:
-          properties:
-            reg:
-              const: 5
-        then:
-          properties:
-            renesas,miic-input:
-              enum: [3, 5, 8, 12]
+              enum: [0, 1, 2, 3]
+          allOf:
+            - if:
+                properties:
+                  reg:
+                    const: 0
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [0, 3, 6]
+            - if:
+                properties:
+                  reg:
+                    const: 1
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [1, 4, 7]
+            - if:
+                properties:
+                  reg:
+                    const: 2
+              then:
+                properties:
+                  renesas,miic-input:
+                    enum: [2, 5, 8]
+            - if:
+                properties:
+                  reg:
+                    const: 3
+              then:
+                properties:
+                  renesas,miic-input:
+                    const: 1
 
 required:
   - '#address-cells'
diff --git a/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h
new file mode 100644
index 000000000000..43a2b5743a63
--- /dev/null
+++ b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corporation.
+ */
+
+#ifndef _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
+#define _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
+
+/*
+ * Media Interface Connection Matrix
+ * ===========================================================
+ *
+ * Selects the function of the Media interface of the MAC to be used
+ *
+ * SW_MODE[2:0] | Port 0      | Port 1      | Port 2      | Port 3
+ * -------------|-------------|-------------|-------------|-------------
+ * 000b         | ETHSW Port0 | ETHSW Port1 | ETHSW Port2 | GMAC1
+ * 001b         | ESC Port0   | ESC Port1   | GMAC2       | GMAC1
+ * 010b         | ESC Port0   | ESC Port1   | ETHSW Port2 | GMAC1
+ * 011b         | ESC Port0   | ESC Port1   | ESC Port2   | GMAC1
+ * 100b         | ETHSW Port0 | ESC Port1   | ESC Port2   | GMAC1
+ * 101b         | ETHSW Port0 | ESC Port1   | ETHSW Port2 | GMAC1
+ * 110b         | ETHSW Port0 | ETHSW Port1 | GMAC2       | GMAC1
+ * 111b         | GMAC0       | GMAC1       | GMAC2       | -
+ */
+#define ETHSS_GMAC0_PORT		0
+#define ETHSS_GMAC1_PORT		1
+#define ETHSS_GMAC2_PORT		2
+#define ETHSS_ESC_PORT0			3
+#define ETHSS_ESC_PORT1			4
+#define ETHSS_ESC_PORT2			5
+#define ETHSS_ETHSW_PORT0		6
+#define ETHSS_ETHSW_PORT1		7
+#define ETHSS_ETHSW_PORT2		8
+
+#endif
-- 
2.51.0

[PATCH net-next v2 2/9] net: pcs: rzn1-miic: Drop trailing comma from of_device_id table

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Remove the trailing comma after the sentinel entry in the
of_device_id match table.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index ce73d9474d5b..c1bd7cd58478 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -529,7 +529,7 @@ static void miic_remove(struct platform_device *pdev)
 
 static const struct of_device_id miic_of_mtable[] = {
 	{ .compatible = "renesas,rzn1-miic" },
-	{ /* sentinel */ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, miic_of_mtable);
 
-- 
2.51.0

[PATCH net-next v2 3/9] net: pcs: rzn1-miic: Add missing include files

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The pcs-rzn1-miic driver makes use of ARRAY_SIZE(), BIT() and GENMASK()
macros but does not explicitly include the headers where they are
defined. Add the missing <linux/array_size.h> and <linux/bits.h>
includes.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index c1bd7cd58478..adf4b5e4741c 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -5,6 +5,8 @@
  * Clément Léger <clement.leger@bootlin.com>
  */
 
+#include <linux/array_size.h>
+#include <linux/bits.h>
 #include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/mdio.h>
-- 
2.51.0

[PATCH net-next v2 4/9] net: pcs: rzn1-miic: Move configuration data to SoC-specific struct

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Move configuration data such as the modctrl matching table, converter
count, and string lookup tables into the SoC-specific miic_of_data
structure. Update the helper functions to use the per-SoC configuration
instead of relying on fixed-size arrays or global tables, and allocate
DT configuration memory dynamically.

This refactoring keeps the existing RZ/N1 support intact while preparing
the driver to handle the different configuration requirements of the
RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 107 ++++++++++++++++++++++----------
 1 file changed, 75 insertions(+), 32 deletions(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index adf4b5e4741c..724bac86cf8c 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -16,6 +16,7 @@
 #include <linux/phylink.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/slab.h>
 #include <dt-bindings/net/pcs-rzn1-miic.h>
 
 #define MIIC_PRCMD			0x0
@@ -50,7 +51,7 @@
 
 #define MIIC_MAX_NR_PORTS		5
 
-#define MIIC_MODCTRL_CONF_CONV_NUM	6
+#define MIIC_MODCTRL_CONF_CONV_MAX	6
 #define MIIC_MODCTRL_CONF_NONE		-1
 
 /**
@@ -58,11 +59,13 @@
  *			  See section 8.2.1 of manual.
  * @mode_cfg: Configuration value for convctrl
  * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
- *	  then index 1 - 5 are CONV1 - CONV5.
+ *	  then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case
+ *	  of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then
+ *	  index 0 - 3 are CONV0 - CONV3.
  */
 struct modctrl_match {
 	u32 mode_cfg;
-	u8 conv[MIIC_MODCTRL_CONF_CONV_NUM];
+	u8 conv[MIIC_MODCTRL_CONF_CONV_MAX];
 };
 
 static struct modctrl_match modctrl_match_table[] = {
@@ -111,7 +114,7 @@ static const char * const conf_to_string[] = {
 	[MIIC_HSR_PORTB]	= "HSR_PORTB",
 };
 
-static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = {
+static const char * const index_to_string[] = {
 	"SWITCH_PORTIN",
 	"CONV1",
 	"CONV2",
@@ -125,11 +128,33 @@ static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = {
  * @base: base address of the MII converter
  * @dev: Device associated to the MII converter
  * @lock: Lock used for read-modify-write access
+ * @of_data: Pointer to OF data
  */
 struct miic {
 	void __iomem *base;
 	struct device *dev;
 	spinlock_t lock;
+	const struct miic_of_data *of_data;
+};
+
+/**
+ * struct miic_of_data - OF data for MII converter
+ * @match_table: Matching table for convctrl configuration
+ * @match_table_count: Number of entries in the matching table
+ * @conf_conv_count: Number of entries in the conf_conv array
+ * @conf_to_string: String representations of the configuration values
+ * @conf_to_string_count: Number of entries in the conf_to_string array
+ * @index_to_string: String representations of the index values
+ * @index_to_string_count: Number of entries in the index_to_string array
+ */
+struct miic_of_data {
+	struct modctrl_match *match_table;
+	u8 match_table_count;
+	u8 conf_conv_count;
+	const char * const *conf_to_string;
+	u8 conf_to_string_count;
+	const char * const *index_to_string;
+	u8 index_to_string_count;
 };
 
 /**
@@ -398,12 +423,11 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode)
 	return 0;
 }
 
-static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],
-			       s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM])
+static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count)
 {
 	int i;
 
-	for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
+	for (i = 0; i < count; i++) {
 		if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
 			continue;
 
@@ -414,53 +438,57 @@ static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],
 	return true;
 }
 
-static void miic_dump_conf(struct device *dev,
-			   s8 conf[MIIC_MODCTRL_CONF_CONV_NUM])
+static void miic_dump_conf(struct miic *miic, s8 *conf)
 {
+	const struct miic_of_data *of_data = miic->of_data;
 	const char *conf_name;
 	int i;
 
-	for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
+	for (i = 0; i < of_data->conf_conv_count; i++) {
 		if (conf[i] != MIIC_MODCTRL_CONF_NONE)
-			conf_name = conf_to_string[conf[i]];
+			conf_name = of_data->conf_to_string[conf[i]];
 		else
 			conf_name = "NONE";
 
-		dev_err(dev, "%s: %s\n", index_to_string[i], conf_name);
+		dev_err(miic->dev, "%s: %s\n", of_data->index_to_string[i], conf_name);
 	}
 }
 
-static int miic_match_dt_conf(struct device *dev,
-			      s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM],
-			      u32 *mode_cfg)
+static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg)
 {
+	const struct miic_of_data *of_data = miic->of_data;
 	struct modctrl_match *table_entry;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) {
-		table_entry = &modctrl_match_table[i];
+	for (i = 0; i < of_data->match_table_count; i++) {
+		table_entry = &of_data->match_table[i];
 
-		if (miic_modctrl_match(table_entry->conv, dt_val)) {
+		if (miic_modctrl_match(table_entry->conv, dt_val,
+				       miic->of_data->conf_conv_count)) {
 			*mode_cfg = table_entry->mode_cfg;
 			return 0;
 		}
 	}
 
-	dev_err(dev, "Failed to apply requested configuration\n");
-	miic_dump_conf(dev, dt_val);
+	dev_err(miic->dev, "Failed to apply requested configuration\n");
+	miic_dump_conf(miic, dt_val);
 
 	return -EINVAL;
 }
 
-static int miic_parse_dt(struct device *dev, u32 *mode_cfg)
+static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
 {
-	s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM];
-	struct device_node *np = dev->of_node;
+	struct device_node *np = miic->dev->of_node;
 	struct device_node *conv;
+	int port, ret;
+	s8 *dt_val;
 	u32 conf;
-	int port;
 
-	memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val));
+	dt_val = kmalloc_array(miic->of_data->conf_conv_count, sizeof(*dt_val), GFP_KERNEL);
+	if (!dt_val)
+		return -ENOMEM;
+
+	memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val));
 
 	if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
 		dt_val[0] = conf;
@@ -473,7 +501,10 @@ static int miic_parse_dt(struct device *dev, u32 *mode_cfg)
 			dt_val[port] = conf;
 	}
 
-	return miic_match_dt_conf(dev, dt_val, mode_cfg);
+	ret = miic_match_dt_conf(miic, dt_val, mode_cfg);
+	kfree(dt_val);
+
+	return ret;
 }
 
 static int miic_probe(struct platform_device *pdev)
@@ -483,16 +514,18 @@ static int miic_probe(struct platform_device *pdev)
 	u32 mode_cfg;
 	int ret;
 
-	ret = miic_parse_dt(dev, &mode_cfg);
-	if (ret < 0)
-		return ret;
-
 	miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
 	if (!miic)
 		return -ENOMEM;
 
-	spin_lock_init(&miic->lock);
+	miic->of_data = of_device_get_match_data(dev);
 	miic->dev = dev;
+
+	ret = miic_parse_dt(miic, &mode_cfg);
+	if (ret < 0)
+		return ret;
+
+	spin_lock_init(&miic->lock);
 	miic->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(miic->base))
 		return PTR_ERR(miic->base);
@@ -529,8 +562,18 @@ static void miic_remove(struct platform_device *pdev)
 	pm_runtime_put(&pdev->dev);
 }
 
+static struct miic_of_data rzn1_miic_of_data = {
+	.match_table = modctrl_match_table,
+	.match_table_count = ARRAY_SIZE(modctrl_match_table),
+	.conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX,
+	.conf_to_string = conf_to_string,
+	.conf_to_string_count = ARRAY_SIZE(conf_to_string),
+	.index_to_string = index_to_string,
+	.index_to_string_count = ARRAY_SIZE(index_to_string),
+};
+
 static const struct of_device_id miic_of_mtable[] = {
-	{ .compatible = "renesas,rzn1-miic" },
+	{ .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, miic_of_mtable);
-- 
2.51.0

[PATCH net-next v2 5/9] net: pcs: rzn1-miic: move port range handling into SoC data

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Define per-SoC miic_port_start and miic_port_max fields in struct
miic_of_data and use them to validate the device-tree "reg" port number
and to compute the driver's internal zero-based port index as
(port - miic_port_start). Replace uses of the hard-coded MIIC_MAX_NR_PORTS
with the SoC-provided miic_port_max when iterating over ports.

On RZ/N1 the MIIC ports are numbered 1..5, whereas RZ/T2H numbers its MIIC
ports 0..3. By making the port base and range part of the OF data the
driver no longer assumes a fixed numbering scheme and can support SoCs that
enumerate ports from either zero or one and that expose different numbers
of ports.

This change is preparatory work for adding RZ/T2H support.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index 724bac86cf8c..c119ec66fe95 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -49,8 +49,6 @@
 #define MIIC_SWCTRL			0x304
 #define MIIC_SWDUPC			0x308
 
-#define MIIC_MAX_NR_PORTS		5
-
 #define MIIC_MODCTRL_CONF_CONV_MAX	6
 #define MIIC_MODCTRL_CONF_NONE		-1
 
@@ -146,6 +144,8 @@ struct miic {
  * @conf_to_string_count: Number of entries in the conf_to_string array
  * @index_to_string: String representations of the index values
  * @index_to_string_count: Number of entries in the index_to_string array
+ * @miic_port_start: MIIC port start number
+ * @miic_port_max: Maximum MIIC supported
  */
 struct miic_of_data {
 	struct modctrl_match *match_table;
@@ -155,6 +155,8 @@ struct miic_of_data {
 	u8 conf_to_string_count;
 	const char * const *index_to_string;
 	u8 index_to_string_count;
+	u8 miic_port_start;
+	u8 miic_port_max;
 };
 
 /**
@@ -330,6 +332,7 @@ static const struct phylink_pcs_ops miic_phylink_ops = {
 
 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
 {
+	const struct miic_of_data *of_data;
 	struct platform_device *pdev;
 	struct miic_port *miic_port;
 	struct device_node *pcs_np;
@@ -342,9 +345,6 @@ struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
 	if (of_property_read_u32(np, "reg", &port))
 		return ERR_PTR(-EINVAL);
 
-	if (port > MIIC_MAX_NR_PORTS || port < 1)
-		return ERR_PTR(-EINVAL);
-
 	/* The PCS pdev is attached to the parent node */
 	pcs_np = of_get_parent(np);
 	if (!pcs_np)
@@ -363,18 +363,24 @@ struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
 		return ERR_PTR(-EPROBE_DEFER);
 	}
 
+	miic = platform_get_drvdata(pdev);
+	of_data = miic->of_data;
+	if (port > of_data->miic_port_max || port < of_data->miic_port_start) {
+		put_device(&pdev->dev);
+		return ERR_PTR(-EINVAL);
+	}
+
 	miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL);
 	if (!miic_port) {
 		put_device(&pdev->dev);
 		return ERR_PTR(-ENOMEM);
 	}
 
-	miic = platform_get_drvdata(pdev);
 	device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
 	put_device(&pdev->dev);
 
 	miic_port->miic = miic;
-	miic_port->port = port - 1;
+	miic_port->port = port - of_data->miic_port_start;
 	miic_port->pcs.ops = &miic_phylink_ops;
 
 	phy_interface_set_rgmii(miic_port->pcs.supported_interfaces);
@@ -410,7 +416,7 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode)
 	miic_reg_writel(miic, MIIC_MODCTRL,
 			FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
 
-	for (port = 0; port < MIIC_MAX_NR_PORTS; port++) {
+	for (port = 0; port < miic->of_data->miic_port_max; port++) {
 		miic_converter_enable(miic, port, 0);
 		/* Disable speed/duplex control from these registers, datasheet
 		 * says switch registers should be used to setup switch port
@@ -497,6 +503,8 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
 		if (of_property_read_u32(conv, "reg", &port))
 			continue;
 
+		/* Adjust for 0 based index */
+		port += !miic->of_data->miic_port_start;
 		if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
 			dt_val[port] = conf;
 	}
@@ -570,6 +578,8 @@ static struct miic_of_data rzn1_miic_of_data = {
 	.conf_to_string_count = ARRAY_SIZE(conf_to_string),
 	.index_to_string = index_to_string,
 	.index_to_string_count = ARRAY_SIZE(index_to_string),
+	.miic_port_start = 1,
+	.miic_port_max = 5,
 };
 
 static const struct of_device_id miic_of_mtable[] = {
-- 
2.51.0

[PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Move the hardcoded switch mode mask definition into the SoC-specific
miic_of_data structure. This allows each SoC to define its own mask
value rather than relying on a single fixed constant. For RZ/N1 the
mask remains GENMASK(4, 0).

This is in preparation for adding support for RZ/T2H, where the
switch mode mask is GENMASK(2, 0).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index c119ec66fe95..c0aa93fd7274 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -7,6 +7,7 @@
 
 #include <linux/array_size.h>
 #include <linux/bits.h>
+#include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/mdio.h>
@@ -23,7 +24,6 @@
 #define MIIC_ESID_CODE			0x4
 
 #define MIIC_MODCTRL			0x8
-#define MIIC_MODCTRL_SW_MODE		GENMASK(4, 0)
 
 #define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
 
@@ -146,6 +146,7 @@ struct miic {
  * @index_to_string_count: Number of entries in the index_to_string array
  * @miic_port_start: MIIC port start number
  * @miic_port_max: Maximum MIIC supported
+ * @sw_mode_mask: Switch mode mask
  */
 struct miic_of_data {
 	struct modctrl_match *match_table;
@@ -157,6 +158,7 @@ struct miic_of_data {
 	u8 index_to_string_count;
 	u8 miic_port_start;
 	u8 miic_port_max;
+	u8 sw_mode_mask;
 };
 
 /**
@@ -402,6 +404,7 @@ EXPORT_SYMBOL(miic_destroy);
 
 static int miic_init_hw(struct miic *miic, u32 cfg_mode)
 {
+	u8 sw_mode_mask = miic->of_data->sw_mode_mask;
 	int port;
 
 	/* Unlock write access to accessory registers (cf datasheet). If this
@@ -414,7 +417,7 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode)
 	miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
 
 	miic_reg_writel(miic, MIIC_MODCTRL,
-			FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
+			((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
 
 	for (port = 0; port < miic->of_data->miic_port_max; port++) {
 		miic_converter_enable(miic, port, 0);
@@ -580,6 +583,7 @@ static struct miic_of_data rzn1_miic_of_data = {
 	.index_to_string_count = ARRAY_SIZE(index_to_string),
 	.miic_port_start = 1,
 	.miic_port_max = 5,
+	.sw_mode_mask = GENMASK(4, 0),
 };
 
 static const struct of_device_id miic_of_mtable[] = {
-- 
2.51.0

[PATCH net-next v2 7/9] net: pcs: rzn1-miic: Add support to handle resets

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add reset-line handling to the RZN1 MIIC driver and move reset
configuration into the SoC/OF data. Introduce MIIC_MAX_NUM_RSTS (= 2),
add storage for reset_control_bulk_data in struct miic and add
reset_ids and reset_count fields to miic_of_data.

When reset_ids are present in the OF data, the driver obtains the reset
lines with devm_reset_control_bulk_get_exclusive(), deasserts them during
probe and registers a devres action to assert them on remove or on error.

This change is preparatory work to support the RZ/T2H SoC, which exposes
two reset lines for the ETHSS IP. The driver remains backward compatible
for platforms that do not provide reset lines.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index c0aa93fd7274..d97554e203f0 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -10,6 +10,7 @@
 #include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/device.h>
+#include <linux/device/devres.h>
 #include <linux/mdio.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
@@ -17,6 +18,7 @@
 #include <linux/phylink.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <dt-bindings/net/pcs-rzn1-miic.h>
 
@@ -52,6 +54,8 @@
 #define MIIC_MODCTRL_CONF_CONV_MAX	6
 #define MIIC_MODCTRL_CONF_NONE		-1
 
+#define MIIC_MAX_NUM_RSTS		2
+
 /**
  * struct modctrl_match - Matching table entry for  convctrl configuration
  *			  See section 8.2.1 of manual.
@@ -126,12 +130,14 @@ static const char * const index_to_string[] = {
  * @base: base address of the MII converter
  * @dev: Device associated to the MII converter
  * @lock: Lock used for read-modify-write access
+ * @rsts: Reset controls for the MII converter
  * @of_data: Pointer to OF data
  */
 struct miic {
 	void __iomem *base;
 	struct device *dev;
 	spinlock_t lock;
+	struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS];
 	const struct miic_of_data *of_data;
 };
 
@@ -147,6 +153,8 @@ struct miic {
  * @miic_port_start: MIIC port start number
  * @miic_port_max: Maximum MIIC supported
  * @sw_mode_mask: Switch mode mask
+ * @reset_ids: Reset names array
+ * @reset_count: Number of entries in the reset_ids array
  */
 struct miic_of_data {
 	struct modctrl_match *match_table;
@@ -159,6 +167,8 @@ struct miic_of_data {
 	u8 miic_port_start;
 	u8 miic_port_max;
 	u8 sw_mode_mask;
+	const char * const *reset_ids;
+	u8 reset_count;
 };
 
 /**
@@ -518,6 +528,16 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
 	return ret;
 }
 
+static void miic_reset_control_bulk_assert(void *data)
+{
+	struct miic *miic = data;
+	int ret;
+
+	ret = reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts);
+	if (ret)
+		dev_err(miic->dev, "failed to assert reset lines\n");
+}
+
 static int miic_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -541,6 +561,27 @@ static int miic_probe(struct platform_device *pdev)
 	if (IS_ERR(miic->base))
 		return PTR_ERR(miic->base);
 
+	if (miic->of_data->reset_count) {
+		u8 i;
+
+		for (i = 0; i < miic->of_data->reset_count; i++)
+			miic->rsts[i].id = miic->of_data->reset_ids[i];
+
+		ret = devm_reset_control_bulk_get_exclusive(miic->dev,
+							    miic->of_data->reset_count,
+							    miic->rsts);
+		if (ret)
+			return dev_err_probe(miic->dev, ret, "failed to get bulk reset lines\n");
+
+		ret = reset_control_bulk_deassert(miic->of_data->reset_count, miic->rsts);
+		if (ret)
+			return dev_err_probe(miic->dev, ret, "failed to deassert reset lines\n");
+
+		ret = devm_add_action_or_reset(dev, miic_reset_control_bulk_assert, miic);
+		if (ret)
+			return dev_err_probe(miic->dev, ret, "failed to add reset action\n");
+	}
+
 	ret = devm_pm_runtime_enable(dev);
 	if (ret < 0)
 		return ret;
-- 
2.51.0

[PATCH net-next v2 8/9] net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF
data. Add init_unlock_lock_regs and miic_write to struct miic_of_data so
the driver can either perform the traditional global unlock sequence (as
used on RZ/N1) or use a different policy for other SoCs (for example
RZ/T2H, which does not require leaving registers unlocked).

miic_reg_writel() now calls the per-SoC miic_write callback to perform
register writes. Provide miic_reg_writel_unlocked() as the default writer
and set it for the RZ/N1 OF data so existing platforms keep the same
behaviour. Add a miic_unlock_regs() helper that implements the accessory
register unlock sequence so the unlock/lock sequence can be reused where
needed (for example when a SoC requires explicit unlock/lock around
individual accesses).

This change is preparatory work for supporting RZ/T2H.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
 drivers/net/pcs/pcs-rzn1-miic.c | 28 +++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index d97554e203f0..86d4dccd694e 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -155,6 +155,8 @@ struct miic {
  * @sw_mode_mask: Switch mode mask
  * @reset_ids: Reset names array
  * @reset_count: Number of entries in the reset_ids array
+ * @init_unlock_lock_regs: Flag to indicate if registers need to be unlocked before access
+ * @miic_write: Function pointer to write a value to a MIIC register
  */
 struct miic_of_data {
 	struct modctrl_match *match_table;
@@ -169,6 +171,8 @@ struct miic_of_data {
 	u8 sw_mode_mask;
 	const char * const *reset_ids;
 	u8 reset_count;
+	bool init_unlock_lock_regs;
+	void (*miic_write)(struct miic *miic, int offset, u32 value);
 };
 
 /**
@@ -190,11 +194,25 @@ static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
 	return container_of(pcs, struct miic_port, pcs);
 }
 
-static void miic_reg_writel(struct miic *miic, int offset, u32 value)
+static inline void miic_unlock_regs(struct miic *miic)
+{
+	/* Unprotect register writes */
+	writel(0x00A5, miic->base + MIIC_PRCMD);
+	writel(0x0001, miic->base + MIIC_PRCMD);
+	writel(0xFFFE, miic->base + MIIC_PRCMD);
+	writel(0x0001, miic->base + MIIC_PRCMD);
+}
+
+static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value)
 {
 	writel(value, miic->base + offset);
 }
 
+static void miic_reg_writel(struct miic *miic, int offset, u32 value)
+{
+	miic->of_data->miic_write(miic, offset, value);
+}
+
 static u32 miic_reg_readl(struct miic *miic, int offset)
 {
 	return readl(miic->base + offset);
@@ -421,10 +439,8 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode)
 	 * is going to be used in conjunction with the Cortex-M3, this sequence
 	 * will have to be moved in register write
 	 */
-	miic_reg_writel(miic, MIIC_PRCMD, 0x00A5);
-	miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
-	miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE);
-	miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
+	if (miic->of_data->init_unlock_lock_regs)
+		miic_unlock_regs(miic);
 
 	miic_reg_writel(miic, MIIC_MODCTRL,
 			((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
@@ -625,6 +641,8 @@ static struct miic_of_data rzn1_miic_of_data = {
 	.miic_port_start = 1,
 	.miic_port_max = 5,
 	.sw_mode_mask = GENMASK(4, 0),
+	.init_unlock_lock_regs = true,
+	.miic_write = miic_reg_writel_unlocked,
 };
 
 static const struct of_device_id miic_of_mtable[] = {
-- 
2.51.0

[PATCH net-next v2 9/9] net: pcs: rzn1-miic: Add RZ/T2H MIIC support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support for the Renesas RZ/T2H MIIC by defining SoC-specific
modctrl match tables, register map, and string representations
for converters and ports.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- Dropped regx in config description.
- Used "renesas,r9a09g077-miic" as compatible for RZ/T2H.
---
 drivers/net/pcs/Kconfig         | 11 +++--
 drivers/net/pcs/pcs-rzn1-miic.c | 82 +++++++++++++++++++++++++++++++++
 2 files changed, 88 insertions(+), 5 deletions(-)

diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index f6aa437473de..76dbc11d9575 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -26,11 +26,12 @@ config PCS_MTK_LYNXI
 	  which is part of MediaTek's SoC and Ethernet switch ICs.
 
 config PCS_RZN1_MIIC
-	tristate "Renesas RZ/N1 MII converter"
-	depends on OF && (ARCH_RZN1 || COMPILE_TEST)
+	tristate "Renesas RZ/N1, RZ/N2H, RZ/T2H MII converter"
+	depends on OF
+	depends on ARCH_RZN1 || ARCH_R9A09G077 || ARCH_R9A09G087 || COMPILE_TEST
 	help
-	  This module provides a driver for the MII converter that is available
-	  on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
-	  pass-through mode for MII.
+	  This module provides a driver for the MII converter available on
+	  Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to
+	  RMII/RGMII, or can be set in pass-through mode for MII.
 
 endmenu
diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index 86d4dccd694e..5ec36bf042cd 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -21,6 +21,7 @@
 #include <linux/reset.h>
 #include <linux/slab.h>
 #include <dt-bindings/net/pcs-rzn1-miic.h>
+#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
 
 #define MIIC_PRCMD			0x0
 #define MIIC_ESID_CODE			0x4
@@ -125,6 +126,57 @@ static const char * const index_to_string[] = {
 	"CONV5",
 };
 
+static struct modctrl_match rzt2h_modctrl_match_table[] = {
+	{0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
+	       ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
+
+	{0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
+	       ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
+
+	{0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
+		ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
+
+	{0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
+	       ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
+
+	{0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
+	       ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
+
+	{0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
+	       ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
+
+	{0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
+	       ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
+
+	{0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT,
+		ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}}
+};
+
+static const char * const rzt2h_conf_to_string[] = {
+	[ETHSS_GMAC0_PORT]	= "GMAC0_PORT",
+	[ETHSS_GMAC1_PORT]	= "GMAC1_PORT",
+	[ETHSS_GMAC2_PORT]	= "GMAC2_PORT",
+	[ETHSS_ESC_PORT0]	= "ETHERCAT_PORT0",
+	[ETHSS_ESC_PORT1]	= "ETHERCAT_PORT1",
+	[ETHSS_ESC_PORT2]	= "ETHERCAT_PORT2",
+	[ETHSS_ETHSW_PORT0]	= "SWITCH_PORT0",
+	[ETHSS_ETHSW_PORT1]	= "SWITCH_PORT1",
+	[ETHSS_ETHSW_PORT2]	= "SWITCH_PORT2",
+};
+
+static const char * const rzt2h_index_to_string[] = {
+	"SWITCH_PORTIN",
+	"CONV0",
+	"CONV1",
+	"CONV2",
+	"CONV3",
+};
+
+static const char * const rzt2h_reset_ids[] = {
+	"rst",
+	"crst",
+};
+
 /**
  * struct miic - MII converter structure
  * @base: base address of the MII converter
@@ -203,11 +255,24 @@ static inline void miic_unlock_regs(struct miic *miic)
 	writel(0x0001, miic->base + MIIC_PRCMD);
 }
 
+static inline void miic_lock_regs(struct miic *miic)
+{
+	/* Protect register writes */
+	writel(0x0000, miic->base + MIIC_PRCMD);
+}
+
 static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value)
 {
 	writel(value, miic->base + offset);
 }
 
+static void miic_reg_writel_locked(struct miic *miic, int offset, u32 value)
+{
+	miic_unlock_regs(miic);
+	writel(value, miic->base + offset);
+	miic_lock_regs(miic);
+}
+
 static void miic_reg_writel(struct miic *miic, int offset, u32 value)
 {
 	miic->of_data->miic_write(miic, offset, value);
@@ -645,7 +710,24 @@ static struct miic_of_data rzn1_miic_of_data = {
 	.miic_write = miic_reg_writel_unlocked,
 };
 
+static struct miic_of_data rzt2h_miic_of_data = {
+	.match_table = rzt2h_modctrl_match_table,
+	.match_table_count = ARRAY_SIZE(rzt2h_modctrl_match_table),
+	.conf_conv_count = 5,
+	.conf_to_string = rzt2h_conf_to_string,
+	.conf_to_string_count = ARRAY_SIZE(rzt2h_conf_to_string),
+	.index_to_string = rzt2h_index_to_string,
+	.index_to_string_count = ARRAY_SIZE(rzt2h_index_to_string),
+	.miic_port_start = 0,
+	.miic_port_max = 4,
+	.sw_mode_mask = GENMASK(2, 0),
+	.reset_ids = rzt2h_reset_ids,
+	.reset_count = ARRAY_SIZE(rzt2h_reset_ids),
+	.miic_write = miic_reg_writel_locked,
+};
+
 static const struct of_device_id miic_of_mtable[] = {
+	{ .compatible = "renesas,r9a09g077-miic", .data = &rzt2h_miic_of_data },
 	{ .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data },
 	{ /* sentinel */ }
 };
-- 
2.51.0

Re: [PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[Simon Horman]

On Thu, Sep 04, 2025 at 12:41:54PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This series aims to add PCS support for the Renesas RZ/T2H and RZ/N2H SoCs
> These SoCs include a MII converter (MIIC) that converts MII to RMII/RGMII
> or can be set in pass-through mode for MII similar to the RZ/N1 SoC. The
> MIIC is used in conjunction with the Ethernet switch (ETHSW) available on
> these SoCs.

Hi Lad,

This patch-set depends with the following commit, which is present in
net but not yet in net-next.

commit a7195a3d67da ("net: pcs: rzn1-miic: Correct MODCTRL register offset")

Please repost (and if necessary, rebase) once it is present in net-next so
that the CI runs.

And please ensure that 24h elapses between postings to allow for review.

Thanks!

-- 
pw-bot: changes-requested

Re: [PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[Lad, Prabhakar]

Hi Simon,

On Thu, Sep 4, 2025 at 1:41 PM Simon Horman <horms@kernel.org> wrote:
>
> On Thu, Sep 04, 2025 at 12:41:54PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Hi All,
> >
> > This series aims to add PCS support for the Renesas RZ/T2H and RZ/N2H SoCs
> > These SoCs include a MII converter (MIIC) that converts MII to RMII/RGMII
> > or can be set in pass-through mode for MII similar to the RZ/N1 SoC. The
> > MIIC is used in conjunction with the Ethernet switch (ETHSW) available on
> > these SoCs.
>
> Hi Lad,
>
> This patch-set depends with the following commit, which is present in
> net but not yet in net-next.
>
> commit a7195a3d67da ("net: pcs: rzn1-miic: Correct MODCTRL register offset")
>
Sorry, I missed to mention the dependency for net-next.

> Please repost (and if necessary, rebase) once it is present in net-next so
> that the CI runs.
>
Ok, I'll repost once the patch lands in net-next.

> And please ensure that 24h elapses between postings to allow for review.
>
Sure, I'll make a note of it.

Cheers,
Prabhakar

Re: [PATCH net-next v2 2/9] net: pcs: rzn1-miic: Drop trailing comma from of_device_id table

[Andrew Lunn]

On Thu, Sep 04, 2025 at 12:41:56PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Remove the trailing comma after the sentinel entry in the
> of_device_id match table.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v2 3/9] net: pcs: rzn1-miic: Add missing include files

[Andrew Lunn]

On Thu, Sep 04, 2025 at 12:41:57PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The pcs-rzn1-miic driver makes use of ARRAY_SIZE(), BIT() and GENMASK()
> macros but does not explicitly include the headers where they are
> defined. Add the missing <linux/array_size.h> and <linux/bits.h>
> includes.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v2 5/9] net: pcs: rzn1-miic: move port range handling into SoC data

[Andrew Lunn]

On Thu, Sep 04, 2025 at 12:41:59PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Define per-SoC miic_port_start and miic_port_max fields in struct
> miic_of_data and use them to validate the device-tree "reg" port number
> and to compute the driver's internal zero-based port index as
> (port - miic_port_start). Replace uses of the hard-coded MIIC_MAX_NR_PORTS
> with the SoC-provided miic_port_max when iterating over ports.
> 
> On RZ/N1 the MIIC ports are numbered 1..5, whereas RZ/T2H numbers its MIIC
> ports 0..3. By making the port base and range part of the OF data the
> driver no longer assumes a fixed numbering scheme and can support SoCs that
> enumerate ports from either zero or one and that expose different numbers
> of ports.
> 
> This change is preparatory work for adding RZ/T2H support.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

[Andrew Lunn]

On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Move the hardcoded switch mode mask definition into the SoC-specific
> miic_of_data structure. This allows each SoC to define its own mask
> value rather than relying on a single fixed constant. For RZ/N1 the
> mask remains GENMASK(4, 0).
> 
> This is in preparation for adding support for RZ/T2H, where the
> switch mode mask is GENMASK(2, 0).

> -#define MIIC_MODCTRL_SW_MODE		GENMASK(4, 0)

>  	miic_reg_writel(miic, MIIC_MODCTRL,
> -			FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> +			((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));

_ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
this __ffs() is pointless.

You might however want to add a comment that this assumption is being
made.

    Andrew

---
pw-bot: cr

Re: [PATCH net-next v2 7/9] net: pcs: rzn1-miic: Add support to handle resets

[Andrew Lunn]

On Thu, Sep 04, 2025 at 12:42:01PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add reset-line handling to the RZN1 MIIC driver and move reset
> configuration into the SoC/OF data. Introduce MIIC_MAX_NUM_RSTS (= 2),
> add storage for reset_control_bulk_data in struct miic and add
> reset_ids and reset_count fields to miic_of_data.
> 
> When reset_ids are present in the OF data, the driver obtains the reset
> lines with devm_reset_control_bulk_get_exclusive(), deasserts them during
> probe and registers a devres action to assert them on remove or on error.
> 
> This change is preparatory work to support the RZ/T2H SoC, which exposes
> two reset lines for the ETHSS IP. The driver remains backward compatible
> for platforms that do not provide reset lines.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v2 8/9] net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock

[Andrew Lunn]

> -static void miic_reg_writel(struct miic *miic, int offset, u32 value)
> +static inline void miic_unlock_regs(struct miic *miic)
> +{

Please don't use inline in C files. The compiler should decide.

       Andrew

Re: [PATCH net-next v2 9/9] net: pcs: rzn1-miic: Add RZ/T2H MIIC support

[Andrew Lunn]

>  /**
>   * struct miic - MII converter structure
>   * @base: base address of the MII converter
> @@ -203,11 +255,24 @@ static inline void miic_unlock_regs(struct miic *miic)
>  	writel(0x0001, miic->base + MIIC_PRCMD);
>  }
>  
> +static inline void miic_lock_regs(struct miic *miic)

Here as well.

	Andrew

Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

[Geert Uytterhoeven]

Hi Andrew,

On Thu, 4 Sept 2025 at 22:37, Andrew Lunn <andrew@lunn.ch> wrote:
> On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Move the hardcoded switch mode mask definition into the SoC-specific
> > miic_of_data structure. This allows each SoC to define its own mask
> > value rather than relying on a single fixed constant. For RZ/N1 the
> > mask remains GENMASK(4, 0).
> >
> > This is in preparation for adding support for RZ/T2H, where the
> > switch mode mask is GENMASK(2, 0).
>
> > -#define MIIC_MODCTRL_SW_MODE         GENMASK(4, 0)
>
> >       miic_reg_writel(miic, MIIC_MODCTRL,
> > -                     FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > +                     ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
>
> _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> this __ffs() is pointless.
>
> You might however want to add a comment that this assumption is being
> made.

I guess Prabhakar did it this way to make it easier to find
candidates for a future conversion to field_prep(), if this ever becomes
available[1].

[1] "[PATCH v3 0/4] Non-const bitfield helpers"
    https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

[Lad, Prabhakar]

Hi Geert,

On Fri, Sep 5, 2025 at 8:02 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Andrew,
>
> On Thu, 4 Sept 2025 at 22:37, Andrew Lunn <andrew@lunn.ch> wrote:
> > On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Move the hardcoded switch mode mask definition into the SoC-specific
> > > miic_of_data structure. This allows each SoC to define its own mask
> > > value rather than relying on a single fixed constant. For RZ/N1 the
> > > mask remains GENMASK(4, 0).
> > >
> > > This is in preparation for adding support for RZ/T2H, where the
> > > switch mode mask is GENMASK(2, 0).
> >
> > > -#define MIIC_MODCTRL_SW_MODE         GENMASK(4, 0)
> >
> > >       miic_reg_writel(miic, MIIC_MODCTRL,
> > > -                     FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > > +                     ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
> >
> > _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> > this __ffs() is pointless.
> >
> > You might however want to add a comment that this assumption is being
> > made.
>
> I guess Prabhakar did it this way to make it easier to find
> candidates for a future conversion to field_prep(), if this ever becomes
> available[1].
>
> [1] "[PATCH v3 0/4] Non-const bitfield helpers"
>     https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be
>
Ah thanks, I wanted to explore this and add a new macro but I thought
it might delay this series so I dropped it. Hopefully your series will
get in soon.

Cheers,
Prabhakar

Re: [PATCH net-next v2 8/9] net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock

[Lad, Prabhakar]

Hi Andrew,

Thank you for the review.

On Thu, Sep 4, 2025 at 9:55 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > -static void miic_reg_writel(struct miic *miic, int offset, u32 value)
> > +static inline void miic_unlock_regs(struct miic *miic)
> > +{
>
> Please don't use inline in C files. The compiler should decide.
>
Ok, I will drop this in the next version.

Cheers,
Prabhakar

Re: [PATCH net-next v2 9/9] net: pcs: rzn1-miic: Add RZ/T2H MIIC support

[Lad, Prabhakar]

Hi Andrew,

Thank you for the review.

On Thu, Sep 4, 2025 at 9:57 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> >  /**
> >   * struct miic - MII converter structure
> >   * @base: base address of the MII converter
> > @@ -203,11 +255,24 @@ static inline void miic_unlock_regs(struct miic *miic)
> >       writel(0x0001, miic->base + MIIC_PRCMD);
> >  }
> >
> > +static inline void miic_lock_regs(struct miic *miic)
>
> Here as well.
>
Ok, I will drop it in the next version.

Cheers,
Prabhakar

Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

[Lad, Prabhakar]

Hi Andrew and Geert,

Thank you for the review.

On Thu, Sep 4, 2025 at 9:37 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Move the hardcoded switch mode mask definition into the SoC-specific
> > miic_of_data structure. This allows each SoC to define its own mask
> > value rather than relying on a single fixed constant. For RZ/N1 the
> > mask remains GENMASK(4, 0).
> >
> > This is in preparation for adding support for RZ/T2H, where the
> > switch mode mask is GENMASK(2, 0).
>
> > -#define MIIC_MODCTRL_SW_MODE         GENMASK(4, 0)
>
> >       miic_reg_writel(miic, MIIC_MODCTRL,
> > -                     FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > +                     ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
>
> _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> this __ffs() is pointless.
>
Agreed.

> You might however want to add a comment that this assumption is being
> made.
>
I will add the below comment for this, so that once Geert's series [0]
hits in it can be easily searched and replaced.

/*
* TODO: Replace with FIELD_PREP() when compile-time
* constant restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask.
*/

[0] https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be

Cheers,
Prabhakar

Re: [PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 966 bytes --]


> This series aims to add PCS support for the Renesas RZ/T2H and RZ/N2H SoCs
> These SoCs include a MII converter (MIIC) that converts MII to RMII/RGMII
> or can be set in pass-through mode for MII similar to the RZ/N1 SoC. The
> MIIC is used in conjunction with the Ethernet switch (ETHSW) available on
> these SoCs.
> 
> v1->v2:
> - Dropped regx in title and description in patch 1/9.
> - As done for other IPs used T2H compatible as a fallback for N2H.
> - Renamed pcs-rzt2h-miic.h -> renesas,r9a09g077-pcs-miic.h
> - Added matrix table in the new header file.
> - Corrected the resets check for RZ/N1.
> - Updated the commit message in patch 1/9.
> - Dropped regx in config description in patch 9/9.
> - Dropped patch "net: pcs: rzn1-miic: Add PCS validate callback
>   for RZ/T2H MIIC" is this already taken care in commit 508df2de7b3e
>   as pointed by Russell King.

I plan to test this series on RZ/N1D next week, hopefully on Monday.


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Re: [PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1226 bytes --]

On Sat, Sep 06, 2025 at 02:19:37PM +0200, Wolfram Sang wrote:
> 
> > This series aims to add PCS support for the Renesas RZ/T2H and RZ/N2H SoCs
> > These SoCs include a MII converter (MIIC) that converts MII to RMII/RGMII
> > or can be set in pass-through mode for MII similar to the RZ/N1 SoC. The
> > MIIC is used in conjunction with the Ethernet switch (ETHSW) available on
> > these SoCs.
> > 
> > v1->v2:
> > - Dropped regx in title and description in patch 1/9.
> > - As done for other IPs used T2H compatible as a fallback for N2H.
> > - Renamed pcs-rzt2h-miic.h -> renesas,r9a09g077-pcs-miic.h
> > - Added matrix table in the new header file.
> > - Corrected the resets check for RZ/N1.
> > - Updated the commit message in patch 1/9.
> > - Dropped regx in config description in patch 9/9.
> > - Dropped patch "net: pcs: rzn1-miic: Add PCS validate callback
> >   for RZ/T2H MIIC" is this already taken care in commit 508df2de7b3e
> >   as pointed by Russell King.
> 
> I plan to test this series on RZ/N1D next week, hopefully on Monday.

No regressions found when using the 5 ethernet ports on the RZ/N1D
board. For this series:

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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Re: [PATCH net-next v2 0/9] Add PCS support for Renesas RZ/{T2H,N2H} SoCs

[Lad, Prabhakar]

Hi Wolfram,

On Wed, Sep 10, 2025 at 11:18 AM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> On Sat, Sep 06, 2025 at 02:19:37PM +0200, Wolfram Sang wrote:
> >
> > > This series aims to add PCS support for the Renesas RZ/T2H and RZ/N2H SoCs
> > > These SoCs include a MII converter (MIIC) that converts MII to RMII/RGMII
> > > or can be set in pass-through mode for MII similar to the RZ/N1 SoC. The
> > > MIIC is used in conjunction with the Ethernet switch (ETHSW) available on
> > > these SoCs.
> > >
> > > v1->v2:
> > > - Dropped regx in title and description in patch 1/9.
> > > - As done for other IPs used T2H compatible as a fallback for N2H.
> > > - Renamed pcs-rzt2h-miic.h -> renesas,r9a09g077-pcs-miic.h
> > > - Added matrix table in the new header file.
> > > - Corrected the resets check for RZ/N1.
> > > - Updated the commit message in patch 1/9.
> > > - Dropped regx in config description in patch 9/9.
> > > - Dropped patch "net: pcs: rzn1-miic: Add PCS validate callback
> > >   for RZ/T2H MIIC" is this already taken care in commit 508df2de7b3e
> > >   as pointed by Russell King.
> >
> > I plan to test this series on RZ/N1D next week, hopefully on Monday.
>
> No regressions found when using the 5 ethernet ports on the RZ/N1D
> board. For this series:
>
Thank you for testing this on RZ/N1, I'll send a v3 with some minor
comments fixed.

> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>

Cheers,
Prabhakar