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Fri, 03 Jul 2020 04:24:27 -0700 (PDT) Subject: Re: [PATCH v3 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 To: Robin Murphy , will@kernel.org, joro@8bytes.org, gregory.clement@bootlin.com, robh+dt@kernel.org, hannah@marvell.com Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, catalin.marinas@arm.com, nadavh@marvell.com, linux-arm-kernel@lists.infradead.org, mw@semihalf.com References: <20200702201633.22693-1-tn@semihalf.com> <20200702201633.22693-3-tn@semihalf.com> From: Tomasz Nowicki Message-ID: <8fb0f73f-35ca-d8ec-43b8-ae89e9a21d0c@semihalf.com> Date: Fri, 3 Jul 2020 13:24:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 03.07.2020 11:03, Robin Murphy wrote: > On 2020-07-02 21:16, Tomasz Nowicki wrote: >> From: Hanna Hawa >> >> Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to >> ARM SMMUv2 registers. >> >> Provide implementation relevant hooks: >> - split the writeq/readq to two accesses of writel/readl. >> - mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format (but >> only AARCH32_L) since with AArch64 format 32 bits access is not >> supported. >> >> Note that separate writes/reads to 2 is not problem regards to >> atomicity, because the driver use the readq/writeq while initialize >> the SMMU, report for SMMU fault, and use spinlock in one >> case (iova_to_phys). > > The comment about the spinlock seems to be out of date, and TBH that > whole sentence is a bit unclear - how about something like: > > "Note that most 64-bit registers like TTBRn can be accessed as two > 32-bit halves without issue, and AArch32 format ensures that the > register writes which must be atomic (for TLBI etc.) need only be 32-bit." > >> Signed-off-by: Hanna Hawa >> Signed-off-by: Gregory CLEMENT >> Signed-off-by: Tomasz Nowicki >> --- >>   Documentation/arm64/silicon-errata.rst |  3 ++ >>   drivers/iommu/arm-smmu-impl.c          | 52 ++++++++++++++++++++++++++ >>   2 files changed, 55 insertions(+) >> >> diff --git a/Documentation/arm64/silicon-errata.rst >> b/Documentation/arm64/silicon-errata.rst >> index 936cf2a59ca4..157214d3abe1 100644 >> --- a/Documentation/arm64/silicon-errata.rst >> +++ b/Documentation/arm64/silicon-errata.rst >> @@ -125,6 +125,9 @@ stable kernels. >>   | Cavium         | ThunderX2 Core  | #219            | >> CAVIUM_TX2_ERRATUM_219      | >> >> +----------------+-----------------+-----------------+-----------------------------+ >> >> >> +----------------+-----------------+-----------------+-----------------------------+ >> >> +| Marvell        | ARM-MMU-500     | #582743         | >> N/A                         | >> ++----------------+-----------------+-----------------+-----------------------------+ >> >> ++----------------+-----------------+-----------------+-----------------------------+ >> >>   | Freescale/NXP  | LS2080A/LS1043A | A-008585        | >> FSL_ERRATUM_A008585         | >> >> +----------------+-----------------+-----------------+-----------------------------+ >> >> >> +----------------+-----------------+-----------------+-----------------------------+ >> >> diff --git a/drivers/iommu/arm-smmu-impl.c >> b/drivers/iommu/arm-smmu-impl.c >> index c75b9d957b70..c1fc5e1b8193 100644 >> --- a/drivers/iommu/arm-smmu-impl.c >> +++ b/drivers/iommu/arm-smmu-impl.c >> @@ -147,6 +147,53 @@ static const struct arm_smmu_impl arm_mmu500_impl >> = { >>       .reset = arm_mmu500_reset, >>   }; >> +static u64 mrvl_mmu500_readq(struct arm_smmu_device *smmu, int page, >> int off) >> +{ >> +    u64 val; >> + >> +    /* >> +     * Marvell Armada-AP806 erratum #582743. >> +     * Split all the readq to double readl >> +     */ >> +    val = (u64)readl_relaxed(arm_smmu_page(smmu, page) + off + 4) << 32; >> +    val |= readl_relaxed(arm_smmu_page(smmu, page) + off); > > Even though io-64-nonatomic-hi-lo.h doesn't override readq() etc. for > 64-bit builds, you can still use hi_lo_readq_relaxed() directly. > >> + >> +    return val; >> +} >> + >> +static void mrvl_mmu500_writeq(struct arm_smmu_device *smmu, int >> page, int off, >> +                   u64 val) >> +{ >> +    /* >> +     * Marvell Armada-AP806 erratum #582743. >> +     * Split all the writeq to double writel >> +     */ >> +    writel_relaxed(upper_32_bits(val), arm_smmu_page(smmu, page) + >> off + 4); >> +    writel_relaxed(lower_32_bits(val), arm_smmu_page(smmu, page) + off); > > Similarly, hi_lo_writeq_relaxed(). > >> +} >> + >> +static u32 mrvl_mmu500_cfg_id2_fixup(u32 id) >> +{ >> + >> +    /* >> +     * Armada-AP806 erratum #582743. >> +     * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64 >> +     * formats altogether and allow using 32 bits access on the >> +     * interconnect. >> +     */ >> +    id &= ~(ARM_SMMU_ID2_PTFS_4K | ARM_SMMU_ID2_PTFS_16K | >> +        ARM_SMMU_ID2_PTFS_64K); >> + >> +    return id; >> +} >> + >> +static const struct arm_smmu_impl mrvl_mmu500_impl = { >> +    .read_reg64 = mrvl_mmu500_readq, >> +    .write_reg64 = mrvl_mmu500_writeq, >> +    .cfg_id2_fixup = mrvl_mmu500_cfg_id2_fixup, >> +    .reset = arm_mmu500_reset, >> +}; >> + >>   struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device >> *smmu) >>   { >> @@ -160,6 +207,11 @@ struct arm_smmu_device *arm_smmu_impl_init(struct >> arm_smmu_device *smmu) >>        */ >>       switch (smmu->model) { >>       case ARM_MMU500: >> +        if (of_device_is_compatible(smmu->dev->of_node, > > Nit: there's a local "np" variable now. > >> +                        "marvell,ap806-smmu-500")) { >> +            smmu->impl = &mrvl_mmu500_impl; >> +            return smmu; >> +        } > > Please put this with the other integration checks below the switch > statement. Yes, it means we'll end up assigning smmu->impl twice for > this particular case, but that's the intended pattern. > Thanks, all above comments do make sense and will be fixed in next spin. Thanks, Tomasz