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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id h4-20020a05651c124400b0026be1de1500sm135360ljh.79.2022.09.30.04.19.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Sep 2022 04:19:51 -0700 (PDT) Message-ID: <8fb538bc-534b-0e7e-280d-754afa8e3cd9@linaro.org> Date: Fri, 30 Sep 2022 13:19:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 1/2] dt-bindings: clk: Add binding for versal clocking wizard Content-Language: en-US To: Shubhrajyoti Datta , linux-clk@vger.kernel.org Cc: git@amd.com, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com References: <20220930080400.15619-1-shubhrajyoti.datta@amd.com> <20220930080400.15619-2-shubhrajyoti.datta@amd.com> From: Krzysztof Kozlowski In-Reply-To: <20220930080400.15619-2-shubhrajyoti.datta@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 30/09/2022 10:03, Shubhrajyoti Datta wrote: > The Clocking Wizard for Versal adaptive compute acceleration platforms > generates multiple configurable number of clock outputs. > Add device tree binding for Versal clocking wizard support. Drop second "binding" from subject. Redundant. > > Signed-off-by: Shubhrajyoti Datta > --- > > .../bindings/clock/xlnx,clk-wizard.yaml | 66 +++++++++++++++++++ > 1 file changed, 66 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml > new file mode 100644 > index 000000000000..41a6f4bcaccd > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/xlnx,clk-wizard.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Versal clocking wizard > + > +maintainers: > + - Shubhrajyoti Datta > + > +description: > + The clocking wizard is a soft ip clocking block of Xilinx versal. The IP Isn't versal a proper noun? Some product? If so, it starts with a capital letter. > + uses the input clock frequencies and generates the requested > + clock output. > + > +properties: > + compatible: > + const: xlnx,clk-wizard-1.0 > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + clocks: > + description: List of clock specifiers which are external input > + clocks to the given clock controller. Drop "List of clock specifiers which are " > + items: > + - description: functional clock input > + - description: axi clock or the interface clock > + > + clock-names: > + items: > + - const: clk_in1 Just "in1" > + - const: s_axi_aclk Just "s_axi" > + > + xlnx,nr-outputs: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 1 > + maximum: 8 > + description: > + Number of outputs. Nope, you just copied the name of property. That's like documenting a function with the name of that function. Not useful at all. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - clocks > + - clock-names > + - xlnx,nr-outputs > + > +... Best regards, Krzysztof