Re: [PATCH v1 5/5] riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 02/08/2023 10:43, Xingyu Wu wrote:
> Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the
> StarFive JH7110 SoC.
> 
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---

...

> +
>  	spi0_pins: spi0-0 {
>  		mosi-pins {
>  			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 05f843b8ca03..507312eb6053 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -512,6 +512,30 @@ tdm: tdm@10090000 {
>  			status = "disabled";
>  		};
>  
> +		i2srx: i2srx@100e0000 {

Node names should be generic, so:
i2s@

> +			compatible = "starfive,jh7110-i2srx";
> +			reg = <0x0 0x100e0000 0x0 0x1000>;
> +			clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
> +				 <&syscrg JH7110_SYSCLK_I2SRX_APB>,
> +				 <&syscrg JH7110_SYSCLK_MCLK>,
> +				 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
> +				 <&mclk_ext>,
> +				 <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
> +				 <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
> +				 <&i2srx_bclk_ext>,
> +				 <&i2srx_lrck_ext>;
> +			clock-names = "i2sclk", "apb", "mclk",
> +				      "mclk_inner", "mclk_ext", "bclk",
> +				      "lrck", "bclk_ext", "lrck_ext";
> +			resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
> +				 <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
> +			dmas = <0>, <&dma 24>;
> +			dma-names = "tx", "rx";
> +			starfive,syscon = <&sys_syscon 0x18 0x2>;
> +			#sound-dai-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		usb0: usb@10100000 {
>  			compatible = "starfive,jh7110-usb";
>  			ranges = <0x0 0x0 0x10100000 0x100000>;
> @@ -736,6 +760,47 @@ spi6: spi@120a0000 {
>  			status = "disabled";
>  		};
>  
> +		i2stx0: i2stx0@120b0000 {

i2s@

> +			compatible = "starfive,jh7110-i2stx0";
> +			reg = <0x0 0x120b0000 0x0 0x1000>;
> +			clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
> +				 <&syscrg JH7110_SYSCLK_I2STX0_APB>,
> +				 <&syscrg JH7110_SYSCLK_MCLK>,
> +				 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
> +				 <&mclk_ext>;
> +			clock-names = "i2sclk", "apb", "mclk",
> +				      "mclk_inner","mclk_ext";
> +			resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
> +				 <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
> +			dmas = <&dma 47>;
> +			dma-names = "tx";
> +			#sound-dai-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2stx1: i2stx1@120c0000 {

i2s@



Best regards,
Krzysztof