From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED4311F8EEC; Wed, 8 Jan 2025 11:48:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736336883; cv=none; b=H6ix7kBfbAQEQ5T9YLMXDh0JXmec4GThoR3dhTWgkdKGkzsFjxCQ127LLtFqX+UGfpvqocbKrcQwyOrehtK6R4wNeve1i78T0CR5cPk0lJC7tyCduE4n13dRdIuizxc0fR7yBjATqIYRqc7GS/rf9kabXq6m5fWCIgcl5AbMIA8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736336883; c=relaxed/simple; bh=Km7GShoT8pXc+hDHCfYuInJ3NIvt6jXsbtyKkCJ3IeA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=QljvoAmTnr/+S6J3gPY7QUOeoBlrtwoG11TYYQsVrOer1IiM/x3tZkrsHvuqamnh7UAJPyP0CheRgJNACdnMRZLGyiZC0xtiBBSe1GayruA5Y+eaInOBv5Qq0eDiFEQMe3Etc0hWKBNG4cB1O5w541kvrl2GFU6dfqGjQXyO/Ys= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TFnXFvf3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TFnXFvf3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70890C4CEDD; Wed, 8 Jan 2025 11:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736336882; bh=Km7GShoT8pXc+hDHCfYuInJ3NIvt6jXsbtyKkCJ3IeA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=TFnXFvf3Qiv291SD7MJT0EpfdiTbYBJZUCEzoYXCRs8KnQFGXeG4/p5uOkuvrHgB+ YyzVFl3o5+xde1rXmmHC9QvkRynwdGo+GAwu5Rk783Q2VwUrBjV6GDCPribxt9/zEl eAcliHRseiPzIIl/yG8JXPTIn+ytz9+550NecZ5OfJFKQNoj/iy7nj/Jm00QrxyWbv eeKQrtA8NyTxNmVh77QMpVPIUAuOkabvYUxYq1mBUJK/1QRTzEO4iQRz/Tuut2o+a0 Xl90QiaV0Zmdhd1p8nIUyJf3HVi1VPhzkAiJ3lZE5mW81Td+uYIjKb/9uWroyQsAT3 SRWHCIbcUPb1w== Message-ID: <8ff20f2c-fe72-48a6-ad00-872ca20f5e8c@kernel.org> Date: Wed, 8 Jan 2025 12:47:57 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET To: Shubhrajyoti Datta , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: git@amd.com References: <20250108113338.20289-1-shubhrajyoti.datta@amd.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/01/2025 12:33, Shubhrajyoti Datta wrote: > description: | > - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC > + Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs > > properties: > $nodename: > @@ -187,6 +187,10 @@ properties: > - const: qemu,mbv > - const: amd,mbv > > + - description: Xilinx Versal NET > + items: > + - const: xlnx,versal-net It is usually too difficult to use SoCs on their own. Just too small pins for our clumsy fingers. Therefore I don't get how this is supposed to be used... Anyway, provide the user for the binding (DTS). Best regards, Krzysztof