* [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
2025-08-16 10:46 [PATCH 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Dan Carpenter
@ 2025-08-16 10:47 ` Ciprian Costea
2025-08-16 12:29 ` Rob Herring (Arm)
` (2 more replies)
2025-08-16 10:47 ` [PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver Dan Carpenter
2025-08-18 18:24 ` [PATCH 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Rob Herring (Arm)
2 siblings, 3 replies; 8+ messages in thread
From: Ciprian Costea @ 2025-08-16 10:47 UTC (permalink / raw)
To: Srinivas Kandagatla
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ciprian Costea,
devicetree, linux-kernel, linaro-s32, NXP S32 Linux Team,
Srinivas Kandagatla
Add bindings to expose the On Chip One-Time Programmable Controller
(OCOTP) for the NXP s32g chipset. There are three versions of this
chip but they're compatible so we can fall back to the nxp,s32g2-ocotp
compatible.
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
.../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
new file mode 100644
index 000000000000..19f3bb6b7eb0
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S32G OCOTP NVMEM driver
+
+maintainers:
+ - Ciprian Costea <ciprianmarian.costea@nxp.com>
+
+description: |
+ The drivers provides an interface to access One Time
+ Programmable memory pages, such as TMU fuse values.
+
+allOf:
+ - $ref: nvmem.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - nxp,s32g3-ocotp
+ - nxp,s32r45-ocotp
+ - const: nxp,s32g2-ocotp
+
+ reg:
+ description:
+ Address and Size of the fuse bank to be read.
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/nvmem/s32g-ocotp-nvmem.h>
+
+ ocotp: ocotp@400a4000 {
+ compatible = "nxp,s32g2-ocotp";
+ reg = <0x400a4000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+ };
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
2025-08-16 10:47 ` [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Ciprian Costea
@ 2025-08-16 12:29 ` Rob Herring (Arm)
2025-08-17 5:48 ` Krzysztof Kozlowski
2025-08-18 8:03 ` Krzysztof Kozlowski
2 siblings, 0 replies; 8+ messages in thread
From: Rob Herring (Arm) @ 2025-08-16 12:29 UTC (permalink / raw)
To: Ciprian Costea
Cc: devicetree, Srinivas Kandagatla, Ciprian Costea, Conor Dooley,
Krzysztof Kozlowski, linaro-s32, NXP S32 Linux Team, linux-kernel
On Sat, 16 Aug 2025 13:47:03 +0300, Ciprian Costea wrote:
> Add bindings to expose the On Chip One-Time Programmable Controller
> (OCOTP) for the NXP s32g chipset. There are three versions of this
> chip but they're compatible so we can fall back to the nxp,s32g2-ocotp
> compatible.
>
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 57 +++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.example.dts:18:18: fatal error: dt-bindings/nvmem/s32g-ocotp-nvmem.h: No such file or directory
18 | #include <dt-bindings/nvmem/s32g-ocotp-nvmem.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:132: Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1524: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/7d0e025ed3fdc9e545f1d0b84f6a1cbb9dfb4e91.1755341000.git.dan.carpenter@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
2025-08-16 10:47 ` [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Ciprian Costea
2025-08-16 12:29 ` Rob Herring (Arm)
@ 2025-08-17 5:48 ` Krzysztof Kozlowski
2025-08-18 8:03 ` Krzysztof Kozlowski
2 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-17 5:48 UTC (permalink / raw)
To: Ciprian Costea, Srinivas Kandagatla
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ciprian Costea,
devicetree, linux-kernel, linaro-s32, NXP S32 Linux Team
On 16/08/2025 12:47, Ciprian Costea wrote:
> Add bindings to expose the On Chip One-Time Programmable Controller
> (OCOTP) for the NXP s32g chipset. There are three versions of this
> chip but they're compatible so we can fall back to the nxp,s32g2-ocotp
> compatible.
>
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 57 +++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
>
> diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
> new file mode 100644
> index 000000000000..19f3bb6b7eb0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP S32G OCOTP NVMEM driver
> +
> +maintainers:
> + - Ciprian Costea <ciprianmarian.costea@nxp.com>
> +
> +description: |
> + The drivers provides an interface to access One Time
> + Programmable memory pages, such as TMU fuse values.
> +
> +allOf:
> + - $ref: nvmem.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - nxp,s32g3-ocotp
> + - nxp,s32r45-ocotp
> + - const: nxp,s32g2-ocotp
> +
> + reg:
> + description:
> + Address and Size of the fuse bank to be read.
Drop description, redundant.
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
Drop these cells, already in nvmem.yaml.
> +
> +required:
> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/nvmem/s32g-ocotp-nvmem.h>
There is no such file.
> +
> + ocotp: ocotp@400a4000 {
> + compatible = "nxp,s32g2-ocotp";
> + reg = <0x400a4000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + status = "okay";
Please drop status
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
2025-08-16 10:47 ` [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Ciprian Costea
2025-08-16 12:29 ` Rob Herring (Arm)
2025-08-17 5:48 ` Krzysztof Kozlowski
@ 2025-08-18 8:03 ` Krzysztof Kozlowski
2 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-18 8:03 UTC (permalink / raw)
To: Ciprian Costea
Cc: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ciprian Costea, devicetree, linux-kernel,
linaro-s32, NXP S32 Linux Team
On Sat, Aug 16, 2025 at 01:47:03PM +0300, Ciprian Costea wrote:
> Add bindings to expose the On Chip One-Time Programmable Controller
> (OCOTP) for the NXP s32g chipset. There are three versions of this
> chip but they're compatible so we can fall back to the nxp,s32g2-ocotp
> compatible.
>
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Also, completely messed From field. I wonder how did you create it...
If you wanted to take ownership, then it is:
git commit --amend --reset-author --signoff
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver
2025-08-16 10:46 [PATCH 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Dan Carpenter
2025-08-16 10:47 ` [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Ciprian Costea
@ 2025-08-16 10:47 ` Dan Carpenter
2025-08-17 5:53 ` Krzysztof Kozlowski
2025-08-18 18:24 ` [PATCH 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Rob Herring (Arm)
2 siblings, 1 reply; 8+ messages in thread
From: Dan Carpenter @ 2025-08-16 10:47 UTC (permalink / raw)
To: Chester Lin
Cc: Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
imx, devicetree, linux-kernel, linaro-s32, Srinivas Kandagatla
Add the device tree information for the S32G On Chip One-Time
Programmable Controller (OCOTP) chip.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 09d2fbbe1d8c..e58ea0d3b083 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -612,5 +612,12 @@ gic: interrupt-controller@50800000 {
interrupt-controller;
#interrupt-cells = <3>;
};
+
+ ocotp: ocotp@400a4000 {
+ compatible = "nxp,s32g2-ocotp";
+ reg = <0x400a4000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 39effbe8217c..184a29dea184 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -681,6 +681,13 @@ gic: interrupt-controller@50800000 {
<0x50420000 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ ocotp: ocotp@400a4000 {
+ compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
+ reg = <0x400a4000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
timer {
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver
2025-08-16 10:47 ` [PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver Dan Carpenter
@ 2025-08-17 5:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2025-08-17 5:53 UTC (permalink / raw)
To: Dan Carpenter, Chester Lin
Cc: Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
imx, devicetree, linux-kernel, linaro-s32, Srinivas Kandagatla
On 16/08/2025 12:47, Dan Carpenter wrote:
> Add the device tree information for the S32G On Chip One-Time
> Programmable Controller (OCOTP) chip.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 09d2fbbe1d8c..e58ea0d3b083 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -612,5 +612,12 @@ gic: interrupt-controller@50800000 {
> interrupt-controller;
> #interrupt-cells = <3>;
> };
> +
> + ocotp: ocotp@400a4000 {
Nodename: efuse@ or nvmem@
> + compatible = "nxp,s32g2-ocotp";
> + reg = <0x400a4000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 39effbe8217c..184a29dea184 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -681,6 +681,13 @@ gic: interrupt-controller@50800000 {
> <0x50420000 0x2000>;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + ocotp: ocotp@400a4000 {
Same here
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP
2025-08-16 10:46 [PATCH 0/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Dan Carpenter
2025-08-16 10:47 ` [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Ciprian Costea
2025-08-16 10:47 ` [PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver Dan Carpenter
@ 2025-08-18 18:24 ` Rob Herring (Arm)
2 siblings, 0 replies; 8+ messages in thread
From: Rob Herring (Arm) @ 2025-08-18 18:24 UTC (permalink / raw)
To: Dan Carpenter
Cc: Conor Dooley, Krzysztof Kozlowski, linux-arm-kernel, Sascha Hauer,
Shawn Guo, Ciprian Costea, Ghennadi Procopciuc,
NXP S32 Linux Team, devicetree, Fabio Estevam,
Pengutronix Kernel Team, imx, linux-kernel, linaro-s32,
Matthias Brugger, Chester Lin, Srinivas Kandagatla
On Sat, 16 Aug 2025 13:46:57 +0300, Dan Carpenter wrote:
> This driver provides a way to access the On Chip One-Time Programmable
> Controller (OCOTP) on the s32g chipset. There are three versions of this
> chip but they're compatible.
>
> Ciprian Costea (2):
> dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
> nvmem: s32g-ocotp: Add driver for S32G OCOTP
>
> Dan Carpenter (1):
> arm64: dts: s32g: Add device tree information for the OCOTP driver
>
> .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 57 ++++++
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +
> drivers/nvmem/Kconfig | 10 +
> drivers/nvmem/Makefile | 2 +
> drivers/nvmem/s32g-ocotp-nvmem.c | 171 ++++++++++++++++++
> 6 files changed, 254 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml
> create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c
>
> --
> 2.47.2
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: remotes/korg/master-95-g90d970cade8e (exact match)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/freescale/' for cover.1755341000.git.dan.carpenter@linaro.org:
arch/arm64/boot/dts/freescale/s32g274a-evb.dtb: ocotp@400a4000 (nxp,s32g2-ocotp): compatible: 'oneOf' conditional failed, one must be fixed:
['nxp,s32g2-ocotp'] is too short
'nxp,s32g2-ocotp' is not one of ['nxp,s32g3-ocotp', 'nxp,s32r45-ocotp']
from schema $id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
arch/arm64/boot/dts/freescale/s32g274a-evb.dtb: ocotp@400a4000 (nxp,s32g2-ocotp): Unevaluated properties are not allowed ('compatible' was unexpected)
from schema $id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dtb: ocotp@400a4000 (nxp,s32g2-ocotp): compatible: 'oneOf' conditional failed, one must be fixed:
['nxp,s32g2-ocotp'] is too short
'nxp,s32g2-ocotp' is not one of ['nxp,s32g3-ocotp', 'nxp,s32r45-ocotp']
from schema $id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dtb: ocotp@400a4000 (nxp,s32g2-ocotp): Unevaluated properties are not allowed ('compatible' was unexpected)
from schema $id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml#
^ permalink raw reply [flat|nested] 8+ messages in thread