* [PATCH v2 1/7] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-15 12:49 ` Konrad Dybcio
2022-12-14 17:11 ` [PATCH v2 2/7] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21 Brian Masney
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
In preparation for adding the missing SPI and I2C nodes to
sc8280xp.dtsi, it was decided to rename all of the existing qupX_
uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
and rename qup2_uart17 to uart17. Note that some nodes are moved in the
file by this patch to preserve the expected sort order in the file.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
---
This is a new patch that's introduced in v2.
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 12 ++++++------
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 12 ++++++------
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 14 +++++++-------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 84cb6f3eeb56..61f2e44e70c1 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -17,7 +17,7 @@ / {
compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
aliases {
- serial0 = &qup2_uart17;
+ serial0 = &uart17;
};
chosen {
@@ -240,11 +240,6 @@ &qup2 {
status = "okay";
};
-&qup2_uart17 {
- compatible = "qcom,geni-debug-uart";
- status = "okay";
-};
-
&remoteproc_adsp {
firmware-name = "qcom/sa8540p/adsp.mbn";
status = "okay";
@@ -338,6 +333,11 @@ pm8450g_gpios: gpio@c000 {
};
};
+&uart17 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
+
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 21f3ff024910..b6e0db5508c7 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -17,7 +17,7 @@ / {
compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
aliases {
- serial0 = &qup2_uart17;
+ serial0 = &uart17;
};
chosen {
@@ -192,11 +192,6 @@ &qup2 {
status = "okay";
};
-&qup2_uart17 {
- compatible = "qcom,geni-debug-uart";
- status = "okay";
-};
-
&remoteproc_nsp0 {
firmware-name = "qcom/sa8540p/cdsp.mbn";
status = "okay";
@@ -207,6 +202,11 @@ &remoteproc_nsp1 {
status = "okay";
};
+&uart17 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
+
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 551768f97729..db273face248 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -17,7 +17,7 @@ / {
compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
aliases {
- serial0 = &qup2_uart17;
+ serial0 = &uart17;
};
backlight {
@@ -363,12 +363,6 @@ keyboard@68 {
};
};
-&qup2_uart17 {
- compatible = "qcom,geni-debug-uart";
-
- status = "okay";
-};
-
&remoteproc_adsp {
firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
@@ -381,6 +375,12 @@ &remoteproc_nsp0 {
status = "okay";
};
+&uart17 {
+ compatible = "qcom,geni-debug-uart";
+
+ status = "okay";
+};
+
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 109c9d2b684d..951cb1b6fcc4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -813,7 +813,7 @@ qup2: geniqup@8c0000 {
status = "disabled";
- qup2_uart17: serial@884000 {
+ uart17: serial@884000 {
compatible = "qcom,geni-uart";
reg = <0 0x00884000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/7] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17
2022-12-14 17:11 ` [PATCH v2 1/7] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17 Brian Masney
@ 2022-12-15 12:49 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-15 12:49 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, robh+dt, johan+linaro, linux-arm-msm, devicetree,
linux-kernel, ahalaney, echanude
On 14.12.2022 18:11, Brian Masney wrote:
> In preparation for adding the missing SPI and I2C nodes to
> sc8280xp.dtsi, it was decided to rename all of the existing qupX_
> uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
> and rename qup2_uart17 to uart17. Note that some nodes are moved in the
> file by this patch to preserve the expected sort order in the file.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> This is a new patch that's introduced in v2.
>
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 12 ++++++------
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 12 ++++++------
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 14 +++++++-------
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 4 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> index 84cb6f3eeb56..61f2e44e70c1 100644
> --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> @@ -17,7 +17,7 @@ / {
> compatible = "qcom,sa8295p-adp", "qcom,sa8540p";
>
> aliases {
> - serial0 = &qup2_uart17;
> + serial0 = &uart17;
> };
>
> chosen {
> @@ -240,11 +240,6 @@ &qup2 {
> status = "okay";
> };
>
> -&qup2_uart17 {
> - compatible = "qcom,geni-debug-uart";
> - status = "okay";
> -};
> -
> &remoteproc_adsp {
> firmware-name = "qcom/sa8540p/adsp.mbn";
> status = "okay";
> @@ -338,6 +333,11 @@ pm8450g_gpios: gpio@c000 {
> };
> };
>
> +&uart17 {
> + compatible = "qcom,geni-debug-uart";
> + status = "okay";
> +};
> +
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index 21f3ff024910..b6e0db5508c7 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -17,7 +17,7 @@ / {
> compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
>
> aliases {
> - serial0 = &qup2_uart17;
> + serial0 = &uart17;
> };
>
> chosen {
> @@ -192,11 +192,6 @@ &qup2 {
> status = "okay";
> };
>
> -&qup2_uart17 {
> - compatible = "qcom,geni-debug-uart";
> - status = "okay";
> -};
> -
> &remoteproc_nsp0 {
> firmware-name = "qcom/sa8540p/cdsp.mbn";
> status = "okay";
> @@ -207,6 +202,11 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> +&uart17 {
> + compatible = "qcom,geni-debug-uart";
> + status = "okay";
> +};
> +
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 551768f97729..db273face248 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -17,7 +17,7 @@ / {
> compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
>
> aliases {
> - serial0 = &qup2_uart17;
> + serial0 = &uart17;
> };
>
> backlight {
> @@ -363,12 +363,6 @@ keyboard@68 {
> };
> };
>
> -&qup2_uart17 {
> - compatible = "qcom,geni-debug-uart";
> -
> - status = "okay";
> -};
> -
> &remoteproc_adsp {
> firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
>
> @@ -381,6 +375,12 @@ &remoteproc_nsp0 {
> status = "okay";
> };
>
> +&uart17 {
> + compatible = "qcom,geni-debug-uart";
> +
> + status = "okay";
> +};
> +
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 109c9d2b684d..951cb1b6fcc4 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -813,7 +813,7 @@ qup2: geniqup@8c0000 {
>
> status = "disabled";
>
> - qup2_uart17: serial@884000 {
> + uart17: serial@884000 {
> compatible = "qcom,geni-uart";
> reg = <0 0x00884000 0 0x4000>;
> clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/7] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
2022-12-14 17:11 ` [PATCH v2 1/7] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17 Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-15 12:52 ` Konrad Dybcio
2022-12-14 17:11 ` [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 Brian Masney
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
In preparation for adding the missing SPI and I2C nodes to
sc8280xp.dtsi, it was decided to rename all of the existing qupX_
uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th
index under qup2, which starts at index 16. Note that some nodes are
moved in the file by this patch to preserve the expected sort order in
the file.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
---
This is a new patch that's introduced in v2.
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 90 ++++++-------
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 120 +++++++++---------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
3 files changed, 106 insertions(+), 106 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index db273face248..0de1bdb68e2c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -228,6 +228,43 @@ vreg_l9d: ldo9 {
};
};
+&i2c21 {
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c21_default>;
+
+ status = "okay";
+
+ touchpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpad_default>;
+
+ wakeup-source;
+ };
+
+ keyboard@68 {
+ compatible = "hid-over-i2c";
+ reg = <0x68>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&kybd_default>;
+
+ wakeup-source;
+ };
+};
+
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
@@ -326,43 +363,6 @@ &qup2 {
status = "okay";
};
-&qup2_i2c5 {
- clock-frequency = <400000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&qup2_i2c5_default>;
-
- status = "okay";
-
- touchpad@15 {
- compatible = "hid-over-i2c";
- reg = <0x15>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpad_default>;
-
- wakeup-source;
- };
-
- keyboard@68 {
- compatible = "hid-over-i2c";
- reg = <0x68>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&kybd_default>;
-
- wakeup-source;
- };
-};
-
&remoteproc_adsp {
firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
@@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state {
&tlmm {
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
+ i2c21_default: i2c21-default-state {
+ pins = "gpio81", "gpio82";
+ function = "qup21";
+
+ bias-disable;
+ drive-strength = <16>;
+ };
+
kybd_default: kybd-default-state {
disable-pins {
pins = "gpio102";
@@ -598,14 +606,6 @@ qup0_i2c4_default: qup0-i2c4-default-state {
drive-strength = <16>;
};
- qup2_i2c5_default: qup2-i2c5-default-state {
- pins = "gpio81", "gpio82";
- function = "qup21";
-
- bias-disable;
- drive-strength = <16>;
- };
-
tpad_default: tpad-default-state {
int-n-pins {
pins = "gpio182";
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 568c6be1ceaa..d7af2040cbcb 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -282,6 +282,59 @@ vreg_l9d: ldo9 {
};
};
+&i2c21 {
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c21_default>;
+
+ status = "okay";
+
+ touchpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpad_default>;
+
+ wakeup-source;
+
+ status = "disabled";
+ };
+
+ touchpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+
+ hid-descr-addr = <0x20>;
+ interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpad_default>;
+
+ wakeup-source;
+ };
+
+ keyboard@68 {
+ compatible = "hid-over-i2c";
+ reg = <0x68>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&kybd_default>;
+
+ wakeup-source;
+ };
+};
+
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
@@ -531,59 +584,6 @@ &qup2 {
status = "okay";
};
-&qup2_i2c5 {
- clock-frequency = <400000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&qup2_i2c5_default>;
-
- status = "okay";
-
- touchpad@15 {
- compatible = "hid-over-i2c";
- reg = <0x15>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpad_default>;
-
- wakeup-source;
-
- status = "disabled";
- };
-
- touchpad@2c {
- compatible = "hid-over-i2c";
- reg = <0x2c>;
-
- hid-descr-addr = <0x20>;
- interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpad_default>;
-
- wakeup-source;
- };
-
- keyboard@68 {
- compatible = "hid-over-i2c";
- reg = <0x68>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&kybd_default>;
-
- wakeup-source;
- };
-};
-
&remoteproc_adsp {
firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn";
@@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state {
bias-disable;
};
+ i2c21_default: i2c21-default-state {
+ pins = "gpio81", "gpio82";
+ function = "qup21";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
kybd_default: kybd-default-state {
disable-pins {
pins = "gpio102";
@@ -801,13 +808,6 @@ qup0_i2c4_default: qup0-i2c4-default-state {
drive-strength = <16>;
};
- qup2_i2c5_default: qup2-i2c5-default-state {
- pins = "gpio81", "gpio82";
- function = "qup21";
- bias-disable;
- drive-strength = <16>;
- };
-
tpad_default: tpad-default-state {
int-n-pins {
pins = "gpio182";
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 951cb1b6fcc4..929365cff555 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -827,7 +827,7 @@ uart17: serial@884000 {
status = "disabled";
};
- qup2_i2c5: i2c@894000 {
+ i2c21: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 2/7] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21
2022-12-14 17:11 ` [PATCH v2 2/7] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21 Brian Masney
@ 2022-12-15 12:52 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-15 12:52 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, robh+dt, johan+linaro, linux-arm-msm, devicetree,
linux-kernel, ahalaney, echanude
On 14.12.2022 18:11, Brian Masney wrote:
> In preparation for adding the missing SPI and I2C nodes to
> sc8280xp.dtsi, it was decided to rename all of the existing qupX_
> uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
> and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th
> index under qup2, which starts at index 16. Note that some nodes are
> moved in the file by this patch to preserve the expected sort order in
> the file.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
> ---
> This is a new patch that's introduced in v2.
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 90 ++++++-------
> .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 120 +++++++++---------
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 3 files changed, 106 insertions(+), 106 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index db273face248..0de1bdb68e2c 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -228,6 +228,43 @@ vreg_l9d: ldo9 {
> };
> };
>
> +&i2c21 {
> + clock-frequency = <400000>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c21_default>;
> +
> + status = "okay";
> +
> + touchpad@15 {
> + compatible = "hid-over-i2c";
> + reg = <0x15>;
> +
> + hid-descr-addr = <0x1>;
> + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&tpad_default>;
> +
> + wakeup-source;
> + };
> +
> + keyboard@68 {
> + compatible = "hid-over-i2c";
> + reg = <0x68>;
> +
> + hid-descr-addr = <0x1>;
> + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&kybd_default>;
> +
> + wakeup-source;
> + };
> +};
> +
> &pcie2a {
> perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
> @@ -326,43 +363,6 @@ &qup2 {
> status = "okay";
> };
>
> -&qup2_i2c5 {
> - clock-frequency = <400000>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&qup2_i2c5_default>;
> -
> - status = "okay";
> -
> - touchpad@15 {
> - compatible = "hid-over-i2c";
> - reg = <0x15>;
> -
> - hid-descr-addr = <0x1>;
> - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&tpad_default>;
> -
> - wakeup-source;
> - };
> -
> - keyboard@68 {
> - compatible = "hid-over-i2c";
> - reg = <0x68>;
> -
> - hid-descr-addr = <0x1>;
> - interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&kybd_default>;
> -
> - wakeup-source;
> - };
> -};
> -
> &remoteproc_adsp {
> firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
>
> @@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state {
> &tlmm {
> gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
>
> + i2c21_default: i2c21-default-state {
> + pins = "gpio81", "gpio82";
> + function = "qup21";
> +
> + bias-disable;
> + drive-strength = <16>;
This is rather nitty, but other DTs usually do
pins
function
drive-strength
bias-
in/output-
I see this patch just moves things around, but if you were to
send a v(n+1), please consider shuffling these properties
around.
Regardless of that:
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> + };
> +
> kybd_default: kybd-default-state {
> disable-pins {
> pins = "gpio102";
> @@ -598,14 +606,6 @@ qup0_i2c4_default: qup0-i2c4-default-state {
> drive-strength = <16>;
> };
>
> - qup2_i2c5_default: qup2-i2c5-default-state {
> - pins = "gpio81", "gpio82";
> - function = "qup21";
> -
> - bias-disable;
> - drive-strength = <16>;
> - };
> -
> tpad_default: tpad-default-state {
> int-n-pins {
> pins = "gpio182";
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> index 568c6be1ceaa..d7af2040cbcb 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> @@ -282,6 +282,59 @@ vreg_l9d: ldo9 {
> };
> };
>
> +&i2c21 {
> + clock-frequency = <400000>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c21_default>;
> +
> + status = "okay";
> +
> + touchpad@15 {
> + compatible = "hid-over-i2c";
> + reg = <0x15>;
> +
> + hid-descr-addr = <0x1>;
> + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&tpad_default>;
> +
> + wakeup-source;
> +
> + status = "disabled";
> + };
> +
> + touchpad@2c {
> + compatible = "hid-over-i2c";
> + reg = <0x2c>;
> +
> + hid-descr-addr = <0x20>;
> + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&tpad_default>;
> +
> + wakeup-source;
> + };
> +
> + keyboard@68 {
> + compatible = "hid-over-i2c";
> + reg = <0x68>;
> +
> + hid-descr-addr = <0x1>;
> + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&kybd_default>;
> +
> + wakeup-source;
> + };
> +};
> +
> &pcie2a {
> perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
> @@ -531,59 +584,6 @@ &qup2 {
> status = "okay";
> };
>
> -&qup2_i2c5 {
> - clock-frequency = <400000>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&qup2_i2c5_default>;
> -
> - status = "okay";
> -
> - touchpad@15 {
> - compatible = "hid-over-i2c";
> - reg = <0x15>;
> -
> - hid-descr-addr = <0x1>;
> - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&tpad_default>;
> -
> - wakeup-source;
> -
> - status = "disabled";
> - };
> -
> - touchpad@2c {
> - compatible = "hid-over-i2c";
> - reg = <0x2c>;
> -
> - hid-descr-addr = <0x20>;
> - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&tpad_default>;
> -
> - wakeup-source;
> - };
> -
> - keyboard@68 {
> - compatible = "hid-over-i2c";
> - reg = <0x68>;
> -
> - hid-descr-addr = <0x1>;
> - interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&kybd_default>;
> -
> - wakeup-source;
> - };
> -};
> -
> &remoteproc_adsp {
> firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn";
>
> @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state {
> bias-disable;
> };
>
> + i2c21_default: i2c21-default-state {
> + pins = "gpio81", "gpio82";
> + function = "qup21";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> kybd_default: kybd-default-state {
> disable-pins {
> pins = "gpio102";
> @@ -801,13 +808,6 @@ qup0_i2c4_default: qup0-i2c4-default-state {
> drive-strength = <16>;
> };
>
> - qup2_i2c5_default: qup2-i2c5-default-state {
> - pins = "gpio81", "gpio82";
> - function = "qup21";
> - bias-disable;
> - drive-strength = <16>;
> - };
> -
> tpad_default: tpad-default-state {
> int-n-pins {
> pins = "gpio182";
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 951cb1b6fcc4..929365cff555 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -827,7 +827,7 @@ uart17: serial@884000 {
> status = "disabled";
> };
>
> - qup2_i2c5: i2c@894000 {
> + i2c21: i2c@894000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00894000 0 0x4000>;
> clock-names = "se";
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
2022-12-14 17:11 ` [PATCH v2 1/7] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17 Brian Masney
2022-12-14 17:11 ` [PATCH v2 2/7] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21 Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-15 12:53 ` Konrad Dybcio
2022-12-14 17:11 ` [PATCH v2 4/7] arm64: dts: qcom: sc8280xp: add missing i2c nodes Brian Masney
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
In preparation for adding the missing SPI and I2C nodes to
sc8280xp.dtsi, it was decided to rename all of the existing qupX_
uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the
file by this patch to preserve the expected sort order in the file.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
---
This is a new patch that's introduced in v2.
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 58 +++++++++----------
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 58 +++++++++----------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
3 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 0de1bdb68e2c..c37a9d93a2a8 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -228,6 +228,27 @@ vreg_l9d: ldo9 {
};
};
+&i2c4 {
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_default>;
+
+ status = "okay";
+
+ touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts0_default>;
+ };
+};
+
&i2c21 {
clock-frequency = <400000>;
@@ -334,27 +355,6 @@ &qup0 {
status = "okay";
};
-&qup0_i2c4 {
- clock-frequency = <400000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&qup0_i2c4_default>;
-
- status = "okay";
-
- touchscreen@10 {
- compatible = "hid-over-i2c";
- reg = <0x10>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&ts0_default>;
- };
-};
-
&qup1 {
status = "okay";
};
@@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state {
&tlmm {
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
+ i2c4_default: i2c4-default-state {
+ pins = "gpio171", "gpio172";
+ function = "qup4";
+
+ bias-disable;
+ drive-strength = <16>;
+ };
+
i2c21_default: i2c21-default-state {
pins = "gpio81", "gpio82";
function = "qup21";
@@ -598,14 +606,6 @@ wake-n-pins {
};
};
- qup0_i2c4_default: qup0-i2c4-default-state {
- pins = "gpio171", "gpio172";
- function = "qup4";
-
- bias-disable;
- drive-strength = <16>;
- };
-
tpad_default: tpad-default-state {
int-n-pins {
pins = "gpio182";
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index d7af2040cbcb..ec06b6216408 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -282,6 +282,28 @@ vreg_l9d: ldo9 {
};
};
+&i2c4 {
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_default>;
+
+ status = "okay";
+
+ /* FIXME: verify */
+ touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&vreg_misc_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts0_default>;
+ };
+};
+
&i2c21 {
clock-frequency = <400000>;
@@ -554,28 +576,6 @@ &qup0 {
status = "okay";
};
-&qup0_i2c4 {
- clock-frequency = <400000>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&qup0_i2c4_default>;
-
- status = "okay";
-
- /* FIXME: verify */
- touchscreen@10 {
- compatible = "hid-over-i2c";
- reg = <0x10>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
- vdd-supply = <&vreg_misc_3p3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&ts0_default>;
- };
-};
-
&qup1 {
status = "okay";
};
@@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state {
bias-disable;
};
+ i2c4_default: i2c4-default-state {
+ pins = "gpio171", "gpio172";
+ function = "qup4";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
i2c21_default: i2c21-default-state {
pins = "gpio81", "gpio82";
function = "qup21";
@@ -801,13 +808,6 @@ wake-n-pins {
};
};
- qup0_i2c4_default: qup0-i2c4-default-state {
- pins = "gpio171", "gpio172";
- function = "qup4";
- bias-disable;
- drive-strength = <16>;
- };
-
tpad_default: tpad-default-state {
int-n-pins {
pins = "gpio182";
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 929365cff555..f1111cd7f679 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -858,7 +858,7 @@ qup0: geniqup@9c0000 {
status = "disabled";
- qup0_i2c4: i2c@990000 {
+ i2c4: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4
2022-12-14 17:11 ` [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 Brian Masney
@ 2022-12-15 12:53 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-15 12:53 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, robh+dt, johan+linaro, linux-arm-msm, devicetree,
linux-kernel, ahalaney, echanude
On 14.12.2022 18:11, Brian Masney wrote:
> In preparation for adding the missing SPI and I2C nodes to
> sc8280xp.dtsi, it was decided to rename all of the existing qupX_
> uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead
> and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the
> file by this patch to preserve the expected sort order in the file.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> This is a new patch that's introduced in v2.
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 58 +++++++++----------
> .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 58 +++++++++----------
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 3 files changed, 59 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 0de1bdb68e2c..c37a9d93a2a8 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -228,6 +228,27 @@ vreg_l9d: ldo9 {
> };
> };
>
> +&i2c4 {
> + clock-frequency = <400000>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c4_default>;
> +
> + status = "okay";
> +
> + touchscreen@10 {
> + compatible = "hid-over-i2c";
> + reg = <0x10>;
> +
> + hid-descr-addr = <0x1>;
> + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&ts0_default>;
> + };
> +};
> +
> &i2c21 {
> clock-frequency = <400000>;
>
> @@ -334,27 +355,6 @@ &qup0 {
> status = "okay";
> };
>
> -&qup0_i2c4 {
> - clock-frequency = <400000>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&qup0_i2c4_default>;
> -
> - status = "okay";
> -
> - touchscreen@10 {
> - compatible = "hid-over-i2c";
> - reg = <0x10>;
> -
> - hid-descr-addr = <0x1>;
> - interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&ts0_default>;
> - };
> -};
> -
> &qup1 {
> status = "okay";
> };
> @@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state {
> &tlmm {
> gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
>
> + i2c4_default: i2c4-default-state {
> + pins = "gpio171", "gpio172";
> + function = "qup4";
> +
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> i2c21_default: i2c21-default-state {
> pins = "gpio81", "gpio82";
> function = "qup21";
> @@ -598,14 +606,6 @@ wake-n-pins {
> };
> };
>
> - qup0_i2c4_default: qup0-i2c4-default-state {
> - pins = "gpio171", "gpio172";
> - function = "qup4";
> -
> - bias-disable;
> - drive-strength = <16>;
> - };
> -
> tpad_default: tpad-default-state {
> int-n-pins {
> pins = "gpio182";
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> index d7af2040cbcb..ec06b6216408 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> @@ -282,6 +282,28 @@ vreg_l9d: ldo9 {
> };
> };
>
> +&i2c4 {
> + clock-frequency = <400000>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c4_default>;
> +
> + status = "okay";
> +
> + /* FIXME: verify */
> + touchscreen@10 {
> + compatible = "hid-over-i2c";
> + reg = <0x10>;
> +
> + hid-descr-addr = <0x1>;
> + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
> + vdd-supply = <&vreg_misc_3p3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&ts0_default>;
> + };
> +};
> +
> &i2c21 {
> clock-frequency = <400000>;
>
> @@ -554,28 +576,6 @@ &qup0 {
> status = "okay";
> };
>
> -&qup0_i2c4 {
> - clock-frequency = <400000>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&qup0_i2c4_default>;
> -
> - status = "okay";
> -
> - /* FIXME: verify */
> - touchscreen@10 {
> - compatible = "hid-over-i2c";
> - reg = <0x10>;
> -
> - hid-descr-addr = <0x1>;
> - interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
> - vdd-supply = <&vreg_misc_3p3>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&ts0_default>;
> - };
> -};
> -
> &qup1 {
> status = "okay";
> };
> @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state {
> bias-disable;
> };
>
> + i2c4_default: i2c4-default-state {
> + pins = "gpio171", "gpio172";
> + function = "qup4";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> i2c21_default: i2c21-default-state {
> pins = "gpio81", "gpio82";
> function = "qup21";
> @@ -801,13 +808,6 @@ wake-n-pins {
> };
> };
>
> - qup0_i2c4_default: qup0-i2c4-default-state {
> - pins = "gpio171", "gpio172";
> - function = "qup4";
> - bias-disable;
> - drive-strength = <16>;
> - };
> -
> tpad_default: tpad-default-state {
> int-n-pins {
> pins = "gpio182";
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 929365cff555..f1111cd7f679 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -858,7 +858,7 @@ qup0: geniqup@9c0000 {
>
> status = "disabled";
>
> - qup0_i2c4: i2c@990000 {
> + i2c4: i2c@990000 {
> compatible = "qcom,geni-i2c";
> reg = <0 0x00990000 0 0x4000>;
> clock-names = "se";
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] arm64: dts: qcom: sc8280xp: add missing i2c nodes
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
` (2 preceding siblings ...)
2022-12-14 17:11 ` [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-14 17:11 ` [PATCH v2 5/7] arm64: dts: qcom: sc8280xp: add missing spi nodes Brian Masney
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
Add the missing nodes for the i2c buses that's present on this SoC.
This work was derived from various patches that Qualcomm delivered
to Red Hat in a downstream kernel.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
Changes since v1:
- Dropped qupX_ prefix from labels. (Johan)
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 352 +++++++++++++++++++++++++
1 file changed, 352 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index f1111cd7f679..a502d4e19d98 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -813,6 +813,38 @@ qup2: geniqup@8c0000 {
status = "disabled";
+ i2c16: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c17: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
uart17: serial@884000 {
compatible = "qcom,geni-uart";
reg = <0 0x00884000 0 0x4000>;
@@ -827,6 +859,54 @@ uart17: serial@884000 {
status = "disabled";
};
+ i2c18: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c19: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c20: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00890000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c21: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
@@ -842,6 +922,38 @@ i2c21: i2c@894000 {
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
+
+ i2c22: i2c@898000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00898000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c23: i2c@89c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0089c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
};
qup0: geniqup@9c0000 {
@@ -858,6 +970,70 @@ qup0: geniqup@9c0000 {
status = "disabled";
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00980000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00984000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00988000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0098c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c4: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
@@ -873,6 +1049,54 @@ i2c4: i2c@990000 {
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00998000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0099c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
};
qup1: geniqup@ac0000 {
@@ -888,6 +1112,134 @@ qup1: geniqup@ac0000 {
ranges;
status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC8280XP_CX>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
};
pcie4: pcie@1c00000 {
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 5/7] arm64: dts: qcom: sc8280xp: add missing spi nodes
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
` (3 preceding siblings ...)
2022-12-14 17:11 ` [PATCH v2 4/7] arm64: dts: qcom: sc8280xp: add missing i2c nodes Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-14 17:11 ` [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes Brian Masney
2022-12-14 17:11 ` [PATCH v2 7/7] arm64: dts: qcom: sc8280xp: add rng device tree node Brian Masney
6 siblings, 0 replies; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
Add the missing nodes for the spi buses that's present on this SoC.
This work was derived from various patches that Qualcomm delivered
to Red Hat in a downstream kernel.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
Changes since v1:
- Dropped qupX_ prefix from labels. (Johan)
- Dropped spi-max-frequency property from spi nodes. (Shazad)
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 360 +++++++++++++++++++++++++
1 file changed, 360 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index a502d4e19d98..4591d411f5fb 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -829,6 +829,21 @@ i2c16: i2c@880000 {
status = "disabled";
};
+ spi16: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00880000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c17: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00884000 0 0x4000>;
@@ -845,6 +860,21 @@ i2c17: i2c@884000 {
status = "disabled";
};
+ spi17: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00884000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
uart17: serial@884000 {
compatible = "qcom,geni-uart";
reg = <0 0x00884000 0 0x4000>;
@@ -875,6 +905,21 @@ i2c18: i2c@888000 {
status = "disabled";
};
+ spi18: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00888000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c19: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
@@ -891,6 +936,21 @@ i2c19: i2c@88c000 {
status = "disabled";
};
+ spi19: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0088c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c20: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
@@ -907,6 +967,21 @@ i2c20: i2c@890000 {
status = "disabled";
};
+ spi20: spi@890000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00890000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c21: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
@@ -923,6 +998,21 @@ i2c21: i2c@894000 {
status = "disabled";
};
+ spi21: spi@894000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00894000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c22: i2c@898000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00898000 0 0x4000>;
@@ -939,6 +1029,21 @@ i2c22: i2c@898000 {
status = "disabled";
};
+ spi22: spi@898000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00898000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c23: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0089c000 0 0x4000>;
@@ -954,6 +1059,21 @@ i2c23: i2c@89c000 {
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
+
+ spi23: spi@89c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0089c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
};
qup0: geniqup@9c0000 {
@@ -986,6 +1106,21 @@ i2c0: i2c@980000 {
status = "disabled";
};
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c1: i2c@984000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00984000 0 0x4000>;
@@ -1002,6 +1137,21 @@ i2c1: i2c@984000 {
status = "disabled";
};
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c2: i2c@988000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00988000 0 0x4000>;
@@ -1018,6 +1168,21 @@ i2c2: i2c@988000 {
status = "disabled";
};
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
@@ -1034,6 +1199,21 @@ i2c3: i2c@98c000 {
status = "disabled";
};
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c4: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
@@ -1050,6 +1230,21 @@ i2c4: i2c@990000 {
status = "disabled";
};
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c5: i2c@994000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00994000 0 0x4000>;
@@ -1066,6 +1261,21 @@ i2c5: i2c@994000 {
status = "disabled";
};
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00994000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c6: i2c@998000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00998000 0 0x4000>;
@@ -1082,6 +1292,21 @@ i2c6: i2c@998000 {
status = "disabled";
};
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c7: i2c@99c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0099c000 0 0x4000>;
@@ -1097,6 +1322,21 @@ i2c7: i2c@99c000 {
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
+
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
};
qup1: geniqup@ac0000 {
@@ -1129,6 +1369,21 @@ i2c8: i2c@a80000 {
status = "disabled";
};
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
@@ -1145,6 +1400,21 @@ i2c9: i2c@a84000 {
status = "disabled";
};
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
@@ -1161,6 +1431,21 @@ i2c10: i2c@a88000 {
status = "disabled";
};
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
@@ -1177,6 +1462,21 @@ i2c11: i2c@a8c000 {
status = "disabled";
};
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a90000 0 0x4000>;
@@ -1193,6 +1493,21 @@ i2c12: i2c@a90000 {
status = "disabled";
};
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
@@ -1209,6 +1524,21 @@ i2c13: i2c@a94000 {
status = "disabled";
};
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c14: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a98000 0 0x4000>;
@@ -1225,6 +1555,21 @@ i2c14: i2c@a98000 {
status = "disabled";
};
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
+
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a9c000 0 0x4000>;
@@ -1240,6 +1585,21 @@ i2c15: i2c@a9c000 {
interconnect-names = "qup-core", "qup-config", "qup-memory";
status = "disabled";
};
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ status = "disabled";
+ };
};
pcie4: pcie@1c00000 {
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
` (4 preceding siblings ...)
2022-12-14 17:11 ` [PATCH v2 5/7] arm64: dts: qcom: sc8280xp: add missing spi nodes Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-15 12:57 ` Konrad Dybcio
2022-12-20 12:44 ` Shazad Hussain
2022-12-14 17:11 ` [PATCH v2 7/7] arm64: dts: qcom: sc8280xp: add rng device tree node Brian Masney
6 siblings, 2 replies; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and
i2c18 functioning on the automotive board and exposed to userspace.
This work was derived from various patches that Qualcomm delivered
to Red Hat in a downstream kernel. This change was validated by using
i2c-tools 4.3.3 on CentOS Stream 9:
[root@localhost ~]# i2cdetect -l
i2c-0 i2c Geni-I2C I2C adapter
i2c-1 i2c Geni-I2C I2C adapter
i2c-12 i2c Geni-I2C I2C adapter
i2c-15 i2c Geni-I2C I2C adapter
i2c-18 i2c Geni-I2C I2C adapter
[root@localhost ~]# i2cdetect -a -y 15
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
Changes since v1:
- Dropped qupX_ prefix from labels. (Johan)
- Reordered nodes based on new name.
- Added i2c buses 0, 1, and 12 (Shazad)
- Drop mux/config-pins and have the pin properties live directly
under the i2cX-default-state node. (Konrad)
- Use decimal notation for drive strength (Johan)
A few things to note with this series applied on top of linux-next:
- Reading from i2c-0 using 'i2cdetect -y -a 0' gives the following error
when reading from the ranges 0x30-0x37 and 0x50-0x5F.
geni_i2c 980000.i2c: Timeout abort_m_cmd
- i2c-1 and i2c-2 successfully read using i2cdetect, however it takes
several seconds.
- i2cdetect runs fast within a small fraction of a second for i2c-15
and i2c18.
- 'i2cdetect -y -a $BUSNUM' shows the same address ranges 0x30-0x37
and 0x50-0x5F in use on all 5 buses.
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 83 +++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index b6e0db5508c7..ccd2ea3c9d04 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -17,6 +17,11 @@ / {
compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c12 = &i2c12;
+ i2c15 = &i2c15;
+ i2c18 = &i2c18;
serial0 = &uart17;
};
@@ -146,6 +151,41 @@ vreg_l8g: ldo8 {
};
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_default>;
+
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_default>;
+
+ status = "okay";
+};
+
+&i2c12 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c12_default>;
+
+ status = "okay";
+};
+
+&i2c15 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c15_default>;
+
+ status = "okay";
+};
+
+&i2c18 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c18_default>;
+
+ status = "okay";
+};
+
&pcie2a {
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
@@ -188,6 +228,14 @@ &pcie3a_phy {
status = "okay";
};
+&qup0 {
+ status = "okay";
+};
+
+&qup1 {
+ status = "okay";
+};
+
&qup2 {
status = "okay";
};
@@ -268,6 +316,41 @@ &xo_board_clk {
/* PINCTRL */
&tlmm {
+ i2c0_default: i2c0-default-state {
+ pins = "gpio135", "gpio136";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ i2c1_default: i2c1-default-state {
+ pins = "gpio158", "gpio159";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ i2c12_default: i2c12-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ i2c15_default: i2c15-default-state {
+ pins = "gpio36", "gpio37";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ i2c18_default: i2c18-default-state {
+ pins = "gpio66", "gpio67";
+ function = "qup18";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
pcie2a_default: pcie2a-default-state {
perst-pins {
pins = "gpio143";
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes
2022-12-14 17:11 ` [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes Brian Masney
@ 2022-12-15 12:57 ` Konrad Dybcio
2022-12-20 12:44 ` Shazad Hussain
1 sibling, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-15 12:57 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, robh+dt, johan+linaro, linux-arm-msm, devicetree,
linux-kernel, ahalaney, echanude
On 14.12.2022 18:11, Brian Masney wrote:
> Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and
> i2c18 functioning on the automotive board and exposed to userspace.
>
> This work was derived from various patches that Qualcomm delivered
> to Red Hat in a downstream kernel. This change was validated by using
> i2c-tools 4.3.3 on CentOS Stream 9:
>
> [root@localhost ~]# i2cdetect -l
> i2c-0 i2c Geni-I2C I2C adapter
> i2c-1 i2c Geni-I2C I2C adapter
> i2c-12 i2c Geni-I2C I2C adapter
> i2c-15 i2c Geni-I2C I2C adapter
> i2c-18 i2c Geni-I2C I2C adapter
>
> [root@localhost ~]# i2cdetect -a -y 15
> Warning: Can't use SMBus Quick Write command, will skip some addresses
> 0 1 2 3 4 5 6 7 8 9 a b c d e f
> 00:
> 10:
> 20:
> 30: -- -- -- -- -- -- -- --
> 40:
> 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 60:
> 70:
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> Changes since v1:
> - Dropped qupX_ prefix from labels. (Johan)
> - Reordered nodes based on new name.
> - Added i2c buses 0, 1, and 12 (Shazad)
> - Drop mux/config-pins and have the pin properties live directly
> under the i2cX-default-state node. (Konrad)
> - Use decimal notation for drive strength (Johan)
>
> A few things to note with this series applied on top of linux-next:
> - Reading from i2c-0 using 'i2cdetect -y -a 0' gives the following error
> when reading from the ranges 0x30-0x37 and 0x50-0x5F.
> geni_i2c 980000.i2c: Timeout abort_m_cmd
> - i2c-1 and i2c-2 successfully read using i2cdetect, however it takes
> several seconds.
> - i2cdetect runs fast within a small fraction of a second for i2c-15
> and i2c18.
> - 'i2cdetect -y -a $BUSNUM' shows the same address ranges 0x30-0x37
> and 0x50-0x5F in use on all 5 buses.
>
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 83 +++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index b6e0db5508c7..ccd2ea3c9d04 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -17,6 +17,11 @@ / {
> compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
>
> aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c12 = &i2c12;
> + i2c15 = &i2c15;
> + i2c18 = &i2c18;
> serial0 = &uart17;
> };
>
> @@ -146,6 +151,41 @@ vreg_l8g: ldo8 {
> };
> };
>
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c12 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c12_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c15 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c15_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c18 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c18_default>;
> +
> + status = "okay";
> +};
> +
> &pcie2a {
> ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
> <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
> @@ -188,6 +228,14 @@ &pcie3a_phy {
> status = "okay";
> };
>
> +&qup0 {
> + status = "okay";
> +};
> +
> +&qup1 {
> + status = "okay";
> +};
> +
> &qup2 {
> status = "okay";
> };
> @@ -268,6 +316,41 @@ &xo_board_clk {
> /* PINCTRL */
>
> &tlmm {
> + i2c0_default: i2c0-default-state {
> + pins = "gpio135", "gpio136";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c1_default: i2c1-default-state {
> + pins = "gpio158", "gpio159";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c12_default: i2c12-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c15_default: i2c15-default-state {
> + pins = "gpio36", "gpio37";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c18_default: i2c18-default-state {
> + pins = "gpio66", "gpio67";
> + function = "qup18";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> pcie2a_default: pcie2a-default-state {
> perst-pins {
> pins = "gpio143";
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes
2022-12-14 17:11 ` [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes Brian Masney
2022-12-15 12:57 ` Konrad Dybcio
@ 2022-12-20 12:44 ` Shazad Hussain
1 sibling, 0 replies; 14+ messages in thread
From: Shazad Hussain @ 2022-12-20 12:44 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: konrad.dybcio, robh+dt, johan+linaro, linux-arm-msm, devicetree,
linux-kernel, ahalaney, echanude
On 12/14/2022 10:41 PM, Brian Masney wrote:
> Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and
> i2c18 functioning on the automotive board and exposed to userspace.
>
> This work was derived from various patches that Qualcomm delivered
> to Red Hat in a downstream kernel. This change was validated by using
> i2c-tools 4.3.3 on CentOS Stream 9:
>
> [root@localhost ~]# i2cdetect -l
> i2c-0 i2c Geni-I2C I2C adapter
> i2c-1 i2c Geni-I2C I2C adapter
> i2c-12 i2c Geni-I2C I2C adapter
> i2c-15 i2c Geni-I2C I2C adapter
> i2c-18 i2c Geni-I2C I2C adapter
>
> [root@localhost ~]# i2cdetect -a -y 15
> Warning: Can't use SMBus Quick Write command, will skip some addresses
> 0 1 2 3 4 5 6 7 8 9 a b c d e f
> 00:
> 10:
> 20:
> 30: -- -- -- -- -- -- -- --
> 40:
> 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 60:
> 70:
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
Tested-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Verified on next-20221220.
> ---
> Changes since v1:
> - Dropped qupX_ prefix from labels. (Johan)
> - Reordered nodes based on new name.
> - Added i2c buses 0, 1, and 12 (Shazad)
> - Drop mux/config-pins and have the pin properties live directly
> under the i2cX-default-state node. (Konrad)
> - Use decimal notation for drive strength (Johan)
>
> A few things to note with this series applied on top of linux-next:
> - Reading from i2c-0 using 'i2cdetect -y -a 0' gives the following error
> when reading from the ranges 0x30-0x37 and 0x50-0x5F.
> geni_i2c 980000.i2c: Timeout abort_m_cmd > - i2c-1 and i2c-2 successfully read using i2cdetect, however it takes
> several seconds.
expected, as no slaves are connected.
> - i2cdetect runs fast within a small fraction of a second for i2c-15
> and i2c18.
slaves have ack on addr:0x18 ret:1 for i2c-15 and addr:0x6a ret:1 for i2c-18
> - 'i2cdetect -y -a $BUSNUM' shows the same address ranges 0x30-0x37
> and 0x50-0x5F in use on all 5 buses.
>
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 83 +++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index b6e0db5508c7..ccd2ea3c9d04 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -17,6 +17,11 @@ / {
> compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
>
> aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c12 = &i2c12;
> + i2c15 = &i2c15;
> + i2c18 = &i2c18;
> serial0 = &uart17;
> };
>
> @@ -146,6 +151,41 @@ vreg_l8g: ldo8 {
> };
> };
>
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c12 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c12_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c15 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c15_default>;
> +
> + status = "okay";
> +};
> +
> +&i2c18 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c18_default>;
> +
> + status = "okay";
> +};
> +
> &pcie2a {
> ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
> <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
> @@ -188,6 +228,14 @@ &pcie3a_phy {
> status = "okay";
> };
>
> +&qup0 {
> + status = "okay";
> +};
> +
> +&qup1 {
> + status = "okay";
> +};
> +
> &qup2 {
> status = "okay";
> };
> @@ -268,6 +316,41 @@ &xo_board_clk {
> /* PINCTRL */
>
> &tlmm {
> + i2c0_default: i2c0-default-state {
> + pins = "gpio135", "gpio136";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c1_default: i2c1-default-state {
> + pins = "gpio158", "gpio159";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c12_default: i2c12-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c15_default: i2c15-default-state {
> + pins = "gpio36", "gpio37";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + i2c18_default: i2c18-default-state {
> + pins = "gpio66", "gpio67";
> + function = "qup18";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> pcie2a_default: pcie2a-default-state {
> perst-pins {
> pins = "gpio143";
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] arm64: dts: qcom: sc8280xp: add rng device tree node
2022-12-14 17:11 [PATCH v2 0/7] dts: qcom: sc8280xp: add i2c, spi, and rng nodes Brian Masney
` (5 preceding siblings ...)
2022-12-14 17:11 ` [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes Brian Masney
@ 2022-12-14 17:11 ` Brian Masney
2022-12-15 12:56 ` Konrad Dybcio
6 siblings, 1 reply; 14+ messages in thread
From: Brian Masney @ 2022-12-14 17:11 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, konrad.dybcio, robh+dt, johan+linaro,
linux-arm-msm, devicetree, linux-kernel, ahalaney, echanude
Add the necessary device tree node for qcom,prng-ee so we can use the
hardware random number generator. This functionality was tested on a
SA8540p automotive development board using kcapi-rng from libkcapi.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
This is a new patch that's introduced in v2.
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 4591d411f5fb..67765975361b 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2811,6 +2811,13 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 230>;
};
+ rng: rng@10d3000 {
+ compatible = "qcom,prng-ee";
+ reg = <0 0x010d3000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_HWKM_CLK>;
+ clock-names = "core";
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 7/7] arm64: dts: qcom: sc8280xp: add rng device tree node
2022-12-14 17:11 ` [PATCH v2 7/7] arm64: dts: qcom: sc8280xp: add rng device tree node Brian Masney
@ 2022-12-15 12:56 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-15 12:56 UTC (permalink / raw)
To: Brian Masney, andersson, krzysztof.kozlowski+dt
Cc: quic_shazhuss, robh+dt, johan+linaro, linux-arm-msm, devicetree,
linux-kernel, ahalaney, echanude
On 14.12.2022 18:11, Brian Masney wrote:
> Add the necessary device tree node for qcom,prng-ee so we can use the
> hardware random number generator. This functionality was tested on a
> SA8540p automotive development board using kcapi-rng from libkcapi.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
> ---
Nodes with MMIO addresses should be sorted address-wise, so
this one should come between qup1 and pcie4.
Konrad
> This is a new patch that's introduced in v2.
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 4591d411f5fb..67765975361b 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -2811,6 +2811,13 @@ tlmm: pinctrl@f100000 {
> gpio-ranges = <&tlmm 0 0 230>;
> };
>
> + rng: rng@10d3000 {
> + compatible = "qcom,prng-ee";
> + reg = <0 0x010d3000 0 0x1000>;
> + clocks = <&rpmhcc RPMH_HWKM_CLK>;
> + clock-names = "core";
> + };
> +
> apps_smmu: iommu@15000000 {
> compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
> reg = <0 0x15000000 0 0x100000>;
^ permalink raw reply [flat|nested] 14+ messages in thread