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Wed, 13 May 2026 11:55:07 -0700 (PDT) X-Received: by 2002:a05:6a00:810:b0:837:42a6:589d with SMTP id d2e1a72fcca58-83f0568612amr4387489b3a.11.1778698506919; Wed, 13 May 2026 11:55:06 -0700 (PDT) Received: from [192.168.0.17] ([49.205.251.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f197781c7sm240554b3a.18.2026.05.13.11.54.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 May 2026 11:55:06 -0700 (PDT) Message-ID: <905f5677-5daf-d6e9-437f-7b928036ea95@oss.qualcomm.com> Date: Thu, 14 May 2026 00:24:55 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH v5 07/14] media: iris: Enable Secure PAS support with IOMMU managed by Linux To: Dmitry Baryshkov , Mukesh Ojha Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Joerg Roedel , Will Deacon , Robin Murphy , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Jorge Ramirez-Ortiz , Del Regno , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, Krzysztof Kozlowski , devicetree@vger.kernel.org References: <20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com> <20260509-glymur-v5-7-7fbb340c5dbd@oss.qualcomm.com> <20260511080104.c4nhhmm2xgzm67fi@hu-mojha-hyd.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE4NiBTYWx0ZWRfX0rVFAM2Cfmua GzJyz4iEODZKJ1yGysQck4CMTyd4oNhdKovF6dxIcfCE0rx3N94nyImmuJu9wc0GsIxGAn9c/A3 BSccvEBexuPyYtJ38+Qw0/1OtshMDX5Y9LCr8OytNlhkyFd9E0fJcPpAEwQiW1bzt0y6PDY6KWi oOcohN8ytrAZVzjszCy3PlLtNBQXtNvOQiucePQFFB7EDSM4qela0+QKKwbQMsmfBUz2wMxX500 VmzkGd82fR+RZmmovmFVKcOccv9BfbEL/ovDUD3O/uvKIADrNkBXOdnNJ0p6B0DlfvHfaEDkRpp r/SsiNdZ2NifGI/692WBizGPtyI5fxm+L96zf+FldBc2gzgAnP5R3c7AaecidpwxHfzqGti5FyP hoPdf2pFx13jKKBd1Js3cjdviPjxNfcqyvmDu8q7XtJ0sOu6hfTL8EaL/T76EdGZ7GePy2A4qqT HaescX2dkbk8pWFvwmA== X-Authority-Analysis: v=2.4 cv=XqXK/1F9 c=1 sm=1 tr=0 ts=6a04c90c cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=UdqKVphAFhxg2bWZaUV5ew==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=B9MledX_AzLNtmQI4O4A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: kUj-_62UyPqTuzZJDvzMDEA8UGdia9mv X-Proofpoint-GUID: kUj-_62UyPqTuzZJDvzMDEA8UGdia9mv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_02,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130186 On 5/13/2026 7:12 PM, Dmitry Baryshkov wrote: > On Mon, May 11, 2026 at 01:31:04PM +0530, Mukesh Ojha wrote: >> On Fri, May 08, 2026 at 11:20:06PM +0300, Dmitry Baryshkov wrote: >>> On Sat, May 09, 2026 at 12:29:56AM +0530, Vishnu Reddy wrote: >>>> From: Mukesh Ojha >>>> >>>> Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah >>>> or QHEE), which typically handles IOMMU configuration. This includes >>>> mapping memory regions and device memory resources for remote processors >>>> by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are >>> No the calls to those functions are not intercepted. Doesn't hypervisor >>> simply implement the SCM calls? >> All the SMC calls are intercepted whenever Gunyah or QHEE hypervisor is present >> and in most of the case the preparational work for the TZ like in case of >> qcom_scm_pas_auth_and_reset() it does create/register SHMbridge over PIL memory >> so that the TZ can access the memory and then calls same SMC call to TZ for >> authentication and once done it comes back does mapping the PIL region >> and call bring up sequence of the co-processor. > I see, thanks for the explanation. > >> SMC SHM setup SMC (auth) map memory/resource and trigger reset sequence >> HLOS ==> Gunyah(QHEE) ==> TZ ==> Gunyah(QHEE) === ==> IRIS >> >> >>>> later removed during teardown. Additionally, SHM bridge setup is required >>>> to enable memory protection for both remoteproc metadata and its memory >>>> regions. >>>> >>>> When the hypervisor is absent, the operating system must perform these >>>> configurations instead. >>>> >>>> Support for handling IOMMU and SHM setup in the absence of a hypervisor >>>> is now in place. Extend the Iris driver to enable this functionality on >>>> platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). >>> I fail to identify, which changes correspond to this description. If >>> it's about the PAS context creation, could you please be more specific? >> I think, commit text is trying to tell the Infra to support any Secure PIL when IOMMU is >> managed by Linux at EL2 and the dependency related to SHM set up in Linux are done as >> part of [1] are in upstream. > Ok... I'd say, this part of the commit message might need some > polishing, but I can't give an exact advice here. > >> [1] >> https://lore.kernel.org/lkml/20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com/ >> >>>> Additionally, the Iris driver must map the firmware and its required >>>> resources to the firmware SID, which is now specified via iommu-map in >>>> the device tree. >>> Why? You miss the most important part here. >> Sorry, I did not get.. are you looking for explaination here, why via iommu-map in >> commit text ? > Yes. Why are you using iommu-map instead of listing it in the main > iommus entry? Without hypervisor: iommu-map is populated, so the driver creates a firmware device and handles the IOMMU mapping. With Gunyah/QHEE: iommu-map is omitted, firmware device is NULL, and the driver skips mapping since the hypervisor takes care of it. The main iommus entry already holds other stream IDs (pixel, non-pixel, etc.) and cannot be used to distinguish the firmware SID or infer hypervisor presence, hence the use of a separate iommu-map property. >>>> Reviewed-by: Vishnu Reddy >>>> Co-developed-by: Vikash Garodia >>>> Signed-off-by: Vikash Garodia >>>> Signed-off-by: Mukesh Ojha >>>> Signed-off-by: Vishnu Reddy >>>> --- >>>> drivers/media/platform/qcom/iris/iris_core.h | 4 ++ >>>> drivers/media/platform/qcom/iris/iris_firmware.c | 72 ++++++++++++++++++++---- >>>> 2 files changed, 66 insertions(+), 10 deletions(-) >>>> >>> -- >>> With best wishes >>> Dmitry >> -- >> -Mukesh Ojha