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[109.252.193.186]) by smtp.googlemail.com with ESMTPSA id l20sm162128lfc.274.2020.10.27.13.37.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Oct 2020 13:37:29 -0700 (PDT) Subject: Re: [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property To: Krzysztof Kozlowski Cc: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-5-digetx@gmail.com> <20201027085417.GD4244@kozik-lap> <54191034-dcb9-7cab-333b-5bb2553f0ed1@gmail.com> <20201027193039.GA140636@kozik-lap> From: Dmitry Osipenko Message-ID: <90df8e53-6dec-f75f-5f82-539cb0f72583@gmail.com> Date: Tue, 27 Oct 2020 23:37:28 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201027193039.GA140636@kozik-lap> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 27.10.2020 22:30, Krzysztof Kozlowski пишет: > On Tue, Oct 27, 2020 at 10:17:19PM +0300, Dmitry Osipenko wrote: >> 27.10.2020 11:54, Krzysztof Kozlowski пишет: >>> On Mon, Oct 26, 2020 at 01:16:47AM +0300, Dmitry Osipenko wrote: >>>> Tegra20 External Memory Controller talks to DRAM chips and it needs to be >>>> reprogrammed when memory frequency changes. Tegra Memory Controller sits >>>> behind EMC and these controllers are tightly coupled. This patch adds the >>>> new phandle property which allows to properly express connection of EMC >>>> and MC hardware in a device-tree, it also put the Tegra20 EMC binding on >>>> par with Tegra30+ EMC bindings, which is handy to have. >>>> >>>> Signed-off-by: Dmitry Osipenko >>>> --- >>>> .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt >>>> index 567cffd37f3f..1b0d4417aad8 100644 >>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt >>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt >>>> @@ -12,6 +12,7 @@ Properties: >>>> irrespective of ram-code configuration. >>>> - interrupts : Should contain EMC General interrupt. >>>> - clocks : Should contain EMC clock. >>>> +- nvidia,memory-controller : Phandle of the Memory Controller node. >>> >>> It looks like you adding a required property which is an ABI break. >> The T20 EMC driver is unused so far in upstream and it will become used >> only once this series is applied. Hence it's fine to change the ABI. > > The ABI is not about upstream, but downstream. There are no other > upstreams using this ABI. Unless you have in mind that existing T20 EMC > driver was a noop, doing absolutely nothing, therefore there is no > breakage of any other users? The T20 EMC driver was a 100% noop for now. It's safe to change the ABI. The T30/124 EMC drivers have users, but these are unsafe drivers (with the known issues) until this series is applied.