From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Xingyu Wu <xingyu.wu@starfivetech.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC
Date: Wed, 5 Jul 2023 08:27:07 +0200 [thread overview]
Message-ID: <913206a5-3ce2-3ce1-774e-3a4a9030b0e2@linaro.org> (raw)
In-Reply-To: <20230704064610.292603-1-xingyu.wu@starfivetech.com>
On 04/07/2023 08:46, Xingyu Wu wrote:
> [Resending because it has a error about examples in syscon bingdings
> and has to be fixed.]
Resending means you sent the same version. If you did not change
anything, then it will fail, right? If you changed something, it is new
version.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-07-05 6:27 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 6:46 [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-04 6:46 ` [RESEND PATCH v6 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-13 12:26 ` Emil Renner Berthing
2023-07-14 6:24 ` Xingyu Wu
2023-07-04 6:46 ` [RESEND PATCH v6 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-04 22:21 ` Conor Dooley
2023-07-05 6:29 ` Krzysztof Kozlowski
2023-07-13 12:31 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-07-04 22:23 ` Conor Dooley
2023-07-07 7:45 ` Xingyu Wu
2023-07-13 12:34 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-13 12:37 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-04 22:25 ` Conor Dooley
2023-07-12 3:24 ` Hal Feng
2023-07-13 13:15 ` Emil Renner Berthing
2023-07-14 8:01 ` Xingyu Wu
2023-07-14 9:36 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-07-13 13:21 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
2023-07-13 13:24 ` Emil Renner Berthing
2023-07-04 22:29 ` [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Conor Dooley
2023-07-12 16:09 ` Conor Dooley
2023-07-05 6:27 ` Krzysztof Kozlowski [this message]
2023-07-07 7:41 ` Xingyu Wu
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