Re: [PATCH net-next 09/12] gpio: tc956x: add TC956x/QPS615 support

Alex Elder
2026-05-06T20:25:59Z

On 5/6/26 2:43 PM, Andrew Lunn wrote:
>>> ----------------------------------
>>> | Host |
>>> ------+...+----------+........+---
>>> |i2c| | PCIe |
>>> ----------------+...+----------+........+------
>>> | TC956x |I2C| |upstream| |
>>> | ----- --+--------+--- |
>>> | ----- ------ ------- | PCIe switch | |
>>> | |SPI| |GPIO| |reset| | | |
>>> | ----- ------ |clock| | DS3 DS2 DS1 | |
>>> | ------- ---++--++--++-- |
>>> | ----- ------ downstream// \\ \\ | downstream
>>> | |MCU| |SRAM| /==========/ \\ \===== PCIe port 1
>>> | ----- ------ //PCIe port 3 \\ |
>>> | || \======= downstream
>>> | ----+-----------++-----------+---- | PCIe port 2
>>> | | M | internal PCIe endpoint | M | |
>>> | | S |------------------------| S | ------ |
>>> | | I | PCIe | | PCIe | I | |UART| |
>>> | | G |function 0| |function 1| G | ------ |
>>> | | E |----++----| |----++----| E | |
>>> | | N | eMAC 0 | | eMAC 1 | N | |
>>> --------+.......+------+.....+-----------------
>>> |USXGMII| |SGMII|
>>> --+.......+-- --+.....+--
>>> | ARQ113C | | QEP8121 |
>>> | PHY | | PHY |
>>> ------------- -----------
>>>
>
>
>> Because the internal endpoint won't operate until the PCIe
>> power controller has enabled power, this GPIO driver and
>> the PCIe power control driver won't interfere with each
>> other's access to the shared registers.
>
> What i find interesting is that there are two GPIOs, and two external
> downstream PCIe ports. A naive way of looking at this is that each
> external PCIe port has one GPIO. And the internal PCIe port does not
> have one. Hence the internal port might well work without any
> additional setup? That was my thinking.

I see what you're saying. I don't actually know what effect those
two reset signals have on the internal PCIe endpoint or its port.

Here is what the power control driver does:
- asserts those two reset signals (via direct register writes)
- for every port on the switch:
- disables the port (which programs a sequence of values to
specific addresses)
- sets several PCIe configuration options
- l0s_entry_delay
- l1_entry_delay
- TX amplitude
- NFTS
- disable DFE
- Finally deasserts those two reset signals again.

And "every port on the switch" is:
- USP (upstream port)
- DSP 1, 2, 3 (downstream ports, including the embedded one)
- Ethernet (which tells me maybe we need to update that driver
to support two eMACs?)

The whole point of this power control driver is that it doesn't
actually power up the PCIe switch at all until *after* this
configuration step is complete. So I believe the internal
endpoint and its two functions aren't powered until after the
power control driver finishes probing.

The GPIO controller is obviously alive when the power control
driver runs though.

> But you are saying it is not as simple as this, and two GPIOs affect
> three ports? Do you have any idea what they actually do?

To be honest, for the most part we haven't looked closely at
the PCIe power control driver--though it's relatively simple
and I understand how the code works...

So I don't know the answer, but I expect with some work I
might be able to find out.

To be clear, the reason you're asking is that you're suggesting
we might want to model the GPIO controller differently, correct?

I.e., model it as *not* associated with the embedded PCIe
functions. Then we need to think about what its parent device
would be (the power control device, which I think somehow
duplicates the switch device?).

-Alex

> Andrew