From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB5C7C7619A for ; Wed, 12 Apr 2023 02:12:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbjDLCM4 (ORCPT ); Tue, 11 Apr 2023 22:12:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229482AbjDLCMz (ORCPT ); Tue, 11 Apr 2023 22:12:55 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F89649F1; Tue, 11 Apr 2023 19:12:54 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6CE4324E053; Wed, 12 Apr 2023 10:12:46 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 12 Apr 2023 10:12:46 +0800 Received: from [192.168.125.87] (113.72.145.176) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 12 Apr 2023 10:12:45 +0800 Message-ID: <91855baa-88cb-96b1-d571-4881ea6d24c8@starfivetech.com> Date: Wed, 12 Apr 2023 10:12:44 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v7 00/22] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC To: Conor Dooley CC: , , , Conor Dooley , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou , Ben Dooks , Daniel Lezcano , Thomas Gleixner , "Marc Zyngier" , Emil Renner Berthing , References: <20230401111934.130844-1-hal.feng@starfivetech.com> <20230405-wharf-rejoin-5222e5958611@spud> <20230411-gleaming-parasail-34e2b7c3de2e@spud> Content-Language: en-US From: Hal Feng In-Reply-To: <20230411-gleaming-parasail-34e2b7c3de2e@spud> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 11 Apr 2023 22:35:04 +0100, Conor Dooley wrote: > On Thu, Apr 06, 2023 at 03:03:14PM +0800, Hal Feng wrote: >> On Wed, 5 Apr 2023 22:30:45 +0100, Conor Dooley wrote: > >> > Hal, can you get your folks to resend whatever dts bits that are now >> > applicable? IOW, the dt-bindings for the entries are in a for-next >> > branch for some subsystem. >> >> Of course. As far as I know, these nodes include trng / pmu / mmc / qspi. > > Just FYI, you can get the lads to resend them whenever, but it's too > late for v6.4 now. I knew it later that, trng depends on stg clock dt-bindings, mmc depends on syscon dt-bindings which will be merged into the pll clock driver, the dt-bindings of qspi need to be fixed due to the actual number of clock inputs it need is 3. Walker plans to resend the pmu bits these days, but sorry to hear that it's too late now. Best regards, Hal