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From: Michal Simek <michal.simek@amd.com>
To: sashiko-reviews@lists.linux.dev
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema
Date: Wed, 8 Jul 2026 13:49:03 +0200	[thread overview]
Message-ID: <9201b249-e6e2-43f1-b4db-f10f874b74b0@amd.com> (raw)
In-Reply-To: <20260708073722.F029C1F000E9@smtp.kernel.org>



On 7/8/26 09:37, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Medium] The regex pattern for `mio_clk` in `clock-names` contains a logic error that fails to correctly constrain the index to 00-77.
> - [Low] The example in `xlnx,versal-clk.yaml` fails schema validation because it wraps a `versal-clk` clock controller in a `zynqmp-firmware` node.
> --
> 
> --- Patch [3]: [PATCH v4 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema ---
> commit 718990212b2e54a25ccb16a23d741b1b1a896e2d
> Author: Michal Simek <michal.simek@amd.com>
> 
> dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema
> 
> The ZynqMP clock controller binding shares only #clock-cells with the
> Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema.
> Also remove "(Optional clock)" from clock description because it is visible
> from schema itself.
> 
>> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
>> index b1623c2ab0f69..12d060c39bfc4 100644
>> --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
>> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> [ ... ]
>>   examples:
>>     - |
>>       firmware {
>>         zynqmp_firmware: zynqmp-firmware {
>>           compatible = "xlnx,zynqmp-firmware";
>>           method = "smc";
>>           versal_clk: clock-controller {
>>             #clock-cells = <1>;
>>             compatible = "xlnx,versal-clk";
> 
> [Severity: Low]
> Will this example now fail make dt_binding_check validation?
> 
> Because xlnx,zynqmp-firmware.yaml is modified in this patch to add an allOf
> rule requiring the clock-controller child of zynqmp-firmware to use
> compatible = "xlnx,zynqmp-clk", this xlnx,versal-clk node inside a
> zynqmp-firmware example seems like it will trigger a schema validation error.
> 

that fix is in 4/5. I will move it to 3/5.

>>             clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>;
>>             clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk";
>>           };
>>         };
>>       };
> [ ... ]
>> diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
>> new file mode 100644
>> index 0000000000000..c64550471581c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
> [ ... ]
>> +  clock-names:
>> +    minItems: 5
>> +    items:
>> +      - const: pss_ref_clk
>> +      - const: video_clk
>> +      - const: pss_alt_ref_clk
>> +      - const: aux_ref_clk
>> +      - const: gt_crx_ref_clk
>> +      - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$"
> 
> [Severity: Medium]
> Does this pattern correctly constrain the clock index to 00-77?
> 
> By combining the + quantifier with .*, this regex allows strings like
> "mio_clk100" to validate, since the "10" matches the capturing group and the
> remaining "0" matches ".*". Could this be corrected to avoid permitting out of
> bounds values?

That's correct but that's just fix in 2/5 where +.* was there before too.
It means yes it is possible that user will pass mio_clk100 and it won't be 
noticed. But I don't have any reference that anybody is really using it and
I don't want to break them.

Thanks,
Michal

  reply	other threads:[~2026-07-08 11:49 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08  7:18 [PATCH v4 0/5] clock: versal-clk: Fix Versal NET clock binding and switch to CCF Michal Simek
2026-07-08  7:18 ` [PATCH v4 1/5] dt-bindings: firmware: xilinx: Add missing example for ZynqMP Michal Simek
2026-07-08  7:27   ` sashiko-bot
2026-07-08  7:18 ` [PATCH v4 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern Michal Simek
2026-07-08  7:32   ` sashiko-bot
2026-07-08 10:59     ` Michal Simek
2026-07-08  7:18 ` [PATCH v4 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema Michal Simek
2026-07-08  7:37   ` sashiko-bot
2026-07-08 11:49     ` Michal Simek [this message]
2026-07-08  9:06   ` Rob Herring (Arm)
2026-07-08  7:18 ` [PATCH v4 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation Michal Simek
2026-07-08  7:18 ` [PATCH v4 5/5] arm64: versal-net: Switch Versal NET to firmware clock interface Michal Simek
2026-07-08  7:42   ` sashiko-bot
2026-07-08 11:51     ` Michal Simek

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