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[83.9.3.23]) by smtp.gmail.com with ESMTPSA id b7-20020ac24107000000b004e9b307d2c8sm2656277lfi.238.2023.04.11.12.50.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Apr 2023 12:50:47 -0700 (PDT) Message-ID: <923fb538-a28a-2172-569f-b58349157d49@linaro.org> Date: Tue, 11 Apr 2023 21:50:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v3 7/7] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Content-Language: en-US To: Bartosz Golaszewski Cc: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Will Deacon , Robin Murphy , Joerg Roedel , Catalin Marinas , Arnd Bergmann , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski References: <20230411125910.401075-1-brgl@bgdev.pl> <20230411125910.401075-8-brgl@bgdev.pl> <6c75d434-bb5d-278f-a125-d096fd6b387d@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11.04.2023 16:41, Bartosz Golaszewski wrote: > On Tue, Apr 11, 2023 at 3:16 PM Konrad Dybcio wrote: >> >> >> >> On 11.04.2023 14:59, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski >>> >>> Add the Adreno GPU IOMMU for sa8775p-based platforms. >>> >>> Signed-off-by: Bartosz Golaszewski >>> --- >>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ >>> 1 file changed, 37 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> index 191b510b5a1a..11f3d80dd869 100644 >>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> @@ -7,6 +7,7 @@ >>> #include >>> #include >>> #include >>> +#include >>> #include >>> #include >>> #include >>> @@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 { >>> #power-domain-cells = <1>; >>> }; >>> >>> + adreno_smmu: iommu@3da0000 { >>> + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", >>> + "arm,mmu-500"; >> Err.. does it even boot like this? You dropped the qcom,smmu-500 compatible >> which means it's getting bound to the generic SMMU driver (without >> QC quirks). If that was a mistake, you should have had all 4 >> >> "qcom,sa8775p-smmu-500", qcom,adreno-smmu, "qcom,smmu-500", "arm,mmu-500" >> >> Without falling into the qc-specific codepaths, the Adreno compat does >> nothing. >> > > I did that initially, then noticed dtbs_check fails because the > existing adreno GPUs implementing "arm,smmu-500" expect three > compatibles like in this commit. I did that and the driver still > probed the same so I assumed all's good. You're right of course, the > adreno impl is not being assigned without "qcom,smmu-500". Are the > bindings wrong in this case and should it be something like the > following? > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index d966dc65ce10..cd1b052a7242 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -84,6 +84,7 @@ properties: > - qcom,sm8150-smmu-500 > - qcom,sm8250-smmu-500 > - const: qcom,adreno-smmu > + - const: qcom,smmu-500 > - const: arm,mmu-500 > - description: Qcom Adreno GPUs implementing "arm,smmu-v2" > items: > > Bartosz Check https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/commit/?h=for-joerg/arm-smmu/bindings&id=5c3686616b1840b3143b227eb58fb1c1621d204e Konrad > >> Konrad >>> + reg = <0x0 0x03da0000 0x0 0x20000>; >>> + #iommu-cells = <2>; >>> + #global-interrupts = <2>; >>> + dma-coherent; >>> + power-domains = <&gpucc GPU_CC_CX_GDSC>; >>> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >>> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >>> + <&gpucc GPU_CC_AHB_CLK>, >>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >>> + <&gpucc GPU_CC_CX_GMU_CLK>, >>> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >>> + <&gpucc GPU_CC_HUB_AON_CLK>; >>> + clock-names = "gcc_gpu_memnoc_gfx_clk", >>> + "gcc_gpu_snoc_dvm_gfx_clk", >>> + "gpu_cc_ahb_clk", >>> + "gpu_cc_hlos1_vote_gpu_smmu_clk", >>> + "gpu_cc_cx_gmu_clk", >>> + "gpu_cc_hub_cx_int_clk", >>> + "gpu_cc_hub_aon_clk"; >>> + interrupts = , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + ; >>> + }; >>> + >>> pdc: interrupt-controller@b220000 { >>> compatible = "qcom,sa8775p-pdc", "qcom,pdc"; >>> reg = <0x0 0x0b220000 0x0 0x30000>,