[PATCH v5 0/4] Fix Versa3 clock mapping

[PATCH v5 0/4] Fix Versa3 clock mapping

[Biju Das]

According to Table 3. ("Output Source") in the 5P35023 datasheet,
the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3,
4=DIFF1, 5=DIFF2. But the code uses inverse.

This patch series aims to document clock-output-names in bindings and
fix the mapping in driver.

Also added a fix for 64 by 64 division.

v4->v5:
 * Added description for #clock-cells property for clock mapping.
 * Updated commit header and description to reflect this change.
 * Dropped fixes tag.
 * Retained Ack tag from Conor and Krzysztof as it is trivial change.
v3->v4:
 * Dropped clock-output-names as there is no validation for it and people
   can get it wrong.
 * Updated commit header, description and example to reflect this change
 * Retained Ack tag from Conor and Krzysztof as it is trivial change.
 * Used clamped value for rate calculation in vc3_pll_round_rate().
v2->v3:
 * Dropped dts patch and added fix for 64 byte division to this patch
   series.
 * Added Rb tag from Geert for patch#3
 * Added a patch to make vc3_clk_mux enum values depend on vc3_clk enum
   values.
v1->v2:
 * Updated binding commit description to make it clear it fixes
   "assigned-clock-rates" in the example based on 5P35023 datasheet.

Biju Das (4):
  dt-bindings: clock: versaclock3: Add description for #clock-cells
    property
  clk: vc3: Fix 64 by 64 division
  clk: vc3: Fix output clock mapping
  clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values

 .../bindings/clock/renesas,5p35023.yaml       | 11 ++-
 drivers/clk/clk-versaclock3.c                 | 81 +++++++++----------
 2 files changed, 47 insertions(+), 45 deletions(-)

-- 
2.25.1

[PATCH v5 1/4] dt-bindings: clock: versaclock3: Add description for #clock-cells property

[Biju Das]

Add description for "#clock-cells" property to map indexes to the clock
output in the Table 3. ("Output Source") in the 5P35023 datasheet
(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}. Also update the "assigned-clock-rates"
in the example.

While at it, replace clocks phandle in the example from x1_x2->x1 as
X2 is a different 32768 kHz crystal.

Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v4->v5:
 * Added description for "#clock-cells" property to map indexes to the
   clock output.
 * Updated commit header and description to reflect this change.
 * Dropped fixes tag.
 * Retained Ack tag from Conor and Krzysztof as it is trivial change.
v3->v4:
 * Dropped clock-output-names as there is no validation for it and people
   can get it wrong.
 * Updated commit header, description and example to reflect this change
 * Retained Ack tag from Conor and Krzysztof as it is trivial change.
v2->v3:
 * No change.
v1->v2:
 * Updated commit description to make it clear it fixes
   "assigned-clock-rates" in the example based on 5P35023 datasheet.
---
 .../devicetree/bindings/clock/renesas,5p35023.yaml    | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
index 839648e753d4..42b6f80613f3 100644
--- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
@@ -37,6 +37,9 @@ properties:
     maxItems: 1
 
   '#clock-cells':
+    description:
+      The index in the assigned-clocks is mapped to the output clock as below
+      0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
     const: 1
 
   clocks:
@@ -68,7 +71,7 @@ examples:
             reg = <0x68>;
             #clock-cells = <1>;
 
-            clocks = <&x1_x2>;
+            clocks = <&x1>;
 
             renesas,settings = [
                 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
@@ -79,8 +82,8 @@ examples:
             assigned-clocks = <&versa3 0>, <&versa3 1>,
                               <&versa3 2>, <&versa3 3>,
                               <&versa3 4>, <&versa3 5>;
-            assigned-clock-rates = <12288000>, <25000000>,
-                                   <12000000>, <11289600>,
-                                   <11289600>, <24000000>;
+            assigned-clock-rates = <24000000>, <11289600>,
+                                   <11289600>, <12000000>,
+                                   <25000000>, <12288000>;
         };
     };
-- 
2.25.1

RE: [PATCH v5 0/4] Fix Versa3 clock mapping

[Biju Das]

Hi All,

Gentle ping.

Cheers,
Biju

> Subject: [PATCH v5 0/4] Fix Versa3 clock mapping
> 
> According to Table 3. ("Output Source") in the 5P35023 datasheet, the
> output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1,
> 5=DIFF2. But the code uses inverse.
> 
> This patch series aims to document clock-output-names in bindings and fix
> the mapping in driver.
> 
> Also added a fix for 64 by 64 division.
> 
> v4->v5:
>  * Added description for #clock-cells property for clock mapping.
>  * Updated commit header and description to reflect this change.
>  * Dropped fixes tag.
>  * Retained Ack tag from Conor and Krzysztof as it is trivial change.
> v3->v4:
>  * Dropped clock-output-names as there is no validation for it and people
>    can get it wrong.
>  * Updated commit header, description and example to reflect this change
>  * Retained Ack tag from Conor and Krzysztof as it is trivial change.
>  * Used clamped value for rate calculation in vc3_pll_round_rate().
> v2->v3:
>  * Dropped dts patch and added fix for 64 byte division to this patch
>    series.
>  * Added Rb tag from Geert for patch#3
>  * Added a patch to make vc3_clk_mux enum values depend on vc3_clk enum
>    values.
> v1->v2:
>  * Updated binding commit description to make it clear it fixes
>    "assigned-clock-rates" in the example based on 5P35023 datasheet.
> 
> Biju Das (4):
>   dt-bindings: clock: versaclock3: Add description for #clock-cells
>     property
>   clk: vc3: Fix 64 by 64 division
>   clk: vc3: Fix output clock mapping
>   clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values
> 
>  .../bindings/clock/renesas,5p35023.yaml       | 11 ++-
>  drivers/clk/clk-versaclock3.c                 | 81 +++++++++----------
>  2 files changed, 47 insertions(+), 45 deletions(-)
> 
> --
> 2.25.1

Re: [PATCH v5 1/4] dt-bindings: clock: versaclock3: Add description for #clock-cells property

[Geert Uytterhoeven]

On Thu, Aug 24, 2023 at 12:48 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add description for "#clock-cells" property to map indexes to the clock
> output in the Table 3. ("Output Source") in the 5P35023 datasheet
> (ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}. Also update the "assigned-clock-rates"
> in the example.
>
> While at it, replace clocks phandle in the example from x1_x2->x1 as
> X2 is a different 32768 kHz crystal.
>
> Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> v4->v5:
>  * Added description for "#clock-cells" property to map indexes to the
>    clock output.
>  * Updated commit header and description to reflect this change.
>  * Dropped fixes tag.
>  * Retained Ack tag from Conor and Krzysztof as it is trivial change.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 0/4] Fix Versa3 clock mapping

[Geert Uytterhoeven]

Hi Stephen,

On Wed, Sep 6, 2023 at 11:09 PM Stephen Boyd <sboyd@kernel.org> wrote:
> Quoting Biju Das (2023-09-06 03:05:18)
> > Gentle ping.
>
> I'm waiting for Geert to review. I think we need to merge this soon to
> fix problems introduced this merge window?

Sorry, I didn't know you were waiting on my reviews (FWIW, I'm not
the maintainer... Oh, scripts/get_maintainer.pl disagrees, due to
the overzealous "renesas," wildcard, now matching all non-SoC devices
produced by companies acquired by Renesas recently :-(

I did review "[PATCH v5 3/4] clk: vc3: Fix output clock mapping" before,
which is the one I care about the most, as it is a hard dependency for
DT changes to be queued...

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 1/4] dt-bindings: clock: versaclock3: Add description for #clock-cells property

[Stephen Boyd]

Quoting Biju Das (2023-08-24 03:48:09)
> Add description for "#clock-cells" property to map indexes to the clock
> output in the Table 3. ("Output Source") in the 5P35023 datasheet
> (ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}. Also update the "assigned-clock-rates"
> in the example.
> 
> While at it, replace clocks phandle in the example from x1_x2->x1 as
> X2 is a different 32768 kHz crystal.
> 
> Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Applied to clk-fixes