From: Marc Zyngier <maz@kernel.org>
To: Samuel Holland <samuel@sholland.org>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Prabhakar <prabhakar.csengg@gmail.com>,
Sagar Kadam <sagar.kadam@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>, Guo Ren <guoren@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow
Date: Fri, 01 Jul 2022 15:28:48 +0100 [thread overview]
Message-ID: <92a45bf04cfe140c7605559fa3d8f4eb@kernel.org> (raw)
In-Reply-To: <20220630100241.35233-1-samuel@sholland.org>
On 2022-06-30 11:02, Samuel Holland wrote:
> This patch series adds PLIC support for Renesas RZ/Five SoC.
>
> Since the T-HEAD C900 PLIC has the same behavior, it also applies the
> fix for that variant.
>
> This series is an update of v2 of the RZ/Five series[0], and replaces
> the separate T-HEAD series[1].
>
> [0]:
> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> [1]:
> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/
>
> Changes in v3:
> - Add a more detailed explanation for why #interrupt-cells differs
> - Add andestech,nceplic100 as a fallback compatible
> - Separate the conditional part of the binding into two blocks (one
> for
> the PLIC implementation and the other for the SoC integration)
> - Use a quirk bit for selecting the flow instead of a variant ID
> - Use the andestech,nceplic100 compatible to select the new behavior
> - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
> always gets called
> - Do not set the handler name, as RISC-V selects
> GENERIC_IRQ_SHOW_LEVEL
> - Use the same name for plic_edge_chip as plic_chip
>
> Changes in v2:
> - Fixed review comments pointed by Marc and Krzysztof.
>
> Changes in v1:
> - Fixed review comments pointed by Rob and Geert.
> - Changed implementation for EDGE interrupt handling on Renesas
> RZ/Five
> SoC.
>
> Lad Prabhakar (2):
> dt-bindings: interrupt-controller: sifive,plic: Document Renesas
> RZ/Five SoC
> irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
>
> Samuel Holland (2):
> dt-bindings: interrupt-controller: Require trigger type for T-HEAD
> PLIC
> irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
>
> .../sifive,plic-1.0.0.yaml | 65 +++++++++++++--
> drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++--
> 2 files changed, 135 insertions(+), 10 deletions(-)
I'm going to provisionally queue this into -next so that it
can get some testing. I'd still want the DT changes to be
Ack'ed before the next merge window though.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2022-07-01 14:33 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 10:02 [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Samuel Holland
2022-06-30 10:02 ` [PATCH v3 1/4] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Samuel Holland
2022-06-30 10:02 ` [PATCH v3 2/4] irqchip/sifive-plic: Add support for " Samuel Holland
2022-06-30 10:02 ` [PATCH v3 3/4] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC Samuel Holland
2022-06-30 10:02 ` [PATCH v3 4/4] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling Samuel Holland
2022-06-30 23:43 ` Guo Ren
2022-07-01 14:28 ` Marc Zyngier [this message]
2022-07-13 3:19 ` [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow Palmer Dabbelt
2022-07-13 7:00 ` Conor.Dooley
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