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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id c16-20020a056512105000b0050d1a0e7129sm1659686lfb.291.2023.12.14.10.18.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Dec 2023 10:18:22 -0800 (PST) Message-ID: <92e9039b-a0e3-4f93-aaa8-226ef9e8b613@linaro.org> Date: Thu, 14 Dec 2023 19:18:19 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/8] arm64: dts: qcom: ipq5332: add support for the NSSCC Content-Language: en-US To: Kathiravan Thirumoorthy , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com> <20231211-ipq5332-nsscc-v3-7-ad13bef9b137@quicinc.com> <8cc2a8ec-632e-4e3b-b13b-d1523a61c136@quicinc.com> From: Konrad Dybcio In-Reply-To: <8cc2a8ec-632e-4e3b-b13b-d1523a61c136@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Level: * On 12/11/23 14:28, Kathiravan Thirumoorthy wrote: > > > On 12/11/2023 4:02 PM, Konrad Dybcio wrote: >> On 11.12.2023 04:37, Kathiravan Thirumoorthy wrote: >>> Describe the NSS clock controller node and it's relevant external >>> clocks. >>> >>> Signed-off-by: Kathiravan Thirumoorthy >>> --- >>>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ >>>   1 file changed, 28 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >>> index 42e2e48b2bc3..a1504f6c40c1 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >>> @@ -15,6 +15,18 @@ / { >>>       #size-cells = <2>; >>>       clocks { >>> +        cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { >>> +            compatible = "fixed-clock"; >>> +            clock-frequency = <200000000>; >>> +            #clock-cells = <0>; >>> +        }; >>> + >>> +        cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { >>> +            compatible = "fixed-clock"; >>> +            clock-frequency = <300000000>; >>> +            #clock-cells = <0>; >>> +        }; >>> + >>>           sleep_clk: sleep-clk { >>>               compatible = "fixed-clock"; >>>               #clock-cells = <0>; >>> @@ -473,6 +485,22 @@ frame@b128000 { >>>                   status = "disabled"; >>>               }; >>>           }; >>> + >>> +        nsscc: clock-controller@39b00000{ >> Missing space between the opening curly brace > > My bad :( will fix it in next spin. > >> >>> +            compatible = "qcom,ipq5332-nsscc"; >>> +            reg = <0x39b00000 0x80000>; >> the regmap_config in the clk driver has .max_register = 0x800, is this >> correct? > > As per the memory map, 512KB is the size of this block. However the last register in that region is at the offset 0x800. Shall I update the max_register also to 512KB to keep it consistency? No, it's fine, I just wanted to know if it's intentional :) Thanks! Konrad