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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id yk13sm2740971ejb.200.2022.02.08.09.01.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Feb 2022 09:01:52 -0800 (PST) Message-ID: <9303ca0e-2a83-3c3e-0892-c74a820562a9@canonical.com> Date: Tue, 8 Feb 2022 18:01:51 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 2/5] dt-bindings: arm: ti: Add bindings for AM625 SoC Content-Language: en-US To: Vignesh Raghavendra , Nishanth Menon , Tero Kristo , Rob Herring , Santosh Shilimkar Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220208131827.1430086-1-vigneshr@ti.com> <20220208131827.1430086-3-vigneshr@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20220208131827.1430086-3-vigneshr@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/02/2022 14:18, Vignesh Raghavendra wrote: > From: Nishanth Menon > > The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC > architecture platform, providing ultra-low-power modes, dual display, > multi-sensor edge compute, security and other BOM-saving integration. > The AM62 SoC targets broad market to enable applications such as > Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building > Automation, Appliances and more. > > Some highlights of this SoC are: > > * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. > Pin-to-pin compatible options for single and quad core are available. > * Cortex-M4F for general-purpose or safety usage. > * Dual display support, providing 24-bit RBG parallel interface and > OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display > resolution. > * Selectable GPUsupport, up to 8GFLOPS, providing better user experience > in 3D graphic display case and Android. > * PRU(Programmable Realtime Unit) support for customized programmable > interfaces/IOs. > * Integrated Giga-bit Ethernet switch supporting up to a total of two > external ports (TSN capable). > * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for > NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, > 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. > * Dedicated Centralized System Controller for Security, Power, and > Resource Management. > * Multiple low power modes support, ex: Deep sleep,Standby, MCU-only, > enabling battery powered system design. > > AM625 is the first device of the family. Add DT bindings for the same. Don't paste the same huge commit description in several commits. > > More details can be found in the Technical Reference Manual: > https://www.ti.com/lit/pdf/spruiv7 > > Signed-off-by: Nishanth Menon > Signed-off-by: Vignesh Raghavendra > --- > Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml > index b03c10fa2e7a..64f3db3ea9dd 100644 > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml > @@ -53,6 +53,12 @@ properties: > - ti,am642-sk > - const: ti,am642 > > + - description: K3 AM625 SoC > + items: > + - enum: > + - ti,am625-sk > + - const: ti,am625 Why keeping it not alphabetically sorted? What sorting did you choose? > + > - description: K3 J721s2 SoC > items: > - enum: Best regards, Krzysztof