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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bd4f4c23feasm200169966b.14.2026.05.15.02.10.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 02:10:30 -0700 (PDT) Message-ID: <934d6876-3c83-43de-b155-d435af4c3547@oss.qualcomm.com> Date: Fri, 15 May 2026 11:10:28 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes To: Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260513-eliza-dts-fix-debug-uart-and-more-support-v1-0-05814d24f4cf@oss.qualcomm.com> <20260513-eliza-dts-fix-debug-uart-and-more-support-v1-2-05814d24f4cf@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260513-eliza-dts-fix-debug-uart-and-more-support-v1-2-05814d24f4cf@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=D7Z37PRj c=1 sm=1 tr=0 ts=6a06e308 cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=olRgGBVlyjl6rEf_PyYA:9 a=QEXdDO2ut3YA:10 a=-aSRE8QhW-JAV6biHavz:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE1MDA5MSBTYWx0ZWRfXxXE3ycNfiIuy JH3jJ+htGm1r6UlYazjCjvEfmqnCvxNgeN4HEE0lwLGu+YvBmYilzUzH+MahjzPxwdif+OaETcn B6VbDnPokpXgSPhBbTal8NLsvo4erMuX8oX+f7kvjLNLufpfpeWwE4ucJEVZaSDETDAH7UmKg6k nIrULLk15ACFLesefosH4CHiZ4EFbBUV7NiUD70R1tW1r+Z3ksmHeSdae1VhJvudmpIhJhdu3xs q7sq49TMLanBGS7hbl66JfkDNC4aedXJEV4/vhW9s3nA0xEf1eF2rHX8mmtFgbFvfNO0MESYiHJ oZHVVIjvIV/AC5vC36bMmLyc4oQfFz46yEks7I0xHAR8PO9N1JMiHTvmHtKFztK54a7Yz6SMS0h HZwuo83YnhdKyRvHkoRolDC507JETbLamsUlgs9PVdlMl+gw4VMUpN8uD2EbM43TRAiiTH1JhMT XMlBiHlYAuMoYNbK1Rg== X-Proofpoint-ORIG-GUID: 5jgRxpfq730lzRplPpUf-RUM23lBQFPv X-Proofpoint-GUID: 5jgRxpfq730lzRplPpUf-RUM23lBQFPv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-15_02,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605150091 On 5/13/26 2:33 PM, Abel Vesa wrote: > Describe the missing Eliza SoC nodes for the QUPv3 WRAP1 and WRAP2 serial > engines, add the matching GPI DMA controllers, the SDHCI controllers and > the LLCC system cache controller. > > Also add the TLMM pinctrl states for the QUPv3 serial engines and the > SD card/eMMC interfaces, plus OPP tables for the SDHCI controllers. > > Signed-off-by: Abel Vesa > --- [...] > + gpi_dma1: dma-controller@a00000 { > + compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0x0 0x00a00000 0x0 0x60000>; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + #dma-cells = <3>; > + > + iommus = <&apps_smmu 0xb6 0x0>; > + dma-coherent; > + > + status = "disabled"; Let's keep the GPIs enabled [...] > + sdhc_1: mmc@f44000 { > + compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x00f44000 0x0 0x1000>, > + <0x0 0x00f45000 0x0 0x1000>, > + <0x0 0x00f48000 0x0 0x8000>; > + reg-names = "hc", > + "cqhci", > + "ice"; This should be a separate node > + > + interrupts = , > + ; > + interrupt-names = "hc_irq", > + "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", > + "core", > + "xo"; > + > + interconnects = <&aggre2_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "sdhc-ddr", > + "cpu-sdhc"; > + > + power-domains = <&rpmhpd RPMHPD_CX>; > + operating-points-v2 = <&sdhc1_opp_table>; > + > + qcom,dll-config = <0x000f44ec>; > + qcom,ddr-config = <0x80040868>; > + > + iommus = <&apps_smmu 0x520 0x0>; > + dma-coherent; > + > + bus-width = <4>; That's definitely 8 > + max-sd-hs-hz = <37500000>; This should be fixed in Eliza [...] > + max-sd-hs-hz = <37500000>; ditto for sdcc2 > + > + resets = <&gcc GCC_SDCC2_BCR>; > + > + status = "disabled"; > + > + sdhc2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; The clock plan says 100, but the SDC doc says 50. What does downstream set here? Konrad