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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Chris Packham <Chris.Packham@alliedtelesis.co.nz>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"will@kernel.org" <will@kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzysztof.kozlowski+dt@linaro.org" 
	<krzysztof.kozlowski+dt@linaro.org>,
	"gregory.clement@bootlin.com" <gregory.clement@bootlin.com>,
	"sebastian.hesselbarth@gmail.com"
	<sebastian.hesselbarth@gmail.com>,
	"kostap@marvell.com" <kostap@marvell.com>,
	"robert.marko@sartura.hr" <robert.marko@sartura.hr>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v5 1/2] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
Date: Tue, 10 May 2022 14:54:05 +0200	[thread overview]
Message-ID: <9365247a-8aa0-bad5-c619-9d5a984b17de@linaro.org> (raw)
In-Reply-To: <Ynpclx4z5z1Emx+b@lunn.ch>

On 10/05/2022 14:37, Andrew Lunn wrote:
> On Tue, May 10, 2022 at 09:08:08AM +0200, Krzysztof Kozlowski wrote:
>> On 10/05/2022 06:14, Chris Packham wrote:
>>>
>>> Based on the information I have (which isn't much) there is a ref_clk 
>>> input that is connected to a 25MHz oscillator and then I'm assuming 
>>> these are all generated from that with various dividers. 25MHz is the 
>>> only documented option.
>>>
>>> There doesn't appear to be any documented register where I can read out 
>>> the divider ratios. It might be nice I could have the fixed osc node and 
>>> have these 3 clocks derived with fixed divisors but I don't see any what 
>>> of achieving that.
>>
>>
>> OK, but where are the dividers? The ref_clk is outside of SoC, so should
>> be defined in board DTS (at least its rate). If the rest is in the SoC,
>> they are usually part of clock controller, because usually they belong
>> to some power domain or have some clock gating.
> 
> 25MHz is a 'magic value' in Ethernet, nearly everything is based
> around it. And remember this SoC is basically an Ethernet switch with
> a small CPU glued on one side. If you gated clocks derived from the
> 25MHz reference clock, probably part of your Ethernet switch stops
> working, which is the whole point of this SoC. So i doubt there are
> gates on the derived clocks. If there is any gating and power domains,
> it is generally at a different level. You can power down individual
> ports of the Ethernet switch. But generally, there is one bit in a
> register somewhere to do that, and you don't have direct control over
> clocks and regulators etc.

The 25 MHz input clock I understand, it was about other clocks, like
spi, axi and core. These clearly look like part of SoC, so defining them
with a "stubs" (uncontrollable fixed-clock) is not the best way of
modelling an SoC. Although maybe this SoC does not have a proper clock
controller and even SPI and AXI clocks are always on?


Best regards,
Krzysztof

  reply	other threads:[~2022-05-10 12:54 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04  4:46 [PATCH v5 0/2] arm64: mvebu: Support for Marvell 98DX2530 (and variants) Chris Packham
2022-05-04  4:46 ` [PATCH v5 1/2] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Chris Packham
2022-05-05  9:19   ` Krzysztof Kozlowski
2022-05-10  4:14     ` Chris Packham
2022-05-10  7:08       ` Krzysztof Kozlowski
2022-05-10 12:37         ` Andrew Lunn
2022-05-10 12:54           ` Krzysztof Kozlowski [this message]
2022-05-10 21:51     ` Chris Packham
2022-05-10 22:00       ` Chris Packham
2022-05-04  4:46 ` [PATCH v5 2/2] arm64: marvell: enable the 98DX2530 pinctrl driver Chris Packham
2022-05-11 16:10 ` [PATCH v5 1/2] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Vadym Kochan
2022-05-11 16:20   ` Andrew Lunn
2022-05-11 22:59     ` Chris Packham
2022-05-12  0:39       ` Andrew Lunn
2022-05-12  6:57         ` [EXT] " Elad Nachman
2022-05-12 12:47           ` Andrew Lunn
2022-05-12 21:19             ` Chris Packham

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