From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5520F14658B; Mon, 13 May 2024 06:38:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715582326; cv=none; b=RCMi0lkaEKJqJGHaDGe5mCOqSgCEMtXl+Oza48ZW8+9XwFCLjl014RjpLrMfTMqrPX7X1OaI+kU5a0D0FegaxsbS1v3ElzFZivj7u2GXABq8sP05pFgv5Vi2PpP65/1YTzKtKYYTW4vYS1hkZtva5r22iqN31Yc0sXMSwLt8R9I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715582326; c=relaxed/simple; bh=rheX3UDLWx2TrGDc2WgD/M6QRBNEUGJmYCKleNbGYx8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=iS05l6fjIFsUHkN/VlUF/sYlFkPP2US2Th0gGkqZYveMydv/kH1zDgbUQw4N1kF//ifiFK3gdNloStZuqv2LpO8KgQroIGxffIbe0vwYvMPm+YatcD/QsVV6j4xDpp1ZsDO0uVpxTvs8rL3l9MUQgkve2vWBEf5QGJd/kucFTCs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VD284AOp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VD284AOp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51529C113CC; Mon, 13 May 2024 06:38:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715582325; bh=rheX3UDLWx2TrGDc2WgD/M6QRBNEUGJmYCKleNbGYx8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=VD284AOpyhEN5r1wOAV4ARcCs40eM38v1f3mQ6sLZ7oOgtcy1nuXYTfx1PBNN805/ iWQcitKNgX/gIz4u4gVX1rpjW2VIVhVz/aLuBX6WpUfWfg8njSTchd2QTmEwQG7uCR 0iK37aDvz8+KWnuE7iyGE8zxrky/KQ/cDJfW+A1L32M+w9TYt0kP+ML+AHupiTipTw egYsbP1vEIb+8ygIgPZjVoZsma1uwsb0JLxSSogtjG+hhdwRlOZYeifw0V9lEiEXVQ h6i8H5mXGf39PQV03JAhSVBD69iJSwhcRB3YaKlanKqDxrnd4PsJzxbjiRy81yGXuu CKHG2MOWE5ECQ== Message-ID: <93690c52-7da7-4fee-9b58-6087b3fb1d71@kernel.org> Date: Mon, 13 May 2024 08:38:38 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] Add write DP phyd register from parse dts To: Liankun Yang , chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, chunfeng.yun@mediatek.com, vkoul@kernel.org, kishon@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, jitao.shi@mediatek.com, mac.shen@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20240510110523.12524-1-liankun.yang@mediatek.com> <20240510110523.12524-2-liankun.yang@mediatek.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/05/2024 13:04, Liankun Yang wrote: > During the testing phase, screen flickering is observed when > using displayport for screen casting. Relevant SSC register parameters > are set in dts to address the screen flickering issue effectively and > improve compatibility with different devices by adjusting the SSC gear. > > Obtaining the DPTX node, parsing the dts to obtain PHY register address > and value can adapt to settings of different manufacturers projects. > > Changeds in v2: > - Optimized method of writing to DP PHY register > https://patchwork.kernel.org/project/linux-mediatek/patch/ > 20240403040517.3279-1-liankun.yang@mediatek.com/ > > Signed-off-by: Liankun Yang > --- > drivers/phy/mediatek/phy-mtk-dp.c | 37 +++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c > index d7024a144335..ce78112d5938 100644 > --- a/drivers/phy/mediatek/phy-mtk-dp.c > +++ b/drivers/phy/mediatek/phy-mtk-dp.c > @@ -28,6 +28,10 @@ > #define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38) > #define DP_GLB_SW_RST_PHYD BIT(0) > > +#define MTK_DP_PHY_DIG_GLB_DA_REG_14 (PHY_OFFSET + 0xD8) > +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT GENMASK(15, 0) > +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT GENMASK(31, 16) > + > #define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) > #define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) > #define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) > @@ -78,10 +82,39 @@ > #define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ > XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) > > +#define SSC_SETTING "dp-ssc-setting" > +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR "ssc-delta-hbr" > + > struct mtk_dp_phy { > struct regmap *regs; > + struct device *dev; > }; > > +static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy) > +{ > + int ret; > + u32 read_value = 0, reg_mask = 0; > + struct device_node *ssc_node = NULL; > + > + ssc_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING); No, really. Node name can change. Best regards, Krzysztof