[PATCH v2 0/2] Add PHY-dp bindings

[PATCH v2 0/2] Add PHY-dp bindings

[Liankun Yang]

Update write DP phyd register and add phy-dp bindings.

Liankun Yang (2):
  Add write DP phyd register from parse dts
  Add dp PHY dt-bindings

 .../display/mediatek/mediatek.phy-dp.yaml     | 45 +++++++++++++++++++
 drivers/phy/mediatek/phy-mtk-dp.c             | 37 +++++++++++++++
 2 files changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml

-- 
2.18.0

[PATCH v2 1/2] Add write DP phyd register from parse dts

[Liankun Yang]

During the testing phase, screen flickering is observed when
using displayport for screen casting. Relevant SSC register parameters
are set in dts to address the screen flickering issue effectively and
improve compatibility with different devices by adjusting the SSC gear.

Obtaining the DPTX node, parsing the dts to obtain PHY register address
and value can adapt to settings of different manufacturers projects.

Changeds in v2:
- Optimized method of writing to DP PHY register
https://patchwork.kernel.org/project/linux-mediatek/patch/
20240403040517.3279-1-liankun.yang@mediatek.com/

Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
---
 drivers/phy/mediatek/phy-mtk-dp.c | 37 +++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index d7024a144335..ce78112d5938 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -28,6 +28,10 @@
 #define MTK_DP_PHY_DIG_SW_RST		(PHY_OFFSET + 0x38)
 #define DP_GLB_SW_RST_PHYD		BIT(0)
 
+#define MTK_DP_PHY_DIG_GLB_DA_REG_14	(PHY_OFFSET + 0xD8)
+#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT	GENMASK(15, 0)
+#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT	GENMASK(31, 16)
+
 #define MTK_DP_LANE0_DRIVING_PARAM_3		(PHY_OFFSET + 0x138)
 #define MTK_DP_LANE1_DRIVING_PARAM_3		(PHY_OFFSET + 0x238)
 #define MTK_DP_LANE2_DRIVING_PARAM_3		(PHY_OFFSET + 0x338)
@@ -78,10 +82,39 @@
 #define DRIVING_PARAM_8_DEFAULT	(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
 				 XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
 
+#define SSC_SETTING	"dp-ssc-setting"
+#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR	"ssc-delta-hbr"
+
 struct mtk_dp_phy {
 	struct regmap *regs;
+	struct device *dev;
 };
 
+static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy)
+{
+	int ret;
+	u32 read_value = 0, reg_mask = 0;
+	struct device_node *ssc_node = NULL;
+
+	ssc_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING);
+	if (!ssc_node) {
+		dev_err(&phy->dev, "SSC node is NULL\n");
+		return -ENODEV;
+	}
+
+	ret = of_property_read_u32(ssc_node, RG_XTP_GLB_TXPLL_SSC_DELTA_HBR, &read_value);
+	if (ret < 0 || !read_value) {
+		dev_err(&phy->dev, "Read SSC vlaue fail!\n");
+		return -EINVAL;
+	}
+	read_value |= read_value << 16;
+	reg_mask |= XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT;
+
+	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_GLB_DA_REG_14, reg_mask, read_value);
+
+	return 0;
+}
+
 static int mtk_dp_phy_init(struct phy *phy)
 {
 	struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
@@ -137,6 +170,8 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
 	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
 			   TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
 
+	mtk_dp_set_ssc_config(phy, dp_phy);
+
 	return 0;
 }
 
@@ -186,6 +221,8 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
 	if (!dev->of_node)
 		phy_create_lookup(phy, "dp", dev_name(dev));
 
+	dp_phy->dev = dev;
+
 	return 0;
 }
 
-- 
2.18.0

Re: [PATCH v2 1/2] Add write DP phyd register from parse dts

[Krzysztof Kozlowski]

On 10/05/2024 13:04, Liankun Yang wrote:
> During the testing phase, screen flickering is observed when
> using displayport for screen casting. Relevant SSC register parameters
> are set in dts to address the screen flickering issue effectively and
> improve compatibility with different devices by adjusting the SSC gear.
> 
> Obtaining the DPTX node, parsing the dts to obtain PHY register address
> and value can adapt to settings of different manufacturers projects.
> 
> Changeds in v2:
> - Optimized method of writing to DP PHY register
> https://patchwork.kernel.org/project/linux-mediatek/patch/
> 20240403040517.3279-1-liankun.yang@mediatek.com/
> 
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> ---
>  drivers/phy/mediatek/phy-mtk-dp.c | 37 +++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> index d7024a144335..ce78112d5938 100644
> --- a/drivers/phy/mediatek/phy-mtk-dp.c
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -28,6 +28,10 @@
>  #define MTK_DP_PHY_DIG_SW_RST		(PHY_OFFSET + 0x38)
>  #define DP_GLB_SW_RST_PHYD		BIT(0)
>  
> +#define MTK_DP_PHY_DIG_GLB_DA_REG_14	(PHY_OFFSET + 0xD8)
> +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT	GENMASK(15, 0)
> +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT	GENMASK(31, 16)
> +
>  #define MTK_DP_LANE0_DRIVING_PARAM_3		(PHY_OFFSET + 0x138)
>  #define MTK_DP_LANE1_DRIVING_PARAM_3		(PHY_OFFSET + 0x238)
>  #define MTK_DP_LANE2_DRIVING_PARAM_3		(PHY_OFFSET + 0x338)
> @@ -78,10 +82,39 @@
>  #define DRIVING_PARAM_8_DEFAULT	(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
>  				 XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
>  
> +#define SSC_SETTING	"dp-ssc-setting"
> +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR	"ssc-delta-hbr"
> +
>  struct mtk_dp_phy {
>  	struct regmap *regs;
> +	struct device *dev;
>  };
>  
> +static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy)
> +{
> +	int ret;
> +	u32 read_value = 0, reg_mask = 0;
> +	struct device_node *ssc_node = NULL;
> +
> +	ssc_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING);

No, really. Node name can change.

Best regards,
Krzysztof

Re: [PATCH v2 1/2] Add write DP phyd register from parse dts

[LIANKUN YANG (杨连坤)]

On Mon, 2024-05-13 at 08:38 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 10/05/2024 13:04, Liankun Yang wrote:
> > During the testing phase, screen flickering is observed when
> > using displayport for screen casting. Relevant SSC register
> parameters
> > are set in dts to address the screen flickering issue effectively
> and
> > improve compatibility with different devices by adjusting the SSC
> gear.
> > 
> > Obtaining the DPTX node, parsing the dts to obtain PHY register
> address
> > and value can adapt to settings of different manufacturers
> projects.
> > 
> > Changeds in v2:
> > - Optimized method of writing to DP PHY register
> > https://patchwork.kernel.org/project/linux-mediatek/patch/
> > 20240403040517.3279-1-liankun.yang@mediatek.com/
> > 
> > Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> > ---
> >  drivers/phy/mediatek/phy-mtk-dp.c | 37
> +++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/phy/mediatek/phy-mtk-dp.c
> b/drivers/phy/mediatek/phy-mtk-dp.c
> > index d7024a144335..ce78112d5938 100644
> > --- a/drivers/phy/mediatek/phy-mtk-dp.c
> > +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> > @@ -28,6 +28,10 @@
> >  #define MTK_DP_PHY_DIG_SW_RST(PHY_OFFSET + 0x38)
> >  #define DP_GLB_SW_RST_PHYDBIT(0)
> >  
> > +#define MTK_DP_PHY_DIG_GLB_DA_REG_14(PHY_OFFSET + 0xD8)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULTGENMASK(15, 0)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULTGENMASK(31, 16)
> > +
> >  #define MTK_DP_LANE0_DRIVING_PARAM_3(PHY_OFFSET + 0x138)
> >  #define MTK_DP_LANE1_DRIVING_PARAM_3(PHY_OFFSET + 0x238)
> >  #define MTK_DP_LANE2_DRIVING_PARAM_3(PHY_OFFSET + 0x338)
> > @@ -78,10 +82,39 @@
> >  #define DRIVING_PARAM_8_DEFAULT(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT
> | \
> >   XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> >  
> > +#define SSC_SETTING"dp-ssc-setting"
> > +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR"ssc-delta-hbr"
> > +
> >  struct mtk_dp_phy {
> >  struct regmap *regs;
> > +struct device *dev;
> >  };
> >  
> > +static int mtk_dp_set_ssc_config(struct phy *phy, struct
> mtk_dp_phy *dp_phy)
> > +{
> > +int ret;
> > +u32 read_value = 0, reg_mask = 0;
> > +struct device_node *ssc_node = NULL;
> > +
> > +ssc_node = of_find_node_by_name(dp_phy->dev->of_node,
> SSC_SETTING);
> 
> No, really. Node name can change.
> 
> Best regards,
> Krzysztof
> 

Thank you for your comment.
I will change the node name.

Best regards.
Liankun yang

Re: [PATCH v2 1/2] Add write DP phyd register from parse dts

[AngeloGioacchino Del Regno]

Il 10/05/24 13:04, Liankun Yang ha scritto:
> During the testing phase, screen flickering is observed when
> using displayport for screen casting. Relevant SSC register parameters
> are set in dts to address the screen flickering issue effectively and
> improve compatibility with different devices by adjusting the SSC gear.
> 
> Obtaining the DPTX node, parsing the dts to obtain PHY register address
> and value can adapt to settings of different manufacturers projects.
> 
> Changeds in v2:
> - Optimized method of writing to DP PHY register
> https://patchwork.kernel.org/project/linux-mediatek/patch/
> 20240403040517.3279-1-liankun.yang@mediatek.com/
> 
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>

There's no devicetree support in this driver - infact, it's being probed by
mtk-dp as a platform device.

You keep sending untested stuff. Fourth time in a row.

Please, TEST YOUR COMMITS upstream before sending!

Regards,
Angelo

> ---
>   drivers/phy/mediatek/phy-mtk-dp.c | 37 +++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> index d7024a144335..ce78112d5938 100644
> --- a/drivers/phy/mediatek/phy-mtk-dp.c
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -28,6 +28,10 @@
>   #define MTK_DP_PHY_DIG_SW_RST		(PHY_OFFSET + 0x38)
>   #define DP_GLB_SW_RST_PHYD		BIT(0)
>   
> +#define MTK_DP_PHY_DIG_GLB_DA_REG_14	(PHY_OFFSET + 0xD8)
> +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT	GENMASK(15, 0)
> +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT	GENMASK(31, 16)
> +
>   #define MTK_DP_LANE0_DRIVING_PARAM_3		(PHY_OFFSET + 0x138)
>   #define MTK_DP_LANE1_DRIVING_PARAM_3		(PHY_OFFSET + 0x238)
>   #define MTK_DP_LANE2_DRIVING_PARAM_3		(PHY_OFFSET + 0x338)
> @@ -78,10 +82,39 @@
>   #define DRIVING_PARAM_8_DEFAULT	(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
>   				 XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
>   
> +#define SSC_SETTING	"dp-ssc-setting"
> +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR	"ssc-delta-hbr"
> +
>   struct mtk_dp_phy {
>   	struct regmap *regs;
> +	struct device *dev;
>   };
>   
> +static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy)
> +{
> +	int ret;
> +	u32 read_value = 0, reg_mask = 0;
> +	struct device_node *ssc_node = NULL;
> +
> +	ssc_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING);
> +	if (!ssc_node) {
> +		dev_err(&phy->dev, "SSC node is NULL\n");
> +		return -ENODEV;
> +	}
> +
> +	ret = of_property_read_u32(ssc_node, RG_XTP_GLB_TXPLL_SSC_DELTA_HBR, &read_value);
> +	if (ret < 0 || !read_value) {
> +		dev_err(&phy->dev, "Read SSC vlaue fail!\n");
> +		return -EINVAL;
> +	}
> +	read_value |= read_value << 16;
> +	reg_mask |= XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT;
> +
> +	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_GLB_DA_REG_14, reg_mask, read_value);
> +
> +	return 0;
> +}
> +
>   static int mtk_dp_phy_init(struct phy *phy)
>   {
>   	struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
> @@ -137,6 +170,8 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
>   	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
>   			   TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
>   
> +	mtk_dp_set_ssc_config(phy, dp_phy);
> +
>   	return 0;
>   }
>   
> @@ -186,6 +221,8 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
>   	if (!dev->of_node)
>   		phy_create_lookup(phy, "dp", dev_name(dev));
>   
> +	dp_phy->dev = dev;
> +
>   	return 0;
>   }
>   

Re: [PATCH v2 1/2] Add write DP phyd register from parse dts

[LIANKUN YANG (杨连坤)]

On Mon, 2024-05-13 at 15:11 +0200, AngeloGioacchino Del Regno wrote:
> Il 10/05/24 13:04, Liankun Yang ha scritto:
> > During the testing phase, screen flickering is observed when
> > using displayport for screen casting. Relevant SSC register
> > parameters
> > are set in dts to address the screen flickering issue effectively
> > and
> > improve compatibility with different devices by adjusting the SSC
> > gear.
> > 
> > Obtaining the DPTX node, parsing the dts to obtain PHY register
> > address
> > and value can adapt to settings of different manufacturers
> > projects.
> > 
> > Changeds in v2:
> > - Optimized method of writing to DP PHY register
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/__;!!CTRNKA9wMg0ARbw!jYnU_tl6YGTUcFparAOcusS3u-H9G26yso2BwugBLoeMOanZudxtqRpEYV1Zy6phDjCQH2amG0KdSaR0s7EZGycYxzaBhBvtuw$
> >  
> > 20240403040517.3279-1-liankun.yang@mediatek.com/
> > 
> > Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> 
> There's no devicetree support in this driver - infact, it's being
> probed by
> mtk-dp as a platform device.
> 
> You keep sending untested stuff. Fourth time in a row.
> 
> Please, TEST YOUR COMMITS upstream before sending!
> 
> Regards,
> Angelo
> 

Thank you for your comment.
It's being probed by mtk-dp as a platform device.
But through dts analysis is a better solution.
I TEST COMMITS upstream before sending in the next version.

Best Regards,
Liankun Yang

> > ---
> >   drivers/phy/mediatek/phy-mtk-dp.c | 37
> > +++++++++++++++++++++++++++++++
> >   1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/phy/mediatek/phy-mtk-dp.c
> > b/drivers/phy/mediatek/phy-mtk-dp.c
> > index d7024a144335..ce78112d5938 100644
> > --- a/drivers/phy/mediatek/phy-mtk-dp.c
> > +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> > @@ -28,6 +28,10 @@
> >   #define MTK_DP_PHY_DIG_SW_RST		(PHY_OFFSET + 0x38)
> >   #define DP_GLB_SW_RST_PHYD		BIT(0)
> >   
> > +#define MTK_DP_PHY_DIG_GLB_DA_REG_14	(PHY_OFFSET + 0xD8)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT	GENMASK(15, 0)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT	GENMASK(31, 16)
> > +
> >   #define MTK_DP_LANE0_DRIVING_PARAM_3		(PHY_OFFSET +
> > 0x138)
> >   #define MTK_DP_LANE1_DRIVING_PARAM_3		(PHY_OFFSET +
> > 0x238)
> >   #define MTK_DP_LANE2_DRIVING_PARAM_3		(PHY_OFFSET +
> > 0x338)
> > @@ -78,10 +82,39 @@
> >   #define DRIVING_PARAM_8_DEFAULT	(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEF
> > AULT | \
> >   				 XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> >   
> > +#define SSC_SETTING	"dp-ssc-setting"
> > +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR	"ssc-delta-hbr"
> > +
> >   struct mtk_dp_phy {
> >   	struct regmap *regs;
> > +	struct device *dev;
> >   };
> >   
> > +static int mtk_dp_set_ssc_config(struct phy *phy, struct
> > mtk_dp_phy *dp_phy)
> > +{
> > +	int ret;
> > +	u32 read_value = 0, reg_mask = 0;
> > +	struct device_node *ssc_node = NULL;
> > +
> > +	ssc_node = of_find_node_by_name(dp_phy->dev->of_node,
> > SSC_SETTING);
> > +	if (!ssc_node) {
> > +		dev_err(&phy->dev, "SSC node is NULL\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	ret = of_property_read_u32(ssc_node,
> > RG_XTP_GLB_TXPLL_SSC_DELTA_HBR, &read_value);
> > +	if (ret < 0 || !read_value) {
> > +		dev_err(&phy->dev, "Read SSC vlaue fail!\n");
> > +		return -EINVAL;
> > +	}
> > +	read_value |= read_value << 16;
> > +	reg_mask |= XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT;
> > +
> > +	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_GLB_DA_REG_14,
> > reg_mask, read_value);
> > +
> > +	return 0;
> > +}
> > +
> >   static int mtk_dp_phy_init(struct phy *phy)
> >   {
> >   	struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
> > @@ -137,6 +170,8 @@ static int mtk_dp_phy_configure(struct phy
> > *phy, union phy_configure_opts *opts)
> >   	regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
> >   			   TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN :
> > 0);
> >   
> > +	mtk_dp_set_ssc_config(phy, dp_phy);
> > +
> >   	return 0;
> >   }
> >   
> > @@ -186,6 +221,8 @@ static int mtk_dp_phy_probe(struct
> > platform_device *pdev)
> >   	if (!dev->of_node)
> >   		phy_create_lookup(phy, "dp", dev_name(dev));
> >   
> > +	dp_phy->dev = dev;
> > +
> >   	return 0;
> >   }
> >   
> 
> 

[PATCH v2 2/2] Add dp PHY dt-bindings

[Liankun Yang]

Add dp PHY dt-bindings.

Changeds in v2:
- Add dp PHY dt-bindings.
https://patchwork.kernel.org/project/linux-mediatek/patch/
20240403040517.3279-1-liankun.yang@mediatek.com/

Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
---
 .../display/mediatek/mediatek.phy-dp.yaml     | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml
index 000000000000..476bc329363f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Port Controller
+
+maintainers:
+  - Mac shen <mac.shen@mediatek.com>
+  - Liankun yang <Liankun.yang@mediatek.com>
+
+description: |
+  Special settings need to be configured by MediaTek DP based on the actual
+  hardware situation. For example, when using a certain brand's docking
+  station for display projection, garbage may appear. Adjusting the specific
+  ssc value can resolve this issue.
+
+properties:
+  status: disabled
+    description: |
+      Since the DP driver has already registered the DP PHY device
+      through mtk_dp_register_phy(), so the status is disabled.
+
+  dp-ssc-setting:
+    - ssc-delta-hbr
+    description: Specific values are set based on the actual HW situation.
+
+required:
+  - status
+  - dp-ssc-setting
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        phy-dp@1c600000 {
+          status = "disabled";
+          dp-ssc-setting {
+            ssc-delta-hbr = <0x01fe>;
+          }
+        };
+    };
-- 
2.18.0

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[Rob Herring]

On Fri, May 10, 2024 at 07:04:15PM +0800, Liankun Yang wrote:
> Add dp PHY dt-bindings.
> 
> Changeds in v2:
> - Add dp PHY dt-bindings.
> https://patchwork.kernel.org/project/linux-mediatek/patch/
> 20240403040517.3279-1-liankun.yang@mediatek.com/
> 
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> ---
>  .../display/mediatek/mediatek.phy-dp.yaml     | 45 +++++++++++++++++++
>  1 file changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml

git refuses to apply your patch because 'new file mode 100644' is 
missing. You must have edited the patch or something.

If it did apply, you'd notice it fails testing.

> index 000000000000..476bc329363f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Display Port Controller
> +
> +maintainers:
> +  - Mac shen <mac.shen@mediatek.com>
> +  - Liankun yang <Liankun.yang@mediatek.com>
> +
> +description: |
> +  Special settings need to be configured by MediaTek DP based on the actual
> +  hardware situation. For example, when using a certain brand's docking
> +  station for display projection, garbage may appear. Adjusting the specific
> +  ssc value can resolve this issue.
> +
> +properties:
> +  status: disabled
> +    description: |
> +      Since the DP driver has already registered the DP PHY device
> +      through mtk_dp_register_phy(), so the status is disabled.

What!? Please show me any other binding that has 'status' in it. Go read 
up on how to write bindings and what goes in them.

> +
> +  dp-ssc-setting:
> +    - ssc-delta-hbr
> +    description: Specific values are set based on the actual HW situation.
> +
> +required:
> +  - status
> +  - dp-ssc-setting
> +
> +examples:
> +  - |
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        phy-dp@1c600000 {
> +          status = "disabled";
> +          dp-ssc-setting {
> +            ssc-delta-hbr = <0x01fe>;
> +          }
> +        };
> +    };
> -- 
> 2.18.0
> 

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[LIANKUN YANG (杨连坤)]

On Fri, 2024-05-10 at 07:48 -0500, Rob Herring wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On Fri, May 10, 2024 at 07:04:15PM +0800, Liankun Yang wrote:
> > Add dp PHY dt-bindings.
> > 
> > Changeds in v2:
> > - Add dp PHY dt-bindings.
> > https://patchwork.kernel.org/project/linux-mediatek/patch/
> > 20240403040517.3279-1-liankun.yang@mediatek.com/
> > 
> > Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> > ---
> >  .../display/mediatek/mediatek.phy-dp.yaml     | 45
> +++++++++++++++++++
> >  1 file changed, 45 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> 
> git refuses to apply your patch because 'new file mode 100644' is 
> missing. You must have edited the patch or something.
> 
> If it did apply, you'd notice it fails testing.
> 

After checking patch,one warning is new file is 'new file mode 100644'.
I will pay attention to the problem in a later patch.

> > index 000000000000..476bc329363f
> > --- /dev/null
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> > @@ -0,0 +1,45 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek Display Port Controller
> > +
> > +maintainers:
> > +  - Mac shen <mac.shen@mediatek.com>
> > +  - Liankun yang <Liankun.yang@mediatek.com>
> > +
> > +description: |
> > +  Special settings need to be configured by MediaTek DP based on
> the actual
> > +  hardware situation. For example, when using a certain brand's
> docking
> > +  station for display projection, garbage may appear. Adjusting
> the specific
> > +  ssc value can resolve this issue.
> > +
> > +properties:
> > +  status: disabled
> > +    description: |
> > +      Since the DP driver has already registered the DP PHY device
> > +      through mtk_dp_register_phy(), so the status is disabled.
> 
> What!? Please show me any other binding that has 'status' in it. Go
> read 
> up on how to write bindings and what goes in them.
> 

Sorry,thank you for your comments.
I immediately learn how to write bindings.

> > +
> > +  dp-ssc-setting:
> > +    - ssc-delta-hbr
> > +    description: Specific values are set based on the actual HW
> situation.
> > +
> > +required:
> > +  - status
> > +  - dp-ssc-setting
> > +
> > +examples:
> > +  - |
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        phy-dp@1c600000 {
> > +          status = "disabled";
> > +          dp-ssc-setting {
> > +            ssc-delta-hbr = <0x01fe>;
> > +          }
> > +        };
> > +    };
> > -- 
> > 2.18.0
> > 

Best regards,
Liankun yang

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[Krzysztof Kozlowski]

On 10/05/2024 13:04, Liankun Yang wrote:
> Add dp PHY dt-bindings.

This tells me nothing. Read submitting patches.

> 
> Changeds in v2:

This does goes to changelog, not commit log.

> - Add dp PHY dt-bindings.
> https://patchwork.kernel.org/project/linux-mediatek/patch/
> 20240403040517.3279-1-liankun.yang@mediatek.com/
> 
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>

This patch looks terrible... there's so many wrong things I don't even
know where to start.

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

Please run scripts/checkpatch.pl and fix reported warnings. Then please
run `scripts/checkpatch.pl --strict` and (probably) fix more warnings.
Some warnings can be ignored, especially from --strict run, but the code
here looks like it needs a fix. Feel free to get in touch if the warning
is not clear.


> ---
>  .../display/mediatek/mediatek.phy-dp.yaml     | 45 +++++++++++++++++++
>  1 file changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml

Wrong filename

> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml
> index 000000000000..476bc329363f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Display Port Controller
> +
> +maintainers:
> +  - Mac shen <mac.shen@mediatek.com>
> +  - Liankun yang <Liankun.yang@mediatek.com>
> +
> +description: |
> +  Special settings need to be configured by MediaTek DP based on the actual
> +  hardware situation. For example, when using a certain brand's docking
> +  station for display projection, garbage may appear. Adjusting the specific
> +  ssc value can resolve this issue.
> +
> +properties:
> +  status: disabled

I think you nicely shocked Rob already.

Please reach internally to Mediatek or collaborating companies to get
basic training and instructions how to write patches and bindings.

Otherwise it is waste of our time. Mediatek is not a small company so
there is no excuse in sending such poor quality patches, which would be
EASILY spotted by the MOST BASIC review.

Best regards,
Krzysztof

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[LIANKUN YANG (杨连坤)]

On Mon, 2024-05-13 at 08:37 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 10/05/2024 13:04, Liankun Yang wrote:
> > Add dp PHY dt-bindings.
> 
> This tells me nothing. Read submitting patches.
> 
> > 
> > Changeds in v2:
> 
> This does goes to changelog, not commit log.
> 
> > - Add dp PHY dt-bindings.
> > https://patchwork.kernel.org/project/linux-mediatek/patch/
> > 20240403040517.3279-1-liankun.yang@mediatek.com/
> > 
> > Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> 
> This patch looks terrible... there's so many wrong things I don't
> even
> know where to start.
> 
> Please use subject prefixes matching the subsystem. You can get them
> for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the
> directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> 
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> 
> Please run scripts/checkpatch.pl and fix reported warnings. Then
> please
> run `scripts/checkpatch.pl --strict` and (probably) fix more
> warnings.
> Some warnings can be ignored, especially from --strict run, but the
> code
> here looks like it needs a fix. Feel free to get in touch if the
> warning
> is not clear.
> 
> 
> > ---
> >  .../display/mediatek/mediatek.phy-dp.yaml     | 45
> +++++++++++++++++++
> >  1 file changed, 45 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> 
> Wrong filename
> 
> > 
> > diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> > index 000000000000..476bc329363f
> > --- /dev/null
> > +++
> b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> > @@ -0,0 +1,45 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek Display Port Controller
> > +
> > +maintainers:
> > +  - Mac shen <mac.shen@mediatek.com>
> > +  - Liankun yang <Liankun.yang@mediatek.com>
> > +
> > +description: |
> > +  Special settings need to be configured by MediaTek DP based on
> the actual
> > +  hardware situation. For example, when using a certain brand's
> docking
> > +  station for display projection, garbage may appear. Adjusting
> the specific
> > +  ssc value can resolve this issue.
> > +
> > +properties:
> > +  status: disabled
> 
> I think you nicely shocked Rob already.
> 
> Please reach internally to Mediatek or collaborating companies to get
> basic training and instructions how to write patches and bindings.
> 
> Otherwise it is waste of our time. Mediatek is not a small company so
> there is no excuse in sending such poor quality patches, which would
> be
> EASILY spotted by the MOST BASIC review.
> 
> Best regards,
> Krzysztof
> 

I used scripts/checkpatch.pl and fix reported error and warnings.
I am resumbmitting bindings by the MOST BASIC review.

Best regards,
Liankun Yang

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[Krzysztof Kozlowski]

On 13/05/2024 16:15, LIANKUN YANG (杨连坤) wrote:
> On Mon, 2024-05-13 at 08:37 +0200, Krzysztof Kozlowski wrote:
>>  	 
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>  On 10/05/2024 13:04, Liankun Yang wrote:
>>> Add dp PHY dt-bindings.
>>
>> This tells me nothing. Read submitting patches.
>>
>>>
>>> Changeds in v2:
>>
>> This does goes to changelog, not commit log.
>>
>>> - Add dp PHY dt-bindings.
>>> https://patchwork.kernel.org/project/linux-mediatek/patch/
>>> 20240403040517.3279-1-liankun.yang@mediatek.com/
>>>
>>> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
>>
>> This patch looks terrible... there's so many wrong things I don't
>> even
>> know where to start.
>>
>> Please use subject prefixes matching the subsystem. You can get them
>> for
>> example with `git log --oneline -- DIRECTORY_OR_FILE` on the
>> directory
>> your patch is touching. For bindings, the preferred subjects are
>> explained here:
>>
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>>
>> Please run scripts/checkpatch.pl and fix reported warnings. Then
>> please
>> run `scripts/checkpatch.pl --strict` and (probably) fix more
>> warnings.
>> Some warnings can be ignored, especially from --strict run, but the
>> code
>> here looks like it needs a fix. Feel free to get in touch if the
>> warning
>> is not clear.
>>
>>
>>> ---
>>>  .../display/mediatek/mediatek.phy-dp.yaml     | 45
>> +++++++++++++++++++
>>>  1 file changed, 45 insertions(+)
>>>  create mode 100644
>> Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
>> dp.yaml
>>
>> Wrong filename
>>
>>>
>>> diff --git
>> a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
>> dp.yaml
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
>> dp.yaml
>>> index 000000000000..476bc329363f
>>> --- /dev/null
>>> +++
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
>> dp.yaml
>>> @@ -0,0 +1,45 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: 
>> http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: MediaTek Display Port Controller
>>> +
>>> +maintainers:
>>> +  - Mac shen <mac.shen@mediatek.com>
>>> +  - Liankun yang <Liankun.yang@mediatek.com>
>>> +
>>> +description: |
>>> +  Special settings need to be configured by MediaTek DP based on
>> the actual
>>> +  hardware situation. For example, when using a certain brand's
>> docking
>>> +  station for display projection, garbage may appear. Adjusting
>> the specific
>>> +  ssc value can resolve this issue.
>>> +
>>> +properties:
>>> +  status: disabled
>>
>> I think you nicely shocked Rob already.
>>
>> Please reach internally to Mediatek or collaborating companies to get
>> basic training and instructions how to write patches and bindings.
>>
>> Otherwise it is waste of our time. Mediatek is not a small company so
>> there is no excuse in sending such poor quality patches, which would
>> be
>> EASILY spotted by the MOST BASIC review.
>>
>> Best regards,
>> Krzysztof
>>
> 
> I used scripts/checkpatch.pl and fix reported error and warnings.
> I am resumbmitting bindings by the MOST BASIC review.

No, please wait. Who did the basic review of your patch? Who from
Mediatek? Upstream is not a workhorse to use instead of your resources
for the absolute basic stuff... This feels such exploiting.

Best regards,
Krzysztof

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[Krzysztof Kozlowski]

On 13/05/2024 16:17, Krzysztof Kozlowski wrote:
>>> dp.yaml
>>>> @@ -0,0 +1,45 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: 
>>> http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: MediaTek Display Port Controller
>>>> +
>>>> +maintainers:
>>>> +  - Mac shen <mac.shen@mediatek.com>
>>>> +  - Liankun yang <Liankun.yang@mediatek.com>
>>>> +
>>>> +description: |
>>>> +  Special settings need to be configured by MediaTek DP based on
>>> the actual
>>>> +  hardware situation. For example, when using a certain brand's
>>> docking
>>>> +  station for display projection, garbage may appear. Adjusting
>>> the specific
>>>> +  ssc value can resolve this issue.
>>>> +
>>>> +properties:
>>>> +  status: disabled
>>>
>>> I think you nicely shocked Rob already.
>>>
>>> Please reach internally to Mediatek or collaborating companies to get
>>> basic training and instructions how to write patches and bindings.
>>>
>>> Otherwise it is waste of our time. Mediatek is not a small company so
>>> there is no excuse in sending such poor quality patches, which would
>>> be
>>> EASILY spotted by the MOST BASIC review.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> I used scripts/checkpatch.pl and fix reported error and warnings.
>> I am resumbmitting bindings by the MOST BASIC review.
> 
> No, please wait. Who did the basic review of your patch? Who from
> Mediatek? Upstream is not a workhorse to use instead of your resources
> for the absolute basic stuff... This feels such exploiting.
> 

After reading AngeloGioacchino's response, it looks even worse... This
was never tested...

So not only exploiting but also feels like wasting our time.

Best regards,
Krzysztof

Re: [PATCH v2 2/2] Add dp PHY dt-bindings

[LIANKUN YANG (杨连坤)]

On Mon, 2024-05-13 at 16:20 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 13/05/2024 16:17, Krzysztof Kozlowski wrote:
> >>> dp.yaml
> >>>> @@ -0,0 +1,45 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>> +%YAML 1.2
> >>>> +---
> >>>> +$id: 
> >>> 
> http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: MediaTek Display Port Controller
> >>>> +
> >>>> +maintainers:
> >>>> +  - Mac shen <mac.shen@mediatek.com>
> >>>> +  - Liankun yang <Liankun.yang@mediatek.com>
> >>>> +
> >>>> +description: |
> >>>> +  Special settings need to be configured by MediaTek DP based
> on
> >>> the actual
> >>>> +  hardware situation. For example, when using a certain brand's
> >>> docking
> >>>> +  station for display projection, garbage may appear. Adjusting
> >>> the specific
> >>>> +  ssc value can resolve this issue.
> >>>> +
> >>>> +properties:
> >>>> +  status: disabled
> >>>
> >>> I think you nicely shocked Rob already.
> >>>
> >>> Please reach internally to Mediatek or collaborating companies to
> get
> >>> basic training and instructions how to write patches and
> bindings.
> >>>
> >>> Otherwise it is waste of our time. Mediatek is not a small
> company so
> >>> there is no excuse in sending such poor quality patches, which
> would
> >>> be
> >>> EASILY spotted by the MOST BASIC review.
> >>>
> >>> Best regards,
> >>> Krzysztof
> >>>
> >>
> >> I used scripts/checkpatch.pl and fix reported error and warnings.
> >> I am resumbmitting bindings by the MOST BASIC review.
> > 
> > No, please wait. Who did the basic review of your patch? Who from
> > Mediatek? Upstream is not a workhorse to use instead of your
> resources
> > for the absolute basic stuff... This feels such exploiting.
> > 
> 
> After reading AngeloGioacchino's response, it looks even worse...
> This
> was never tested...
> 
> So not only exploiting but also feels like wasting our time.
> 
> Best regards,
> Krzysztof
> 


Sorry,I guess I didn't make myself clear.
I am resumbmitting bindings after the MOST BASIC internal review.
Thank you for your comment.

Best Regards,
Liankun Yang

Re: [PATCH v2 0/2] Add PHY-dp bindings

[Jani Nikula]

On Fri, 10 May 2024, Liankun Yang <liankun.yang@mediatek.com> wrote:
> Update write DP phyd register and add phy-dp bindings.
>
> Liankun Yang (2):
>   Add write DP phyd register from parse dts
>   Add dp PHY dt-bindings

Please use the proper subject prefix for the driver. git log suggests
"phy: phy-mtk-dp:".

Thanks,
Jani.


>
>  .../display/mediatek/mediatek.phy-dp.yaml     | 45 +++++++++++++++++++
>  drivers/phy/mediatek/phy-mtk-dp.c             | 37 +++++++++++++++
>  2 files changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml

-- 
Jani Nikula, Intel

Re: [PATCH v2 0/2] Add PHY-dp bindings

[LIANKUN YANG (杨连坤)]

On Fri, 2024-05-10 at 14:27 +0300, Jani Nikula wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On Fri, 10 May 2024, Liankun Yang <liankun.yang@mediatek.com> wrote:
> > Update write DP phyd register and add phy-dp bindings.
> >
> > Liankun Yang (2):
> >   Add write DP phyd register from parse dts
> >   Add dp PHY dt-bindings
> 
> Please use the proper subject prefix for the driver. git log suggests
> "phy: phy-mtk-dp:".
> 
> Thanks,
> Jani.
> 
> 
> >
> >  .../display/mediatek/mediatek.phy-dp.yaml     | 45
> +++++++++++++++++++
> >  drivers/phy/mediatek/phy-mtk-dp.c             | 37 +++++++++++++++
> >  2 files changed, 82 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek.phy-
> dp.yaml
> 
> -- 
> Jani Nikula, Intel

Thank you for your comments.
I will actively study and correct in the next version.

Best Regards,
Liankun Yang