* [PATCH v3 0/4] Add kd101ne3-40ti configuration in driver jd9365da
@ 2024-06-14 14:55 Zhaoxiong Lv
2024-06-14 14:55 ` [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands Zhaoxiong Lv
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Zhaoxiong Lv @ 2024-06-14 14:55 UTC (permalink / raw)
To: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos,
benjamin.tissoires, dianders, hsinyi
Cc: dri-devel, devicetree, linux-kernel, Zhaoxiong Lv
This kingdisplay panel uses the jd9365da controller, so add it to
panel-jadard-jd9365da-h3.c driver, but because the init_code and timing
are different, some variables are added in struct jadard_panel_des to
control it.
In addition, since sending init_code in the enable() function takes a long time,
it is moved to the prepare() function.
Changes in v3:
- PATCH 1/4: Modify the init_code sending method
- PATCH 2/4: Add binding for kingdisplay-kd101ne3 in jadard,jd9365da-h3.yaml
- PATCH 3/4: Add compatibility for kingdisplay-kd101ne3 in panel-jadard-jd9365da-h3.c driver,
- and add some variables to control timing.
- PATCH 4/4: Add the function of adjusting orientation.
- Link to v2: https://lore.kernel.org/all/20240601084528.22502-1-lvzhaoxiong@huaqin.corp-partner.google.com/
Changes in v2:
- PATCH 1/4: Delete some unnecessary information.
- PATCH 2/4: Use the new mipi_dsi_dcs_write_seq_multi() function, deleted some unnecessary functions.
- PATCH 3/4: Add compatible for Starry-er88577.
- PATCH 4/4: Add starry panel configuration in panel-kingdisplay-kd101ne3 driver.
- Link to v1: https://lore.kernel.org/all/20240418081548.12160-1-lvzhaoxiong@huaqin.corp-partner.google.com/
Zhaoxiong Lv (4):
drm/panel: jd9365da: Modify the method of sending commands
dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3
drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel.
drm/panel: jd9365da: Add the function of adjusting orientation
.../display/panel/jadard,jd9365da-h3.yaml | 1 +
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 1081 +++++++++++------
2 files changed, 693 insertions(+), 389 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands 2024-06-14 14:55 [PATCH v3 0/4] Add kd101ne3-40ti configuration in driver jd9365da Zhaoxiong Lv @ 2024-06-14 14:55 ` Zhaoxiong Lv 2024-06-14 16:16 ` Dmitry Baryshkov 2024-06-14 17:09 ` Alex Bee 2024-06-14 14:55 ` [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Zhaoxiong Lv ` (2 subsequent siblings) 3 siblings, 2 replies; 10+ messages in thread From: Zhaoxiong Lv @ 2024-06-14 14:55 UTC (permalink / raw) To: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi Cc: dri-devel, devicetree, linux-kernel, Zhaoxiong Lv Currently, the init_code of the jd9365da driver is placed in the enable() function and sent, but this seems to take a long time. It takes 17ms to send each instruction (an init code consists of about 200 instructions), so it takes about 3.5s to send the init_code. So we moved the sending of the inti_code to the prepare() function, and each instruction seemed to take only 25μs. Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 781 +++++++++--------- 1 file changed, 393 insertions(+), 388 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 4879835fe101..b39f01d7002e 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -19,17 +19,13 @@ #include <linux/of.h> #include <linux/regulator/consumer.h> -#define JD9365DA_INIT_CMD_LEN 2 - -struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; -}; +struct jadard; struct jadard_panel_desc { const struct drm_display_mode mode; unsigned int lanes; enum mipi_dsi_pixel_format format; - const struct jadard_init_cmd *init_cmds; + int (*init)(struct jadard *jadard); u32 num_init_cmds; }; @@ -52,21 +48,9 @@ static int jadard_enable(struct drm_panel *panel) { struct device *dev = panel->dev; struct jadard *jadard = panel_to_jadard(panel); - const struct jadard_panel_desc *desc = jadard->desc; struct mipi_dsi_device *dsi = jadard->dsi; - unsigned int i; int err; - msleep(10); - - for (i = 0; i < desc->num_init_cmds; i++) { - const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; - - err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); - if (err < 0) - return err; - } - msleep(120); err = mipi_dsi_dcs_exit_sleep_mode(dsi); @@ -117,9 +101,21 @@ static int jadard_prepare(struct drm_panel *panel) msleep(10); gpiod_set_value(jadard->reset, 1); - msleep(120); + msleep(130); + + ret = jadard->desc->init(jadard); + if (ret < 0) + goto poweroff; return 0; + +poweroff: + gpiod_set_value(jadard->reset, 0); + /* T6: 2ms */ + usleep_range(1000, 2000); + regulator_disable(jadard->vccio); + + return ret; } static int jadard_unprepare(struct drm_panel *panel) @@ -167,176 +163,181 @@ static const struct drm_panel_funcs jadard_funcs = { .get_modes = jadard_get_modes, }; -static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = { - { .data = { 0xE0, 0x00 } }, - { .data = { 0xE1, 0x93 } }, - { .data = { 0xE2, 0x65 } }, - { .data = { 0xE3, 0xF8 } }, - { .data = { 0x80, 0x03 } }, - { .data = { 0xE0, 0x01 } }, - { .data = { 0x00, 0x00 } }, - { .data = { 0x01, 0x7E } }, - { .data = { 0x03, 0x00 } }, - { .data = { 0x04, 0x65 } }, - { .data = { 0x0C, 0x74 } }, - { .data = { 0x17, 0x00 } }, - { .data = { 0x18, 0xB7 } }, - { .data = { 0x19, 0x00 } }, - { .data = { 0x1A, 0x00 } }, - { .data = { 0x1B, 0xB7 } }, - { .data = { 0x1C, 0x00 } }, - { .data = { 0x24, 0xFE } }, - { .data = { 0x37, 0x19 } }, - { .data = { 0x38, 0x05 } }, - { .data = { 0x39, 0x00 } }, - { .data = { 0x3A, 0x01 } }, - { .data = { 0x3B, 0x01 } }, - { .data = { 0x3C, 0x70 } }, - { .data = { 0x3D, 0xFF } }, - { .data = { 0x3E, 0xFF } }, - { .data = { 0x3F, 0xFF } }, - { .data = { 0x40, 0x06 } }, - { .data = { 0x41, 0xA0 } }, - { .data = { 0x43, 0x1E } }, - { .data = { 0x44, 0x0F } }, - { .data = { 0x45, 0x28 } }, - { .data = { 0x4B, 0x04 } }, - { .data = { 0x55, 0x02 } }, - { .data = { 0x56, 0x01 } }, - { .data = { 0x57, 0xA9 } }, - { .data = { 0x58, 0x0A } }, - { .data = { 0x59, 0x0A } }, - { .data = { 0x5A, 0x37 } }, - { .data = { 0x5B, 0x19 } }, - { .data = { 0x5D, 0x78 } }, - { .data = { 0x5E, 0x63 } }, - { .data = { 0x5F, 0x54 } }, - { .data = { 0x60, 0x49 } }, - { .data = { 0x61, 0x45 } }, - { .data = { 0x62, 0x38 } }, - { .data = { 0x63, 0x3D } }, - { .data = { 0x64, 0x28 } }, - { .data = { 0x65, 0x43 } }, - { .data = { 0x66, 0x41 } }, - { .data = { 0x67, 0x43 } }, - { .data = { 0x68, 0x62 } }, - { .data = { 0x69, 0x50 } }, - { .data = { 0x6A, 0x57 } }, - { .data = { 0x6B, 0x49 } }, - { .data = { 0x6C, 0x44 } }, - { .data = { 0x6D, 0x37 } }, - { .data = { 0x6E, 0x23 } }, - { .data = { 0x6F, 0x10 } }, - { .data = { 0x70, 0x78 } }, - { .data = { 0x71, 0x63 } }, - { .data = { 0x72, 0x54 } }, - { .data = { 0x73, 0x49 } }, - { .data = { 0x74, 0x45 } }, - { .data = { 0x75, 0x38 } }, - { .data = { 0x76, 0x3D } }, - { .data = { 0x77, 0x28 } }, - { .data = { 0x78, 0x43 } }, - { .data = { 0x79, 0x41 } }, - { .data = { 0x7A, 0x43 } }, - { .data = { 0x7B, 0x62 } }, - { .data = { 0x7C, 0x50 } }, - { .data = { 0x7D, 0x57 } }, - { .data = { 0x7E, 0x49 } }, - { .data = { 0x7F, 0x44 } }, - { .data = { 0x80, 0x37 } }, - { .data = { 0x81, 0x23 } }, - { .data = { 0x82, 0x10 } }, - { .data = { 0xE0, 0x02 } }, - { .data = { 0x00, 0x47 } }, - { .data = { 0x01, 0x47 } }, - { .data = { 0x02, 0x45 } }, - { .data = { 0x03, 0x45 } }, - { .data = { 0x04, 0x4B } }, - { .data = { 0x05, 0x4B } }, - { .data = { 0x06, 0x49 } }, - { .data = { 0x07, 0x49 } }, - { .data = { 0x08, 0x41 } }, - { .data = { 0x09, 0x1F } }, - { .data = { 0x0A, 0x1F } }, - { .data = { 0x0B, 0x1F } }, - { .data = { 0x0C, 0x1F } }, - { .data = { 0x0D, 0x1F } }, - { .data = { 0x0E, 0x1F } }, - { .data = { 0x0F, 0x5F } }, - { .data = { 0x10, 0x5F } }, - { .data = { 0x11, 0x57 } }, - { .data = { 0x12, 0x77 } }, - { .data = { 0x13, 0x35 } }, - { .data = { 0x14, 0x1F } }, - { .data = { 0x15, 0x1F } }, - { .data = { 0x16, 0x46 } }, - { .data = { 0x17, 0x46 } }, - { .data = { 0x18, 0x44 } }, - { .data = { 0x19, 0x44 } }, - { .data = { 0x1A, 0x4A } }, - { .data = { 0x1B, 0x4A } }, - { .data = { 0x1C, 0x48 } }, - { .data = { 0x1D, 0x48 } }, - { .data = { 0x1E, 0x40 } }, - { .data = { 0x1F, 0x1F } }, - { .data = { 0x20, 0x1F } }, - { .data = { 0x21, 0x1F } }, - { .data = { 0x22, 0x1F } }, - { .data = { 0x23, 0x1F } }, - { .data = { 0x24, 0x1F } }, - { .data = { 0x25, 0x5F } }, - { .data = { 0x26, 0x5F } }, - { .data = { 0x27, 0x57 } }, - { .data = { 0x28, 0x77 } }, - { .data = { 0x29, 0x35 } }, - { .data = { 0x2A, 0x1F } }, - { .data = { 0x2B, 0x1F } }, - { .data = { 0x58, 0x40 } }, - { .data = { 0x59, 0x00 } }, - { .data = { 0x5A, 0x00 } }, - { .data = { 0x5B, 0x10 } }, - { .data = { 0x5C, 0x06 } }, - { .data = { 0x5D, 0x40 } }, - { .data = { 0x5E, 0x01 } }, - { .data = { 0x5F, 0x02 } }, - { .data = { 0x60, 0x30 } }, - { .data = { 0x61, 0x01 } }, - { .data = { 0x62, 0x02 } }, - { .data = { 0x63, 0x03 } }, - { .data = { 0x64, 0x6B } }, - { .data = { 0x65, 0x05 } }, - { .data = { 0x66, 0x0C } }, - { .data = { 0x67, 0x73 } }, - { .data = { 0x68, 0x09 } }, - { .data = { 0x69, 0x03 } }, - { .data = { 0x6A, 0x56 } }, - { .data = { 0x6B, 0x08 } }, - { .data = { 0x6C, 0x00 } }, - { .data = { 0x6D, 0x04 } }, - { .data = { 0x6E, 0x04 } }, - { .data = { 0x6F, 0x88 } }, - { .data = { 0x70, 0x00 } }, - { .data = { 0x71, 0x00 } }, - { .data = { 0x72, 0x06 } }, - { .data = { 0x73, 0x7B } }, - { .data = { 0x74, 0x00 } }, - { .data = { 0x75, 0xF8 } }, - { .data = { 0x76, 0x00 } }, - { .data = { 0x77, 0xD5 } }, - { .data = { 0x78, 0x2E } }, - { .data = { 0x79, 0x12 } }, - { .data = { 0x7A, 0x03 } }, - { .data = { 0x7B, 0x00 } }, - { .data = { 0x7C, 0x00 } }, - { .data = { 0x7D, 0x03 } }, - { .data = { 0x7E, 0x7B } }, - { .data = { 0xE0, 0x04 } }, - { .data = { 0x00, 0x0E } }, - { .data = { 0x02, 0xB3 } }, - { .data = { 0x09, 0x60 } }, - { .data = { 0x0E, 0x2A } }, - { .data = { 0x36, 0x59 } }, - { .data = { 0xE0, 0x00 } }, +static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + + return 0; }; static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { @@ -359,205 +360,209 @@ static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { }, .lanes = 4, .format = MIPI_DSI_FMT_RGB888, - .init_cmds = radxa_display_8hd_ad002_init_cmds, - .num_init_cmds = ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds), + .init = radxa_display_8hd_ad002_init_cmds, }; -static const struct jadard_init_cmd cz101b4001_init_cmds[] = { - { .data = { 0xE0, 0x00 } }, - { .data = { 0xE1, 0x93 } }, - { .data = { 0xE2, 0x65 } }, - { .data = { 0xE3, 0xF8 } }, - { .data = { 0x80, 0x03 } }, - { .data = { 0xE0, 0x01 } }, - { .data = { 0x00, 0x00 } }, - { .data = { 0x01, 0x3B } }, - { .data = { 0x0C, 0x74 } }, - { .data = { 0x17, 0x00 } }, - { .data = { 0x18, 0xAF } }, - { .data = { 0x19, 0x00 } }, - { .data = { 0x1A, 0x00 } }, - { .data = { 0x1B, 0xAF } }, - { .data = { 0x1C, 0x00 } }, - { .data = { 0x35, 0x26 } }, - { .data = { 0x37, 0x09 } }, - { .data = { 0x38, 0x04 } }, - { .data = { 0x39, 0x00 } }, - { .data = { 0x3A, 0x01 } }, - { .data = { 0x3C, 0x78 } }, - { .data = { 0x3D, 0xFF } }, - { .data = { 0x3E, 0xFF } }, - { .data = { 0x3F, 0x7F } }, - { .data = { 0x40, 0x06 } }, - { .data = { 0x41, 0xA0 } }, - { .data = { 0x42, 0x81 } }, - { .data = { 0x43, 0x14 } }, - { .data = { 0x44, 0x23 } }, - { .data = { 0x45, 0x28 } }, - { .data = { 0x55, 0x02 } }, - { .data = { 0x57, 0x69 } }, - { .data = { 0x59, 0x0A } }, - { .data = { 0x5A, 0x2A } }, - { .data = { 0x5B, 0x17 } }, - { .data = { 0x5D, 0x7F } }, - { .data = { 0x5E, 0x6B } }, - { .data = { 0x5F, 0x5C } }, - { .data = { 0x60, 0x4F } }, - { .data = { 0x61, 0x4D } }, - { .data = { 0x62, 0x3F } }, - { .data = { 0x63, 0x42 } }, - { .data = { 0x64, 0x2B } }, - { .data = { 0x65, 0x44 } }, - { .data = { 0x66, 0x43 } }, - { .data = { 0x67, 0x43 } }, - { .data = { 0x68, 0x63 } }, - { .data = { 0x69, 0x52 } }, - { .data = { 0x6A, 0x5A } }, - { .data = { 0x6B, 0x4F } }, - { .data = { 0x6C, 0x4E } }, - { .data = { 0x6D, 0x20 } }, - { .data = { 0x6E, 0x0F } }, - { .data = { 0x6F, 0x00 } }, - { .data = { 0x70, 0x7F } }, - { .data = { 0x71, 0x6B } }, - { .data = { 0x72, 0x5C } }, - { .data = { 0x73, 0x4F } }, - { .data = { 0x74, 0x4D } }, - { .data = { 0x75, 0x3F } }, - { .data = { 0x76, 0x42 } }, - { .data = { 0x77, 0x2B } }, - { .data = { 0x78, 0x44 } }, - { .data = { 0x79, 0x43 } }, - { .data = { 0x7A, 0x43 } }, - { .data = { 0x7B, 0x63 } }, - { .data = { 0x7C, 0x52 } }, - { .data = { 0x7D, 0x5A } }, - { .data = { 0x7E, 0x4F } }, - { .data = { 0x7F, 0x4E } }, - { .data = { 0x80, 0x20 } }, - { .data = { 0x81, 0x0F } }, - { .data = { 0x82, 0x00 } }, - { .data = { 0xE0, 0x02 } }, - { .data = { 0x00, 0x02 } }, - { .data = { 0x01, 0x02 } }, - { .data = { 0x02, 0x00 } }, - { .data = { 0x03, 0x00 } }, - { .data = { 0x04, 0x1E } }, - { .data = { 0x05, 0x1E } }, - { .data = { 0x06, 0x1F } }, - { .data = { 0x07, 0x1F } }, - { .data = { 0x08, 0x1F } }, - { .data = { 0x09, 0x17 } }, - { .data = { 0x0A, 0x17 } }, - { .data = { 0x0B, 0x37 } }, - { .data = { 0x0C, 0x37 } }, - { .data = { 0x0D, 0x47 } }, - { .data = { 0x0E, 0x47 } }, - { .data = { 0x0F, 0x45 } }, - { .data = { 0x10, 0x45 } }, - { .data = { 0x11, 0x4B } }, - { .data = { 0x12, 0x4B } }, - { .data = { 0x13, 0x49 } }, - { .data = { 0x14, 0x49 } }, - { .data = { 0x15, 0x1F } }, - { .data = { 0x16, 0x01 } }, - { .data = { 0x17, 0x01 } }, - { .data = { 0x18, 0x00 } }, - { .data = { 0x19, 0x00 } }, - { .data = { 0x1A, 0x1E } }, - { .data = { 0x1B, 0x1E } }, - { .data = { 0x1C, 0x1F } }, - { .data = { 0x1D, 0x1F } }, - { .data = { 0x1E, 0x1F } }, - { .data = { 0x1F, 0x17 } }, - { .data = { 0x20, 0x17 } }, - { .data = { 0x21, 0x37 } }, - { .data = { 0x22, 0x37 } }, - { .data = { 0x23, 0x46 } }, - { .data = { 0x24, 0x46 } }, - { .data = { 0x25, 0x44 } }, - { .data = { 0x26, 0x44 } }, - { .data = { 0x27, 0x4A } }, - { .data = { 0x28, 0x4A } }, - { .data = { 0x29, 0x48 } }, - { .data = { 0x2A, 0x48 } }, - { .data = { 0x2B, 0x1F } }, - { .data = { 0x2C, 0x01 } }, - { .data = { 0x2D, 0x01 } }, - { .data = { 0x2E, 0x00 } }, - { .data = { 0x2F, 0x00 } }, - { .data = { 0x30, 0x1F } }, - { .data = { 0x31, 0x1F } }, - { .data = { 0x32, 0x1E } }, - { .data = { 0x33, 0x1E } }, - { .data = { 0x34, 0x1F } }, - { .data = { 0x35, 0x17 } }, - { .data = { 0x36, 0x17 } }, - { .data = { 0x37, 0x37 } }, - { .data = { 0x38, 0x37 } }, - { .data = { 0x39, 0x08 } }, - { .data = { 0x3A, 0x08 } }, - { .data = { 0x3B, 0x0A } }, - { .data = { 0x3C, 0x0A } }, - { .data = { 0x3D, 0x04 } }, - { .data = { 0x3E, 0x04 } }, - { .data = { 0x3F, 0x06 } }, - { .data = { 0x40, 0x06 } }, - { .data = { 0x41, 0x1F } }, - { .data = { 0x42, 0x02 } }, - { .data = { 0x43, 0x02 } }, - { .data = { 0x44, 0x00 } }, - { .data = { 0x45, 0x00 } }, - { .data = { 0x46, 0x1F } }, - { .data = { 0x47, 0x1F } }, - { .data = { 0x48, 0x1E } }, - { .data = { 0x49, 0x1E } }, - { .data = { 0x4A, 0x1F } }, - { .data = { 0x4B, 0x17 } }, - { .data = { 0x4C, 0x17 } }, - { .data = { 0x4D, 0x37 } }, - { .data = { 0x4E, 0x37 } }, - { .data = { 0x4F, 0x09 } }, - { .data = { 0x50, 0x09 } }, - { .data = { 0x51, 0x0B } }, - { .data = { 0x52, 0x0B } }, - { .data = { 0x53, 0x05 } }, - { .data = { 0x54, 0x05 } }, - { .data = { 0x55, 0x07 } }, - { .data = { 0x56, 0x07 } }, - { .data = { 0x57, 0x1F } }, - { .data = { 0x58, 0x40 } }, - { .data = { 0x5B, 0x30 } }, - { .data = { 0x5C, 0x16 } }, - { .data = { 0x5D, 0x34 } }, - { .data = { 0x5E, 0x05 } }, - { .data = { 0x5F, 0x02 } }, - { .data = { 0x63, 0x00 } }, - { .data = { 0x64, 0x6A } }, - { .data = { 0x67, 0x73 } }, - { .data = { 0x68, 0x1D } }, - { .data = { 0x69, 0x08 } }, - { .data = { 0x6A, 0x6A } }, - { .data = { 0x6B, 0x08 } }, - { .data = { 0x6C, 0x00 } }, - { .data = { 0x6D, 0x00 } }, - { .data = { 0x6E, 0x00 } }, - { .data = { 0x6F, 0x88 } }, - { .data = { 0x75, 0xFF } }, - { .data = { 0x77, 0xDD } }, - { .data = { 0x78, 0x3F } }, - { .data = { 0x79, 0x15 } }, - { .data = { 0x7A, 0x17 } }, - { .data = { 0x7D, 0x14 } }, - { .data = { 0x7E, 0x82 } }, - { .data = { 0xE0, 0x04 } }, - { .data = { 0x00, 0x0E } }, - { .data = { 0x02, 0xB3 } }, - { .data = { 0x09, 0x61 } }, - { .data = { 0x0E, 0x48 } }, - { .data = { 0xE0, 0x00 } }, - { .data = { 0xE6, 0x02 } }, - { .data = { 0xE7, 0x0C } }, +static int cz101b4001_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); + + return 0; }; static const struct jadard_panel_desc cz101b4001_desc = { @@ -580,8 +585,8 @@ static const struct jadard_panel_desc cz101b4001_desc = { }, .lanes = 4, .format = MIPI_DSI_FMT_RGB888, - .init_cmds = cz101b4001_init_cmds, - .num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds), + .init = cz101b4001_init_cmds, + }; static int jadard_dsi_probe(struct mipi_dsi_device *dsi) -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands 2024-06-14 14:55 ` [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands Zhaoxiong Lv @ 2024-06-14 16:16 ` Dmitry Baryshkov 2024-06-14 17:09 ` Alex Bee 1 sibling, 0 replies; 10+ messages in thread From: Dmitry Baryshkov @ 2024-06-14 16:16 UTC (permalink / raw) To: Zhaoxiong Lv Cc: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi, dri-devel, devicetree, linux-kernel On Fri, Jun 14, 2024 at 10:55:07PM GMT, Zhaoxiong Lv wrote: > Currently, the init_code of the jd9365da driver is placed > in the enable() function and sent, but this seems to take > a long time. It takes 17ms to send each instruction (an init > code consists of about 200 instructions), so it takes > about 3.5s to send the init_code. So we moved the sending > of the inti_code to the prepare() function, and each > instruction seemed to take only 25μs. Additional details about the DSI host would be appreciated. I guess that the difference in time used to send the command is due to the DSI host interleaving commands between video frames, but it would be nice to have that spelled in the commit message. > > Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> > --- > .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 781 +++++++++--------- > 1 file changed, 393 insertions(+), 388 deletions(-) > > diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > index 4879835fe101..b39f01d7002e 100644 > --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > @@ -19,17 +19,13 @@ > #include <linux/of.h> > #include <linux/regulator/consumer.h> > > -#define JD9365DA_INIT_CMD_LEN 2 > - > -struct jadard_init_cmd { > - u8 data[JD9365DA_INIT_CMD_LEN]; > -}; > +struct jadard; > > struct jadard_panel_desc { > const struct drm_display_mode mode; > unsigned int lanes; > enum mipi_dsi_pixel_format format; > - const struct jadard_init_cmd *init_cmds; > + int (*init)(struct jadard *jadard); > u32 num_init_cmds; > }; > > @@ -52,21 +48,9 @@ static int jadard_enable(struct drm_panel *panel) > { > struct device *dev = panel->dev; > struct jadard *jadard = panel_to_jadard(panel); > - const struct jadard_panel_desc *desc = jadard->desc; > struct mipi_dsi_device *dsi = jadard->dsi; > - unsigned int i; > int err; > > - msleep(10); > - > - for (i = 0; i < desc->num_init_cmds; i++) { > - const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; > - > - err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); > - if (err < 0) > - return err; > - } > - > msleep(120); > > err = mipi_dsi_dcs_exit_sleep_mode(dsi); > @@ -117,9 +101,21 @@ static int jadard_prepare(struct drm_panel *panel) > msleep(10); > > gpiod_set_value(jadard->reset, 1); > - msleep(120); > + msleep(130); > + > + ret = jadard->desc->init(jadard); > + if (ret < 0) > + goto poweroff; Plese don't mix refactoring with functional changes. Please split this into two patches, one for using _multi and another one for moving init to prepare() > > return 0; > + > +poweroff: > + gpiod_set_value(jadard->reset, 0); > + /* T6: 2ms */ > + usleep_range(1000, 2000); > + regulator_disable(jadard->vccio); > + > + return ret; > } > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands 2024-06-14 14:55 ` [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands Zhaoxiong Lv 2024-06-14 16:16 ` Dmitry Baryshkov @ 2024-06-14 17:09 ` Alex Bee 1 sibling, 0 replies; 10+ messages in thread From: Alex Bee @ 2024-06-14 17:09 UTC (permalink / raw) To: Zhaoxiong Lv, dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi Cc: dri-devel, devicetree, linux-kernel Am 14.06.24 um 16:55 schrieb Zhaoxiong Lv: > Currently, the init_code of the jd9365da driver is placed > in the enable() function and sent, but this seems to take > a long time. It takes 17ms to send each instruction (an init > code consists of about 200 instructions), so it takes > about 3.5s to send the init_code. So we moved the sending That's certainly a dsi host issue (to slow AHB/APB host clock?). With a Synopsis DSI host it takes < 10 ms when called in .enable. > of the inti_code to the prepare() function, and each > instruction seemed to take only 25μs. > > Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> > --- > .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 781 +++++++++--------- > 1 file changed, 393 insertions(+), 388 deletions(-) > > diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > index 4879835fe101..b39f01d7002e 100644 > --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > @@ -19,17 +19,13 @@ > #include <linux/of.h> > #include <linux/regulator/consumer.h> > > -#define JD9365DA_INIT_CMD_LEN 2 > - > -struct jadard_init_cmd { > - u8 data[JD9365DA_INIT_CMD_LEN]; > -}; > +struct jadard; > > struct jadard_panel_desc { > const struct drm_display_mode mode; > unsigned int lanes; > enum mipi_dsi_pixel_format format; > - const struct jadard_init_cmd *init_cmds; > + int (*init)(struct jadard *jadard); > u32 num_init_cmds; > }; > > @@ -52,21 +48,9 @@ static int jadard_enable(struct drm_panel *panel) > { > struct device *dev = panel->dev; > struct jadard *jadard = panel_to_jadard(panel); > - const struct jadard_panel_desc *desc = jadard->desc; > struct mipi_dsi_device *dsi = jadard->dsi; > - unsigned int i; > int err; > > - msleep(10); > - > - for (i = 0; i < desc->num_init_cmds; i++) { > - const struct jadard_init_cmd *cmd = &desc->init_cmds[i]; > - > - err = mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); > - if (err < 0) > - return err; > - } Why did you remove that and instead of just make mipi_dsi_dcs_write_buffer to mipi_dsi_dcs_write_seq_multi and call it in .prepare if you think that improves anything? The code looks rather ugly now, imho. Alex > - > msleep(120); > > err = mipi_dsi_dcs_exit_sleep_mode(dsi); > @@ -117,9 +101,21 @@ static int jadard_prepare(struct drm_panel *panel) > msleep(10); > > gpiod_set_value(jadard->reset, 1); > - msleep(120); > + msleep(130); > + > + ret = jadard->desc->init(jadard); > + if (ret < 0) > + goto poweroff; > > return 0; > + > +poweroff: > + gpiod_set_value(jadard->reset, 0); > + /* T6: 2ms */ > + usleep_range(1000, 2000); > + regulator_disable(jadard->vccio); > + > + return ret; > } > > static int jadard_unprepare(struct drm_panel *panel) > @@ -167,176 +163,181 @@ static const struct drm_panel_funcs jadard_funcs = { > .get_modes = jadard_get_modes, > }; > > -static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = { > - { .data = { 0xE0, 0x00 } }, > - { .data = { 0xE1, 0x93 } }, > - { .data = { 0xE2, 0x65 } }, > - { .data = { 0xE3, 0xF8 } }, > - { .data = { 0x80, 0x03 } }, > - { .data = { 0xE0, 0x01 } }, > - { .data = { 0x00, 0x00 } }, > - { .data = { 0x01, 0x7E } }, > - { .data = { 0x03, 0x00 } }, > - { .data = { 0x04, 0x65 } }, > - { .data = { 0x0C, 0x74 } }, > - { .data = { 0x17, 0x00 } }, > - { .data = { 0x18, 0xB7 } }, > - { .data = { 0x19, 0x00 } }, > - { .data = { 0x1A, 0x00 } }, > - { .data = { 0x1B, 0xB7 } }, > - { .data = { 0x1C, 0x00 } }, > - { .data = { 0x24, 0xFE } }, > - { .data = { 0x37, 0x19 } }, > - { .data = { 0x38, 0x05 } }, > - { .data = { 0x39, 0x00 } }, > - { .data = { 0x3A, 0x01 } }, > - { .data = { 0x3B, 0x01 } }, > - { .data = { 0x3C, 0x70 } }, > - { .data = { 0x3D, 0xFF } }, > - { .data = { 0x3E, 0xFF } }, > - { .data = { 0x3F, 0xFF } }, > - { .data = { 0x40, 0x06 } }, > - { .data = { 0x41, 0xA0 } }, > - { .data = { 0x43, 0x1E } }, > - { .data = { 0x44, 0x0F } }, > - { .data = { 0x45, 0x28 } }, > - { .data = { 0x4B, 0x04 } }, > - { .data = { 0x55, 0x02 } }, > - { .data = { 0x56, 0x01 } }, > - { .data = { 0x57, 0xA9 } }, > - { .data = { 0x58, 0x0A } }, > - { .data = { 0x59, 0x0A } }, > - { .data = { 0x5A, 0x37 } }, > - { .data = { 0x5B, 0x19 } }, > - { .data = { 0x5D, 0x78 } }, > - { .data = { 0x5E, 0x63 } }, > - { .data = { 0x5F, 0x54 } }, > - { .data = { 0x60, 0x49 } }, > - { .data = { 0x61, 0x45 } }, > - { .data = { 0x62, 0x38 } }, > - { .data = { 0x63, 0x3D } }, > - { .data = { 0x64, 0x28 } }, > - { .data = { 0x65, 0x43 } }, > - { .data = { 0x66, 0x41 } }, > - { .data = { 0x67, 0x43 } }, > - { .data = { 0x68, 0x62 } }, > - { .data = { 0x69, 0x50 } }, > - { .data = { 0x6A, 0x57 } }, > - { .data = { 0x6B, 0x49 } }, > - { .data = { 0x6C, 0x44 } }, > - { .data = { 0x6D, 0x37 } }, > - { .data = { 0x6E, 0x23 } }, > - { .data = { 0x6F, 0x10 } }, > - { .data = { 0x70, 0x78 } }, > - { .data = { 0x71, 0x63 } }, > - { .data = { 0x72, 0x54 } }, > - { .data = { 0x73, 0x49 } }, > - { .data = { 0x74, 0x45 } }, > - { .data = { 0x75, 0x38 } }, > - { .data = { 0x76, 0x3D } }, > - { .data = { 0x77, 0x28 } }, > - { .data = { 0x78, 0x43 } }, > - { .data = { 0x79, 0x41 } }, > - { .data = { 0x7A, 0x43 } }, > - { .data = { 0x7B, 0x62 } }, > - { .data = { 0x7C, 0x50 } }, > - { .data = { 0x7D, 0x57 } }, > - { .data = { 0x7E, 0x49 } }, > - { .data = { 0x7F, 0x44 } }, > - { .data = { 0x80, 0x37 } }, > - { .data = { 0x81, 0x23 } }, > - { .data = { 0x82, 0x10 } }, > - { .data = { 0xE0, 0x02 } }, > - { .data = { 0x00, 0x47 } }, > - { .data = { 0x01, 0x47 } }, > - { .data = { 0x02, 0x45 } }, > - { .data = { 0x03, 0x45 } }, > - { .data = { 0x04, 0x4B } }, > - { .data = { 0x05, 0x4B } }, > - { .data = { 0x06, 0x49 } }, > - { .data = { 0x07, 0x49 } }, > - { .data = { 0x08, 0x41 } }, > - { .data = { 0x09, 0x1F } }, > - { .data = { 0x0A, 0x1F } }, > - { .data = { 0x0B, 0x1F } }, > - { .data = { 0x0C, 0x1F } }, > - { .data = { 0x0D, 0x1F } }, > - { .data = { 0x0E, 0x1F } }, > - { .data = { 0x0F, 0x5F } }, > - { .data = { 0x10, 0x5F } }, > - { .data = { 0x11, 0x57 } }, > - { .data = { 0x12, 0x77 } }, > - { .data = { 0x13, 0x35 } }, > - { .data = { 0x14, 0x1F } }, > - { .data = { 0x15, 0x1F } }, > - { .data = { 0x16, 0x46 } }, > - { .data = { 0x17, 0x46 } }, > - { .data = { 0x18, 0x44 } }, > - { .data = { 0x19, 0x44 } }, > - { .data = { 0x1A, 0x4A } }, > - { .data = { 0x1B, 0x4A } }, > - { .data = { 0x1C, 0x48 } }, > - { .data = { 0x1D, 0x48 } }, > - { .data = { 0x1E, 0x40 } }, > - { .data = { 0x1F, 0x1F } }, > - { .data = { 0x20, 0x1F } }, > - { .data = { 0x21, 0x1F } }, > - { .data = { 0x22, 0x1F } }, > - { .data = { 0x23, 0x1F } }, > - { .data = { 0x24, 0x1F } }, > - { .data = { 0x25, 0x5F } }, > - { .data = { 0x26, 0x5F } }, > - { .data = { 0x27, 0x57 } }, > - { .data = { 0x28, 0x77 } }, > - { .data = { 0x29, 0x35 } }, > - { .data = { 0x2A, 0x1F } }, > - { .data = { 0x2B, 0x1F } }, > - { .data = { 0x58, 0x40 } }, > - { .data = { 0x59, 0x00 } }, > - { .data = { 0x5A, 0x00 } }, > - { .data = { 0x5B, 0x10 } }, > - { .data = { 0x5C, 0x06 } }, > - { .data = { 0x5D, 0x40 } }, > - { .data = { 0x5E, 0x01 } }, > - { .data = { 0x5F, 0x02 } }, > - { .data = { 0x60, 0x30 } }, > - { .data = { 0x61, 0x01 } }, > - { .data = { 0x62, 0x02 } }, > - { .data = { 0x63, 0x03 } }, > - { .data = { 0x64, 0x6B } }, > - { .data = { 0x65, 0x05 } }, > - { .data = { 0x66, 0x0C } }, > - { .data = { 0x67, 0x73 } }, > - { .data = { 0x68, 0x09 } }, > - { .data = { 0x69, 0x03 } }, > - { .data = { 0x6A, 0x56 } }, > - { .data = { 0x6B, 0x08 } }, > - { .data = { 0x6C, 0x00 } }, > - { .data = { 0x6D, 0x04 } }, > - { .data = { 0x6E, 0x04 } }, > - { .data = { 0x6F, 0x88 } }, > - { .data = { 0x70, 0x00 } }, > - { .data = { 0x71, 0x00 } }, > - { .data = { 0x72, 0x06 } }, > - { .data = { 0x73, 0x7B } }, > - { .data = { 0x74, 0x00 } }, > - { .data = { 0x75, 0xF8 } }, > - { .data = { 0x76, 0x00 } }, > - { .data = { 0x77, 0xD5 } }, > - { .data = { 0x78, 0x2E } }, > - { .data = { 0x79, 0x12 } }, > - { .data = { 0x7A, 0x03 } }, > - { .data = { 0x7B, 0x00 } }, > - { .data = { 0x7C, 0x00 } }, > - { .data = { 0x7D, 0x03 } }, > - { .data = { 0x7E, 0x7B } }, > - { .data = { 0xE0, 0x04 } }, > - { .data = { 0x00, 0x0E } }, > - { .data = { 0x02, 0xB3 } }, > - { .data = { 0x09, 0x60 } }, > - { .data = { 0x0E, 0x2A } }, > - { .data = { 0x36, 0x59 } }, > - { .data = { 0xE0, 0x00 } }, > +static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) > +{ > + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; > + > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); > + > + return 0; > }; > > static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { > @@ -359,205 +360,209 @@ static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { > }, > .lanes = 4, > .format = MIPI_DSI_FMT_RGB888, > - .init_cmds = radxa_display_8hd_ad002_init_cmds, > - .num_init_cmds = ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds), > + .init = radxa_display_8hd_ad002_init_cmds, > }; > > -static const struct jadard_init_cmd cz101b4001_init_cmds[] = { > - { .data = { 0xE0, 0x00 } }, > - { .data = { 0xE1, 0x93 } }, > - { .data = { 0xE2, 0x65 } }, > - { .data = { 0xE3, 0xF8 } }, > - { .data = { 0x80, 0x03 } }, > - { .data = { 0xE0, 0x01 } }, > - { .data = { 0x00, 0x00 } }, > - { .data = { 0x01, 0x3B } }, > - { .data = { 0x0C, 0x74 } }, > - { .data = { 0x17, 0x00 } }, > - { .data = { 0x18, 0xAF } }, > - { .data = { 0x19, 0x00 } }, > - { .data = { 0x1A, 0x00 } }, > - { .data = { 0x1B, 0xAF } }, > - { .data = { 0x1C, 0x00 } }, > - { .data = { 0x35, 0x26 } }, > - { .data = { 0x37, 0x09 } }, > - { .data = { 0x38, 0x04 } }, > - { .data = { 0x39, 0x00 } }, > - { .data = { 0x3A, 0x01 } }, > - { .data = { 0x3C, 0x78 } }, > - { .data = { 0x3D, 0xFF } }, > - { .data = { 0x3E, 0xFF } }, > - { .data = { 0x3F, 0x7F } }, > - { .data = { 0x40, 0x06 } }, > - { .data = { 0x41, 0xA0 } }, > - { .data = { 0x42, 0x81 } }, > - { .data = { 0x43, 0x14 } }, > - { .data = { 0x44, 0x23 } }, > - { .data = { 0x45, 0x28 } }, > - { .data = { 0x55, 0x02 } }, > - { .data = { 0x57, 0x69 } }, > - { .data = { 0x59, 0x0A } }, > - { .data = { 0x5A, 0x2A } }, > - { .data = { 0x5B, 0x17 } }, > - { .data = { 0x5D, 0x7F } }, > - { .data = { 0x5E, 0x6B } }, > - { .data = { 0x5F, 0x5C } }, > - { .data = { 0x60, 0x4F } }, > - { .data = { 0x61, 0x4D } }, > - { .data = { 0x62, 0x3F } }, > - { .data = { 0x63, 0x42 } }, > - { .data = { 0x64, 0x2B } }, > - { .data = { 0x65, 0x44 } }, > - { .data = { 0x66, 0x43 } }, > - { .data = { 0x67, 0x43 } }, > - { .data = { 0x68, 0x63 } }, > - { .data = { 0x69, 0x52 } }, > - { .data = { 0x6A, 0x5A } }, > - { .data = { 0x6B, 0x4F } }, > - { .data = { 0x6C, 0x4E } }, > - { .data = { 0x6D, 0x20 } }, > - { .data = { 0x6E, 0x0F } }, > - { .data = { 0x6F, 0x00 } }, > - { .data = { 0x70, 0x7F } }, > - { .data = { 0x71, 0x6B } }, > - { .data = { 0x72, 0x5C } }, > - { .data = { 0x73, 0x4F } }, > - { .data = { 0x74, 0x4D } }, > - { .data = { 0x75, 0x3F } }, > - { .data = { 0x76, 0x42 } }, > - { .data = { 0x77, 0x2B } }, > - { .data = { 0x78, 0x44 } }, > - { .data = { 0x79, 0x43 } }, > - { .data = { 0x7A, 0x43 } }, > - { .data = { 0x7B, 0x63 } }, > - { .data = { 0x7C, 0x52 } }, > - { .data = { 0x7D, 0x5A } }, > - { .data = { 0x7E, 0x4F } }, > - { .data = { 0x7F, 0x4E } }, > - { .data = { 0x80, 0x20 } }, > - { .data = { 0x81, 0x0F } }, > - { .data = { 0x82, 0x00 } }, > - { .data = { 0xE0, 0x02 } }, > - { .data = { 0x00, 0x02 } }, > - { .data = { 0x01, 0x02 } }, > - { .data = { 0x02, 0x00 } }, > - { .data = { 0x03, 0x00 } }, > - { .data = { 0x04, 0x1E } }, > - { .data = { 0x05, 0x1E } }, > - { .data = { 0x06, 0x1F } }, > - { .data = { 0x07, 0x1F } }, > - { .data = { 0x08, 0x1F } }, > - { .data = { 0x09, 0x17 } }, > - { .data = { 0x0A, 0x17 } }, > - { .data = { 0x0B, 0x37 } }, > - { .data = { 0x0C, 0x37 } }, > - { .data = { 0x0D, 0x47 } }, > - { .data = { 0x0E, 0x47 } }, > - { .data = { 0x0F, 0x45 } }, > - { .data = { 0x10, 0x45 } }, > - { .data = { 0x11, 0x4B } }, > - { .data = { 0x12, 0x4B } }, > - { .data = { 0x13, 0x49 } }, > - { .data = { 0x14, 0x49 } }, > - { .data = { 0x15, 0x1F } }, > - { .data = { 0x16, 0x01 } }, > - { .data = { 0x17, 0x01 } }, > - { .data = { 0x18, 0x00 } }, > - { .data = { 0x19, 0x00 } }, > - { .data = { 0x1A, 0x1E } }, > - { .data = { 0x1B, 0x1E } }, > - { .data = { 0x1C, 0x1F } }, > - { .data = { 0x1D, 0x1F } }, > - { .data = { 0x1E, 0x1F } }, > - { .data = { 0x1F, 0x17 } }, > - { .data = { 0x20, 0x17 } }, > - { .data = { 0x21, 0x37 } }, > - { .data = { 0x22, 0x37 } }, > - { .data = { 0x23, 0x46 } }, > - { .data = { 0x24, 0x46 } }, > - { .data = { 0x25, 0x44 } }, > - { .data = { 0x26, 0x44 } }, > - { .data = { 0x27, 0x4A } }, > - { .data = { 0x28, 0x4A } }, > - { .data = { 0x29, 0x48 } }, > - { .data = { 0x2A, 0x48 } }, > - { .data = { 0x2B, 0x1F } }, > - { .data = { 0x2C, 0x01 } }, > - { .data = { 0x2D, 0x01 } }, > - { .data = { 0x2E, 0x00 } }, > - { .data = { 0x2F, 0x00 } }, > - { .data = { 0x30, 0x1F } }, > - { .data = { 0x31, 0x1F } }, > - { .data = { 0x32, 0x1E } }, > - { .data = { 0x33, 0x1E } }, > - { .data = { 0x34, 0x1F } }, > - { .data = { 0x35, 0x17 } }, > - { .data = { 0x36, 0x17 } }, > - { .data = { 0x37, 0x37 } }, > - { .data = { 0x38, 0x37 } }, > - { .data = { 0x39, 0x08 } }, > - { .data = { 0x3A, 0x08 } }, > - { .data = { 0x3B, 0x0A } }, > - { .data = { 0x3C, 0x0A } }, > - { .data = { 0x3D, 0x04 } }, > - { .data = { 0x3E, 0x04 } }, > - { .data = { 0x3F, 0x06 } }, > - { .data = { 0x40, 0x06 } }, > - { .data = { 0x41, 0x1F } }, > - { .data = { 0x42, 0x02 } }, > - { .data = { 0x43, 0x02 } }, > - { .data = { 0x44, 0x00 } }, > - { .data = { 0x45, 0x00 } }, > - { .data = { 0x46, 0x1F } }, > - { .data = { 0x47, 0x1F } }, > - { .data = { 0x48, 0x1E } }, > - { .data = { 0x49, 0x1E } }, > - { .data = { 0x4A, 0x1F } }, > - { .data = { 0x4B, 0x17 } }, > - { .data = { 0x4C, 0x17 } }, > - { .data = { 0x4D, 0x37 } }, > - { .data = { 0x4E, 0x37 } }, > - { .data = { 0x4F, 0x09 } }, > - { .data = { 0x50, 0x09 } }, > - { .data = { 0x51, 0x0B } }, > - { .data = { 0x52, 0x0B } }, > - { .data = { 0x53, 0x05 } }, > - { .data = { 0x54, 0x05 } }, > - { .data = { 0x55, 0x07 } }, > - { .data = { 0x56, 0x07 } }, > - { .data = { 0x57, 0x1F } }, > - { .data = { 0x58, 0x40 } }, > - { .data = { 0x5B, 0x30 } }, > - { .data = { 0x5C, 0x16 } }, > - { .data = { 0x5D, 0x34 } }, > - { .data = { 0x5E, 0x05 } }, > - { .data = { 0x5F, 0x02 } }, > - { .data = { 0x63, 0x00 } }, > - { .data = { 0x64, 0x6A } }, > - { .data = { 0x67, 0x73 } }, > - { .data = { 0x68, 0x1D } }, > - { .data = { 0x69, 0x08 } }, > - { .data = { 0x6A, 0x6A } }, > - { .data = { 0x6B, 0x08 } }, > - { .data = { 0x6C, 0x00 } }, > - { .data = { 0x6D, 0x00 } }, > - { .data = { 0x6E, 0x00 } }, > - { .data = { 0x6F, 0x88 } }, > - { .data = { 0x75, 0xFF } }, > - { .data = { 0x77, 0xDD } }, > - { .data = { 0x78, 0x3F } }, > - { .data = { 0x79, 0x15 } }, > - { .data = { 0x7A, 0x17 } }, > - { .data = { 0x7D, 0x14 } }, > - { .data = { 0x7E, 0x82 } }, > - { .data = { 0xE0, 0x04 } }, > - { .data = { 0x00, 0x0E } }, > - { .data = { 0x02, 0xB3 } }, > - { .data = { 0x09, 0x61 } }, > - { .data = { 0x0E, 0x48 } }, > - { .data = { 0xE0, 0x00 } }, > - { .data = { 0xE6, 0x02 } }, > - { .data = { 0xE7, 0x0C } }, > +static int cz101b4001_init_cmds(struct jadard *jadard) > +{ > + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; > + > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); > + > + return 0; > }; > > static const struct jadard_panel_desc cz101b4001_desc = { > @@ -580,8 +585,8 @@ static const struct jadard_panel_desc cz101b4001_desc = { > }, > .lanes = 4, > .format = MIPI_DSI_FMT_RGB888, > - .init_cmds = cz101b4001_init_cmds, > - .num_init_cmds = ARRAY_SIZE(cz101b4001_init_cmds), > + .init = cz101b4001_init_cmds, > + > }; > > static int jadard_dsi_probe(struct mipi_dsi_device *dsi) ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 2024-06-14 14:55 [PATCH v3 0/4] Add kd101ne3-40ti configuration in driver jd9365da Zhaoxiong Lv 2024-06-14 14:55 ` [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands Zhaoxiong Lv @ 2024-06-14 14:55 ` Zhaoxiong Lv 2024-06-14 16:34 ` Dmitry Baryshkov 2024-06-15 10:06 ` Krzysztof Kozlowski 2024-06-14 14:55 ` [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel Zhaoxiong Lv 2024-06-14 14:55 ` [PATCH v3 4/4] drm/panel: jd9365da: Add the function of adjusting orientation Zhaoxiong Lv 3 siblings, 2 replies; 10+ messages in thread From: Zhaoxiong Lv @ 2024-06-14 14:55 UTC (permalink / raw) To: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi Cc: dri-devel, devicetree, linux-kernel, Zhaoxiong Lv The kingdisplay-kd101ne3 is a 10.1" WXGA TFT-LCD panel with jadard-jd9365da controller. Hence, we add a new compatible with panel specific config. Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> --- Chage since V3: - 1. Abandon the V2 patch and add kingdisplay kd101ne3-40ti binding to - jadard,jd9365da-h3.yaml again. V2:https://lore.kernel.org/all/20240601084528.22502-2-lvzhaoxiong@huaqin.corp-partner.google.com/ Chage since V2: - Drop some properties that have already been defined in panel-common. - The header file 'dt-bindings/gpio/gpio.h' is not used, delete it V1: https://lore.kernel.org/all/20240418081548.12160-2-lvzhaoxiong@huaqin.corp-partner.google.com/ --- .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml index 41eb7fbf7715..6138d853a15b 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml @@ -19,6 +19,7 @@ properties: - chongzhou,cz101b4001 - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 + - kingdisplay,kd101ne3-40ti - const: jadard,jd9365da-h3 reg: true -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 2024-06-14 14:55 ` [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Zhaoxiong Lv @ 2024-06-14 16:34 ` Dmitry Baryshkov 2024-06-15 10:06 ` Krzysztof Kozlowski 1 sibling, 0 replies; 10+ messages in thread From: Dmitry Baryshkov @ 2024-06-14 16:34 UTC (permalink / raw) To: Zhaoxiong Lv Cc: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi, dri-devel, devicetree, linux-kernel On Fri, Jun 14, 2024 at 10:55:08PM GMT, Zhaoxiong Lv wrote: > The kingdisplay-kd101ne3 is a 10.1" WXGA TFT-LCD panel with > jadard-jd9365da controller. Hence, we add a new compatible > with panel specific config. > > Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> > --- > Chage since V3: > > - 1. Abandon the V2 patch and add kingdisplay kd101ne3-40ti binding to > - jadard,jd9365da-h3.yaml again. > > V2:https://lore.kernel.org/all/20240601084528.22502-2-lvzhaoxiong@huaqin.corp-partner.google.com/ > > Chage since V2: > > - Drop some properties that have already been defined in panel-common. > - The header file 'dt-bindings/gpio/gpio.h' is not used, delete it > > V1: https://lore.kernel.org/all/20240418081548.12160-2-lvzhaoxiong@huaqin.corp-partner.google.com/ > > --- > .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml > index 41eb7fbf7715..6138d853a15b 100644 > --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml > +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml > @@ -19,6 +19,7 @@ properties: > - chongzhou,cz101b4001 > - radxa,display-10hd-ad001 > - radxa,display-8hd-ad002 > + - kingdisplay,kd101ne3-40ti I think the list was sorted. Please keep it this way. > - const: jadard,jd9365da-h3 > > reg: true > -- > 2.17.1 > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 2024-06-14 14:55 ` [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Zhaoxiong Lv 2024-06-14 16:34 ` Dmitry Baryshkov @ 2024-06-15 10:06 ` Krzysztof Kozlowski 1 sibling, 0 replies; 10+ messages in thread From: Krzysztof Kozlowski @ 2024-06-15 10:06 UTC (permalink / raw) To: Zhaoxiong Lv, dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi Cc: dri-devel, devicetree, linux-kernel On 14/06/2024 16:55, Zhaoxiong Lv wrote: > The kingdisplay-kd101ne3 is a 10.1" WXGA TFT-LCD panel with > jadard-jd9365da controller. Hence, we add a new compatible > with panel specific config. > > Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> > --- > Chage since V3: > > - 1. Abandon the V2 patch and add kingdisplay kd101ne3-40ti binding to > - jadard,jd9365da-h3.yaml again. > > V2:https://lore.kernel.org/all/20240601084528.22502-2-lvzhaoxiong@huaqin.corp-partner.google.com/ > > Chage since V2: > > - Drop some properties that have already been defined in panel-common. > - The header file 'dt-bindings/gpio/gpio.h' is not used, delete it > > V1: https://lore.kernel.org/all/20240418081548.12160-2-lvzhaoxiong@huaqin.corp-partner.google.com/ > > --- > .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml > index 41eb7fbf7715..6138d853a15b 100644 > --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml > +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml > @@ -19,6 +19,7 @@ properties: > - chongzhou,cz101b4001 > - radxa,display-10hd-ad001 > - radxa,display-8hd-ad002 > + - kingdisplay,kd101ne3-40ti Again, don't add to the end of the lists. Look - list is ordered. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel. 2024-06-14 14:55 [PATCH v3 0/4] Add kd101ne3-40ti configuration in driver jd9365da Zhaoxiong Lv 2024-06-14 14:55 ` [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands Zhaoxiong Lv 2024-06-14 14:55 ` [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Zhaoxiong Lv @ 2024-06-14 14:55 ` Zhaoxiong Lv 2024-06-14 17:05 ` Dmitry Baryshkov 2024-06-14 14:55 ` [PATCH v3 4/4] drm/panel: jd9365da: Add the function of adjusting orientation Zhaoxiong Lv 3 siblings, 1 reply; 10+ messages in thread From: Zhaoxiong Lv @ 2024-06-14 14:55 UTC (permalink / raw) To: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi Cc: dri-devel, devicetree, linux-kernel, Zhaoxiong Lv The K&d kd101ne3-40ti is a 10.1" WXGA TFT-LCD panel, use jd9365da controller,which fits in nicely with the existing panel-jadard-jd9365da-h3 driver.Hence,we add a new compatible with panel specific config. Although they have the same control IC, the two panels are different, and the timing will be slightly different, so we added some variables in struct jadard_panel_desc to control the timing Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> --- Chage since V3: - 1. Give up creating a new driver and re-add K&d kd101ne3-40ti - configuration to the panel-jadard-jd9365da-h3.c driver. V2:https://lore.kernel.org/all/20240601084528.22502-3-lvzhaoxiong@huaqin.corp-partner.google.com/ Chage since V2: - 1. Use the new mipi_dsi_dcs_write_seq_multi() function. - 2. Modify Move mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sleep_mode() to disable(), - and drop kingdisplay_panel_enter_sleep_mode(). - 3. If prepare fails, disable GPIO before regulators. - 4. This function drm_connector_set_panel_orientation() is no longer used. Delete it. - 5. Drop ".shutdown = kingdisplay_panel_shutdown". --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 284 ++++++++++++++++++ 1 file changed, 284 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index b39f01d7002e..f6e130567707 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -27,6 +27,15 @@ struct jadard_panel_desc { enum mipi_dsi_pixel_format format; int (*init)(struct jadard *jadard); u32 num_init_cmds; + bool lp11_before_reset; + bool power_off_vcioo_before_reset; + unsigned int vcioo_to_lp11_delay; + unsigned int lp11_to_reset_delay; + unsigned int exit_sleep_to_display_on_delay; + unsigned int display_on_delay; + unsigned int backlight_off_to_display_off_delay; + unsigned int display_off_to_enter_sleep_delay; + unsigned int enter_sleep_to_reset_down_delay; }; struct jadard { @@ -57,10 +66,18 @@ static int jadard_enable(struct drm_panel *panel) if (err < 0) DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err); + /* tSLPOUT >= 120ms */ + if (jadard->desc->exit_sleep_to_display_on_delay) + msleep(jadard->desc->exit_sleep_to_display_on_delay); + err = mipi_dsi_dcs_set_display_on(dsi); if (err < 0) DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err); + /* tDISON >= 20ms */ + if (jadard->desc->display_on_delay) + msleep(jadard->desc->display_on_delay); + return 0; } @@ -70,14 +87,26 @@ static int jadard_disable(struct drm_panel *panel) struct jadard *jadard = panel_to_jadard(panel); int ret; + /* tBLOFF:Backlight_to_0x28h >= 100ms */ + if (jadard->desc->backlight_off_to_display_off_delay) + msleep(jadard->desc->backlight_off_to_display_off_delay); + ret = mipi_dsi_dcs_set_display_off(jadard->dsi); if (ret < 0) DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); + /* tDISOFF >= 50ms */ + if (jadard->desc->display_off_to_enter_sleep_delay) + msleep(jadard->desc->display_off_to_enter_sleep_delay); + ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); if (ret < 0) DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); + /* tSLPIN >= 100ms */ + if (jadard->desc->enter_sleep_to_reset_down_delay) + msleep(jadard->desc->enter_sleep_to_reset_down_delay); + return 0; } @@ -94,6 +123,21 @@ static int jadard_prepare(struct drm_panel *panel) if (ret) return ret; + /* tMIPI_ON >= 0ms */ + if (jadard->desc->vcioo_to_lp11_delay) + msleep(jadard->desc->vcioo_to_lp11_delay); + + if (jadard->desc->lp11_before_reset) { + ret = mipi_dsi_dcs_nop(jadard->dsi); + if (ret < 0) + goto poweroff; + + usleep_range(1000, 2000); + } + /* tRPWIRES >= 5ms */ + if (jadard->desc->lp11_to_reset_delay) + msleep(jadard->desc->lp11_to_reset_delay); + gpiod_set_value(jadard->reset, 1); msleep(5); @@ -125,6 +169,12 @@ static int jadard_unprepare(struct drm_panel *panel) gpiod_set_value(jadard->reset, 1); msleep(120); + if (jadard->desc->power_off_vcioo_before_reset) { + gpiod_set_value(jadard->reset, 0); + + usleep_range(1000, 2000); + } + regulator_disable(jadard->vdd); regulator_disable(jadard->vccio); @@ -586,7 +636,237 @@ static const struct jadard_panel_desc cz101b4001_desc = { .lanes = 4, .format = MIPI_DSI_FMT_RGB888, .init = cz101b4001_init_cmds, +}; + +static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + + return 0; +}; + +static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = { + .mode = { + .clock = 70595, + + .hdisplay = 800, + .hsync_start = 800 + 30, + .hsync_end = 800 + 30 + 30, + .htotal = 800 + 30 + 30 + 30, + + .vdisplay = 1280, + .vsync_start = 1280 + 30, + .vsync_end = 1280 + 30 + 4, + .vtotal = 1280 + 30 + 4 + 8, + + .width_mm = 135, + .height_mm = 216, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init = kingdisplay_kd101ne3_init_cmds, + .lp11_before_reset = true, + .power_off_vcioo_before_reset = true, + .vcioo_to_lp11_delay = 5, + .lp11_to_reset_delay = 10, + .exit_sleep_to_display_on_delay = 120, + .display_on_delay = 20, + .backlight_off_to_display_off_delay = 100, + .display_off_to_enter_sleep_delay = 50, + .enter_sleep_to_reset_down_delay = 100, }; static int jadard_dsi_probe(struct mipi_dsi_device *dsi) @@ -665,6 +945,10 @@ static const struct of_device_id jadard_of_match[] = { .compatible = "radxa,display-8hd-ad002", .data = &radxa_display_8hd_ad002_desc }, + { + .compatible = "kingdisplay,kd101ne3-40ti", + .data = &kingdisplay_kd101ne3_40ti_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, jadard_of_match); -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel. 2024-06-14 14:55 ` [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel Zhaoxiong Lv @ 2024-06-14 17:05 ` Dmitry Baryshkov 0 siblings, 0 replies; 10+ messages in thread From: Dmitry Baryshkov @ 2024-06-14 17:05 UTC (permalink / raw) To: Zhaoxiong Lv Cc: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi, dri-devel, devicetree, linux-kernel On Fri, Jun 14, 2024 at 10:55:09PM GMT, Zhaoxiong Lv wrote: > The K&d kd101ne3-40ti is a 10.1" WXGA TFT-LCD panel, use > jd9365da controller,which fits in nicely with the existing > panel-jadard-jd9365da-h3 driver.Hence,we add a new compatible > with panel specific config. > > Although they have the same control IC, the two panels are different, > and the timing will be slightly different, so we added some variables > in struct jadard_panel_desc to control the timing > > Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> > --- > > Chage since V3: > - 1. Give up creating a new driver and re-add K&d kd101ne3-40ti > - configuration to the panel-jadard-jd9365da-h3.c driver. > > V2:https://lore.kernel.org/all/20240601084528.22502-3-lvzhaoxiong@huaqin.corp-partner.google.com/ > > Chage since V2: > > - 1. Use the new mipi_dsi_dcs_write_seq_multi() function. > - 2. Modify Move mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sleep_mode() to disable(), > - and drop kingdisplay_panel_enter_sleep_mode(). > - 3. If prepare fails, disable GPIO before regulators. > - 4. This function drm_connector_set_panel_orientation() is no longer used. Delete it. > - 5. Drop ".shutdown = kingdisplay_panel_shutdown". > > --- > .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 284 ++++++++++++++++++ > 1 file changed, 284 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > index b39f01d7002e..f6e130567707 100644 > --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c > @@ -27,6 +27,15 @@ struct jadard_panel_desc { > enum mipi_dsi_pixel_format format; > int (*init)(struct jadard *jadard); > u32 num_init_cmds; > + bool lp11_before_reset; > + bool power_off_vcioo_before_reset; > + unsigned int vcioo_to_lp11_delay; > + unsigned int lp11_to_reset_delay; > + unsigned int exit_sleep_to_display_on_delay; > + unsigned int display_on_delay; > + unsigned int backlight_off_to_display_off_delay; > + unsigned int display_off_to_enter_sleep_delay; > + unsigned int enter_sleep_to_reset_down_delay; > }; > > struct jadard { > @@ -57,10 +66,18 @@ static int jadard_enable(struct drm_panel *panel) > if (err < 0) > DRM_DEV_ERROR(dev, "failed to exit sleep mode ret = %d\n", err); > > + /* tSLPOUT >= 120ms */ The comments are probably applicable to your panel, but not to the other panels. > + if (jadard->desc->exit_sleep_to_display_on_delay) > + msleep(jadard->desc->exit_sleep_to_display_on_delay); Maybe extend mipi_dsi_msleep to skip slipping if delay is 0 and then use _multi here too? > + > err = mipi_dsi_dcs_set_display_on(dsi); > if (err < 0) > DRM_DEV_ERROR(dev, "failed to set display on ret = %d\n", err); > > + /* tDISON >= 20ms */ > + if (jadard->desc->display_on_delay) > + msleep(jadard->desc->display_on_delay); > + > return 0; > } > > @@ -70,14 +87,26 @@ static int jadard_disable(struct drm_panel *panel) > struct jadard *jadard = panel_to_jadard(panel); > int ret; > > + /* tBLOFF:Backlight_to_0x28h >= 100ms */ > + if (jadard->desc->backlight_off_to_display_off_delay) > + msleep(jadard->desc->backlight_off_to_display_off_delay); > + > ret = mipi_dsi_dcs_set_display_off(jadard->dsi); > if (ret < 0) > DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); > > + /* tDISOFF >= 50ms */ > + if (jadard->desc->display_off_to_enter_sleep_delay) > + msleep(jadard->desc->display_off_to_enter_sleep_delay); > + > ret = mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); > if (ret < 0) > DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); > > + /* tSLPIN >= 100ms */ > + if (jadard->desc->enter_sleep_to_reset_down_delay) > + msleep(jadard->desc->enter_sleep_to_reset_down_delay); > + > return 0; > } > > @@ -94,6 +123,21 @@ static int jadard_prepare(struct drm_panel *panel) > if (ret) > return ret; > > + /* tMIPI_ON >= 0ms */ > + if (jadard->desc->vcioo_to_lp11_delay) > + msleep(jadard->desc->vcioo_to_lp11_delay); > + > + if (jadard->desc->lp11_before_reset) { > + ret = mipi_dsi_dcs_nop(jadard->dsi); > + if (ret < 0) > + goto poweroff; > + > + usleep_range(1000, 2000); > + } > + /* tRPWIRES >= 5ms */ > + if (jadard->desc->lp11_to_reset_delay) > + msleep(jadard->desc->lp11_to_reset_delay); > + > gpiod_set_value(jadard->reset, 1); > msleep(5); > > @@ -125,6 +169,12 @@ static int jadard_unprepare(struct drm_panel *panel) > gpiod_set_value(jadard->reset, 1); > msleep(120); > > + if (jadard->desc->power_off_vcioo_before_reset) { > + gpiod_set_value(jadard->reset, 0); The implemented behaviour contradicts with the name of the flag. If the flag is set, then reset is down before powering down the vccio supply. > + > + usleep_range(1000, 2000); > + } > + > regulator_disable(jadard->vdd); > regulator_disable(jadard->vccio); > > @@ -586,7 +636,237 @@ static const struct jadard_panel_desc cz101b4001_desc = { > .lanes = 4, > .format = MIPI_DSI_FMT_RGB888, > .init = cz101b4001_init_cmds, > +}; > + [skipped] > + > +static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = { > + .mode = { > + .clock = 70595, Please change this to something like: (800 + 30 + 30 + 30) * (1280 + 30 + 4 + 8) * 60 / 1000 > + > + .hdisplay = 800, > + .hsync_start = 800 + 30, > + .hsync_end = 800 + 30 + 30, > + .htotal = 800 + 30 + 30 + 30, > + > + .vdisplay = 1280, > + .vsync_start = 1280 + 30, > + .vsync_end = 1280 + 30 + 4, > + .vtotal = 1280 + 30 + 4 + 8, > + > + .width_mm = 135, > + .height_mm = 216, > + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, > + }, > + .lanes = 4, > + .format = MIPI_DSI_FMT_RGB888, > + .init = kingdisplay_kd101ne3_init_cmds, > + .lp11_before_reset = true, > + .power_off_vcioo_before_reset = true, > + .vcioo_to_lp11_delay = 5, > + .lp11_to_reset_delay = 10, > + .exit_sleep_to_display_on_delay = 120, > + .display_on_delay = 20, > + .backlight_off_to_display_off_delay = 100, > + .display_off_to_enter_sleep_delay = 50, > + .enter_sleep_to_reset_down_delay = 100, > }; > > static int jadard_dsi_probe(struct mipi_dsi_device *dsi) > @@ -665,6 +945,10 @@ static const struct of_device_id jadard_of_match[] = { > .compatible = "radxa,display-8hd-ad002", > .data = &radxa_display_8hd_ad002_desc > }, > + { > + .compatible = "kingdisplay,kd101ne3-40ti", > + .data = &kingdisplay_kd101ne3_40ti_desc > + }, Keep it sorted, please. > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(of, jadard_of_match); > -- > 2.17.1 > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 4/4] drm/panel: jd9365da: Add the function of adjusting orientation 2024-06-14 14:55 [PATCH v3 0/4] Add kd101ne3-40ti configuration in driver jd9365da Zhaoxiong Lv ` (2 preceding siblings ...) 2024-06-14 14:55 ` [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel Zhaoxiong Lv @ 2024-06-14 14:55 ` Zhaoxiong Lv 3 siblings, 0 replies; 10+ messages in thread From: Zhaoxiong Lv @ 2024-06-14 14:55 UTC (permalink / raw) To: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, jikos, benjamin.tissoires, dianders, hsinyi Cc: dri-devel, devicetree, linux-kernel, Zhaoxiong Lv This driver does not have the function to adjust the orientation, so this function is added. Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com> --- drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index f6e130567707..7f86bb7f2299 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -42,7 +42,7 @@ struct jadard { struct drm_panel panel; struct mipi_dsi_device *dsi; const struct jadard_panel_desc *desc; - + enum drm_panel_orientation orientation; struct regulator *vdd; struct regulator *vccio; struct gpio_desc *reset; @@ -205,12 +205,20 @@ static int jadard_get_modes(struct drm_panel *panel, return 1; } +static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_panel *panel) +{ + struct jadard *jadard = panel_to_jadard(panel); + + return jadard->orientation; +} + static const struct drm_panel_funcs jadard_funcs = { .disable = jadard_disable, .unprepare = jadard_unprepare, .prepare = jadard_prepare, .enable = jadard_enable, .get_modes = jadard_get_modes, + .get_orientation = jadard_panel_get_orientation, }; static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) @@ -907,6 +915,12 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi) drm_panel_init(&jadard->panel, dev, &jadard_funcs, DRM_MODE_CONNECTOR_DSI); + ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation); + if (ret < 0) { + dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret); + return ret; + } + ret = drm_panel_of_backlight(&jadard->panel); if (ret) return ret; -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-06-15 10:06 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-06-14 14:55 [PATCH v3 0/4] Add kd101ne3-40ti configuration in driver jd9365da Zhaoxiong Lv 2024-06-14 14:55 ` [PATCH v3 1/4] drm/panel: jd9365da: Modify the method of sending commands Zhaoxiong Lv 2024-06-14 16:16 ` Dmitry Baryshkov 2024-06-14 17:09 ` Alex Bee 2024-06-14 14:55 ` [PATCH v3 2/4] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Zhaoxiong Lv 2024-06-14 16:34 ` Dmitry Baryshkov 2024-06-15 10:06 ` Krzysztof Kozlowski 2024-06-14 14:55 ` [PATCH v3 3/4] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel Zhaoxiong Lv 2024-06-14 17:05 ` Dmitry Baryshkov 2024-06-14 14:55 ` [PATCH v3 4/4] drm/panel: jd9365da: Add the function of adjusting orientation Zhaoxiong Lv
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