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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439922141a5sm35844685e9.2.2025.02.18.11.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 11:26:32 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 07/15] clk: sunxi-ng: a523: add video mod clocks Date: Tue, 18 Feb 2025 20:26:31 +0100 Message-ID: <9406479.CDJkKcVGEf@jernej-laptop> In-Reply-To: <20250214125359.5204-8-andre.przywara@arm.com> References: <20250214125359.5204-1-andre.przywara@arm.com> <20250214125359.5204-8-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne petek, 14. februar 2025 ob 13:53:51 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > Add the clocks driving the various video subsystems of the SoC: the "DE" > display engine, the "DI" deinterlacer, the "G2D" 2D graphics system, the > Mali "GPU", the "VE" video engine, its associated IOMMU, as well as the > clocks for the various video output drivers (HDMI, DP, LCDs). >=20 > Signed-off-by: Andre Przywara > --- > drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 219 +++++++++++++++++++++++++ > 1 file changed, 219 insertions(+) >=20 > diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-n= g/ccu-sun55i-a523.c > index 59f45e7c0904b..0ef1fd71a1ca5 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c > +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c > @@ -364,6 +364,192 @@ static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", = apb1_parents, 0x524, > 24, 3, /* mux */ > 0); > =20 > + > +/***********************************************************************= *** > + * mod clocks = * > + ***********************************************************************= ***/ > + > +static const struct clk_hw *de_parents[] =3D { > + &pll_periph0_300M_clk.hw, > + &pll_periph0_400M_clk.hw, > + &pll_video3_4x_clk.common.hw, > + &pll_video3_3x_clk.hw, > +}; > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static const struct clk_hw *di_parents[] =3D { > + &pll_periph0_300M_clk.hw, > + &pll_periph0_400M_clk.hw, > + &pll_video0_4x_clk.common.hw, > + &pll_video1_4x_clk.common.hw, > +}; > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0x620, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static const struct clk_hw *g2d_parents[] =3D { > + &pll_periph0_400M_clk.hw, > + &pll_periph0_300M_clk.hw, > + &pll_video0_4x_clk.common.hw, > + &pll_video1_4x_clk.common.hw, > +}; > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0x630, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const struct clk_hw *gpu_parents[] =3D { > + &pll_gpu_clk.common.hw, > + &pll_periph0_800M_clk.common.hw, > + &pll_periph0_600M_clk.hw, > + &pll_periph0_400M_clk.hw, > + &pll_periph0_300M_clk.hw, > + &pll_periph0_200M_clk.hw, > +}; > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, > + 0, 4, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); GPU clock should have CLK_SET_RATE_FLAG. > + > +static const struct clk_hw *ve_parents[] =3D { > + &pll_ve_clk.common.hw, > + &pll_periph0_480M_clk.common.hw, > + &pll_periph0_400M_clk.hw, > + &pll_periph0_300M_clk.hw, > +}; > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static const struct clk_parent_data iommu_parents[] =3D { > + { .hw =3D &pll_periph0_600M_clk.hw }, > + { .hw =3D &pll_ddr0_clk.common.hw }, > + { .hw =3D &pll_periph0_480M_clk.common.hw }, > + { .hw =3D &pll_periph0_400M_clk.hw }, > + { .hw =3D &pll_periph0_150M_clk.hw }, > + { .fw_name =3D "hosc" }, > +}; > + > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(iommu_clk, "iommu", iommu_parents,= 0x7b0, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); This won't work. IOMMU clock has also update bit, which must be set to actu= ally apply the new value, same as DDR clock. > + > +static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(= 31), 0); > + > +/* TODO: add mux between 32kOSC and PERIPH0/18750 */ Not sure what this TODO means. > +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", > + pll_periph0_2x_hws, > + 0xb10, BIT(30), 36621, 0); > + > +static const struct clk_parent_data hdmi_cec_parents[] =3D { > + { .fw_name =3D "losc" }, > + { .hw =3D &hdmi_cec_32k_clk.common.hw }, > +}; > +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_p= arents, > + 0xb10, > + 24, 1, /* mux */ > + BIT(31), /* gate */ > + 0); > + > +static const struct clk_parent_data mipi_dsi_parents[] =3D { > + { .fw_name =3D "hosc" }, > + { .hw =3D &pll_periph0_200M_clk.hw }, > + { .hw =3D &pll_periph0_150M_clk.hw }, > +}; > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi0_clk, "mipi-dsi0", > + mipi_dsi_parents, 0xb24, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi1_clk, "mipi-dsi1", > + mipi_dsi_parents, 0xb28, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static const struct clk_hw *tcon_parents[] =3D { > + &pll_video0_4x_clk.common.hw, > + &pll_video1_4x_clk.common.hw, > + &pll_video2_4x_clk.common.hw, > + &pll_video3_4x_clk.common.hw, > + &pll_periph0_2x_clk.common.hw, > + &pll_video0_3x_clk.hw, > + &pll_video1_3x_clk.hw, > +}; > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_par= ents, > + 0xb60, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_par= ents, > + 0xb64, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); Missing tcon-lcd2 - see T527 manual. > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi0_clk, "combophy-dsi0", > + tcon_parents, 0xb6c, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi1_clk, "combophy-dsi1", > + tcon_parents, 0xb70, > + 0, 5, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_paren= ts, > + 0xb80, > + 0, 4, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); > + > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_paren= ts, > + 0xb84, > + 0, 4, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + CLK_SET_RATE_PARENT); TCON TV0-1 parents are subset of others, according to T527 manual. > + > +static const struct clk_hw *edp_parents[] =3D { > + &pll_video0_4x_clk.common.hw, > + &pll_video1_4x_clk.common.hw, > + &pll_video2_4x_clk.common.hw, > + &pll_video3_4x_clk.common.hw, > + &pll_periph0_2x_clk.common.hw, > +}; > +static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_clk, "edp", edp_parents, 0xbb0, > + 0, 4, /* M */ > + 24, 3, /* mux */ > + BIT(31), /* gate */ > + 0); > + Missing CLK_SET_RATE_PARENT flag. Best regards, Jernej > /* > * Contains all clocks that are controlled by a hardware register. They > * have a (sunxi) .common member, which needs to be initialised by the c= ommon > @@ -394,6 +580,22 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D= { > &ahb_clk.common, > &apb0_clk.common, > &apb1_clk.common, > + &de_clk.common, > + &di_clk.common, > + &g2d_clk.common, > + &gpu_clk.common, > + &ve_clk.common, > + &iommu_clk.common, > + &hdmi_24M_clk.common, > + &hdmi_cec_32k_clk.common, > + &hdmi_cec_clk.common, > + &mipi_dsi0_clk.common, > + &mipi_dsi1_clk.common, > + &tcon_lcd0_clk.common, > + &tcon_lcd1_clk.common, > + &tcon_tv0_clk.common, > + &tcon_tv1_clk.common, > + &edp_clk.common, > }; > =20 > static struct clk_hw_onecell_data sun55i_a523_hw_clks =3D { > @@ -442,6 +644,23 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clk= s =3D { > [CLK_AHB] =3D &ahb_clk.common.hw, > [CLK_APB0] =3D &apb0_clk.common.hw, > [CLK_APB1] =3D &apb1_clk.common.hw, > + [CLK_DE] =3D &de_clk.common.hw, > + [CLK_DI] =3D &di_clk.common.hw, > + [CLK_G2D] =3D &g2d_clk.common.hw, > + [CLK_GPU] =3D &gpu_clk.common.hw, > + [CLK_VE] =3D &ve_clk.common.hw, > + [CLK_HDMI_24M] =3D &hdmi_24M_clk.common.hw, > + [CLK_HDMI_CEC_32K] =3D &hdmi_cec_32k_clk.common.hw, > + [CLK_HDMI_CEC] =3D &hdmi_cec_clk.common.hw, > + [CLK_MIPI_DSI0] =3D &mipi_dsi0_clk.common.hw, > + [CLK_MIPI_DSI1] =3D &mipi_dsi1_clk.common.hw, > + [CLK_TCON_LCD0] =3D &tcon_lcd0_clk.common.hw, > + [CLK_TCON_LCD1] =3D &tcon_lcd1_clk.common.hw, > + [CLK_COMBOPHY_DSI0] =3D &combophy_dsi0_clk.common.hw, > + [CLK_COMBOPHY_DSI1] =3D &combophy_dsi1_clk.common.hw, > + [CLK_TCON_TV0] =3D &tcon_tv0_clk.common.hw, > + [CLK_TCON_TV1] =3D &tcon_tv1_clk.common.hw, > + [CLK_EDP] =3D &edp_clk.common.hw, > }, > }; > =20 >=20