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([2a01:e0a:3d9:2080:4144:6a84:fe1d:3aae]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e2446b0sm45162715e9.21.2025.06.13.02.12.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jun 2025 02:12:27 -0700 (PDT) Message-ID: <9455a4e1-6352-4832-ac9f-2816f889c3a4@linaro.org> Date: Fri, 13 Jun 2025 11:12:26 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH v3 9/9] arm64: dts: exynos: ExynosAutov920: add USB and USB SS combo phy nodes To: Pritam Manohar Sutar , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com References: <20250613055613.866909-1-pritam.sutar@samsung.com> <20250613055613.866909-10-pritam.sutar@samsung.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 13/06/2025 07:56, Pritam Manohar Sutar wrote: > Update the USB 3.1 DRD controller and USB31DRD phy nodes to support > SS combo phy for this soc. > > The USB 3.1 DRD controller has the following features: > * DWC3 compatible > * compliant with both USB device 3.1 and USB device 2.0 standards > * compliant with USB host 3.1 and USB host 2.0 standards > * supports USB device 3.1 and USB device 2.0 interfaces > * supports USB host 3.1 and USB host 2.0 interfaces > * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device > 2.0 interface > * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface > * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface > * single USB port which can be used for USB 3.1 or USB 2.0 > * on-chip USB PHY transceiver > * supports up to 16 bi-directional endpoints > * compliant with xHCI 1.1 specification > > USB3.1 SSP+(10Gbps) is supported in this commit and SS phy in combo > phy only supports PIPE3 interface and it is added in index 0 of SS phy. > UTMI+ and PIPE3 PHY interfaces are specified in "phys" property, > UTMI+ (index 0 HS phy) and PIPE3 (index 0 SS phy). > > Signed-off-by: Pritam Manohar Sutar > --- > .../arm64/boot/dts/exynos/exynosautov920-sadk.dts | 4 ++++ > arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++-- > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > index a21386bd9af3..40588f7c9998 100644 > --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > @@ -88,6 +88,10 @@ &xtcxo { > }; > > /* usb */ > +&usbdrd31_ssphy { > + status = "okay"; > +}; > + > &usbdrd31_hsphy { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > index 4efc005cae80..5ee7fad346b9 100644 > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > @@ -1048,6 +1048,17 @@ pinctrl_hsi1: pinctrl@16450000 { > interrupts = ; > }; > > + usbdrd31_ssphy: phy@16480000 { > + compatible = "samsung,exynosautov920-usb31drd-ssphy"; > + reg = <0x16480000 0x0200>; > + clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, > + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; > + clock-names = "phy", "ref"; > + #phy-cells = <1>; > + samsung,pmu-syscon = <&pmu_system_controller>; > + status = "disabled"; > + }; > + > usbdrd31_hsphy: phy@16490000 { > compatible = "samsung,exynosautov920-usbdrd-hsphy"; > reg = <0x16490000 0x0200>; > @@ -1109,8 +1120,8 @@ usbdrd31_dwc3: usb@0 { > <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; > clock-names = "ref", "susp_clk"; > interrupts = ; > - phys = <&usbdrd31_hsphy 0>; > - phy-names = "usb2-phy"; > + phys = <&usbdrd31_hsphy 0>, <&usbdrd31_ssphy 0>; > + phy-names = "usb2-phy", "usb3-phy"; > snps,has-lpm-erratum; > snps,dis_u2_susphy_quirk; > snps,dis_u3_susphy_quirk; I think at least patch 6 & 9 should be squashed. Neil