[PATCH 0/6] drm/panel: nv3052c: Add support for new Anbernic panels

[PATCH 0/6] drm/panel: nv3052c: Add support for new Anbernic panels

[Hironori KIKUCHI]

Add support for new panels used in the Anbernic RG XX series.

This patch series adds:
* YLM-LBV0345001H-V2 `anbernic,rg35xx-plus-rev6-panel`, for the RG35XX Plus (Rev6)
* YLM-LBV0400001X-V1 `anbernic,rg40xx-panel`, for the RG40XX series
* YLM-LBN0395004H-V1 `anbernic,rgcubexx-panel`, for the RG CubeXX

Hironori KIKUCHI (6):
  dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)
  drm: panel: nv3052c: Add another panel for RG35XX Plus (Rev6)
  dt-bindings: display: panel: Add a panel for RG40XX series
  drm: panel: nv3052c: Add a panel for RG40XX series
  dt-bindings: display: panel: Add a panel for RG CubeXX
  drm: panel: nv3052c: Add a panel for RG CubeXX

 .../anbernic,rg35xx-plus-rev6-panel.yaml      |  60 ++
 .../display/panel/anbernic,rg40xx-panel.yaml  |  60 ++
 .../panel/anbernic,rgcubexx-panel.yaml        |  60 ++
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 588 ++++++++++++++++++
 4 files changed, 768 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
 create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml
 create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml

-- 
2.47.0

[PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Hironori KIKUCHI]

This is a display panel used in the recent revision of the Anbernic
RG35XX Plus, a handheld gaming device from Anbernic.
It is 3.45 inches in size (diagonally) with a resolution of 640x480.

It has the same interface (pins and connector) as the panel of the former
revision of RG35XX Plus, but they differ in their init-sequence. So add
it as a new panel.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
---
 .../anbernic,rg35xx-plus-rev6-panel.yaml      | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml

diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
new file mode 100644
index 00000000000..b60a4cf00f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Anbernic RG35XX series (YLM-LBV0345001H-V2) 3.45" 640x480 24-bit IPS LCD panel
+
+maintainers:
+  - Hironori KIKUCHI <kikuchan98@gmail.com>
+
+allOf:
+  - $ref: panel-common.yaml#
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: anbernic,rg35xx-plus-rev6-panel
+
+  reg:
+    maxItems: 1
+
+  spi-3wire: true
+
+required:
+  - compatible
+  - reg
+  - port
+  - power-supply
+  - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        panel@0 {
+            compatible = "anbernic,rg35xx-plus-rev6-panel";
+            reg = <0>;
+
+            spi-3wire;
+            spi-max-frequency = <3125000>;
+
+            reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
+
+            backlight = <&backlight>;
+            power-supply = <&reg_lcd>;
+
+            port {
+                endpoint {
+                    remote-endpoint = <&tcon_lcd0_out_lcd>;
+                };
+            };
+        };
+    };
-- 
2.47.0

[PATCH 2/6] drm: panel: nv3052c: Add another panel for RG35XX Plus (Rev6)

[Hironori KIKUCHI]

This is a display panel used in the recent revision of the Anbernic
RG35XX Plus, a handheld gaming device from Anbernic.
It is 3.45 inches in size (diagonally) with a resolution of 640x480.

It has the same interface (pins and connector) as the panel of the former
revision of RG35XX Plus, but they differ in their init-sequence. So add
it as a new panel.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 178 ++++++++++++++++++
 1 file changed, 178 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 06e16a7c14a..166393ccfed 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -629,6 +629,156 @@ static const struct nv3052c_reg wl_355608_a8_panel_regs[] = {
 	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
 };
 
+static const struct nv3052c_reg ylm_lbv0345001h_v2_panel_regs[] = {
+	// EXTC Command set enable, select page 1
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+	// Mostly unknown registers
+	{ 0xe3, 0x00 },
+	{ 0x0a, 0x01 },
+	{ 0x23, 0x00 }, // RGB interface control: DE+SYNC MODE PCLK-N
+	{ 0x24, 0x10 },
+	{ 0x25, 0x09 },
+	{ 0x28, 0x47 },
+	{ 0x29, 0x01 },
+	{ 0x2a, 0xdf },
+	{ 0x38, 0x9c }, // VCOM_ADJ1
+	{ 0x39, 0xa7 }, // VCOM_ADJ2
+	{ 0x3a, 0x3f }, // VCOM_ADJ3
+	{ 0x91, 0x77 }, // EXTPW_CTRL2
+	{ 0x92, 0x77 }, // EXTPW_CTRL3
+	{ 0xa0, 0x55 },
+	{ 0xa1, 0x50 },
+	{ 0xa4, 0x9c },
+	{ 0xa7, 0x02 },
+	{ 0xa8, 0x01 },
+	{ 0xa9, 0x01 },
+	{ 0xaa, 0xfc },
+	{ 0xab, 0x28 },
+	{ 0xac, 0x06 },
+	{ 0xad, 0x06 },
+	{ 0xae, 0x06 },
+	{ 0xaf, 0x03 },
+	{ 0xb0, 0x08 },
+	{ 0xb1, 0x26 },
+	{ 0xb2, 0x28 },
+	{ 0xb3, 0x28 },
+	{ 0xb4, 0x03 },
+	{ 0xb5, 0x08 },
+	{ 0xb6, 0x26 },
+	{ 0xb7, 0x08 },
+	{ 0xb8, 0x26 },
+	// EXTC Command set enable, select page 2
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Set gray scale voltage to adjust gamma
+	{ 0xb0, 0x02 }, // PGAMVR0
+	{ 0xb1, 0x0f }, // PGAMVR1
+	{ 0xb2, 0x11 }, // PGAMVR2
+	{ 0xb3, 0x32 }, // PGAMVR3
+	{ 0xb4, 0x36 }, // PGAMVR4
+	{ 0xb5, 0x3c }, // PGAMVR5
+	{ 0xb6, 0x20 }, // PGAMPR0
+	{ 0xb7, 0x3e }, // PGAMPR1
+	{ 0xb8, 0x0e }, // PGAMPK0
+	{ 0xb9, 0x05 }, // PGAMPK1
+	{ 0xba, 0x11 }, // PGAMPK2
+	{ 0xbb, 0x11 }, // PGAMPK3
+	{ 0xbc, 0x13 }, // PGAMPK4
+	{ 0xbd, 0x14 }, // PGAMPK5
+	{ 0xbe, 0x16 }, // PGAMPK6
+	{ 0xbf, 0x0e }, // PGAMPK7
+	{ 0xc0, 0x17 }, // PGAMPK8
+	{ 0xc1, 0x07 }, // PGAMPK9
+	{ 0xd0, 0x02 }, // NGAMVR0
+	{ 0xd1, 0x10 }, // NGAMVR0
+	{ 0xd2, 0x12 }, // NGAMVR1
+	{ 0xd3, 0x33 }, // NGAMVR2
+	{ 0xd4, 0x36 }, // NGAMVR3
+	{ 0xd5, 0x3c }, // NGAMVR4
+	{ 0xd6, 0x20 }, // NGAMPR0
+	{ 0xd7, 0x3e }, // NGAMPR1
+	{ 0xd8, 0x0d }, // NGAMPK0
+	{ 0xd9, 0x05 }, // NGAMPK1
+	{ 0xda, 0x12 }, // NGAMPK2
+	{ 0xdb, 0x11 }, // NGAMPK3
+	{ 0xdc, 0x14 }, // NGAMPK4
+	{ 0xdd, 0x14 }, // NGAMPK5
+	{ 0xde, 0x18 }, // NGAMPK6
+	{ 0xdf, 0x0f }, // NGAMPK7
+	{ 0xe0, 0x17 }, // NGAMPK8
+	{ 0xe1, 0x08 }, // NGAMPK9
+	// EXTC Command set enable, select page 3
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
+	// Set various timing settings
+	{ 0x07, 0x03 }, // GIP_VST_8
+	{ 0x08, 0x00 }, // GIP_VST_9
+	{ 0x09, 0x01 }, // GIP_VST_10
+	{ 0x30, 0x00 }, // GIP_CLK_1
+	{ 0x31, 0x00 }, // GIP_CLK_2
+	{ 0x32, 0x00 }, // GIP_CLK_3
+	{ 0x33, 0x00 }, // GIP_CLK_4
+	{ 0x34, 0x61 }, // GIP_CLK_5
+	{ 0x35, 0xd4 }, // GIP_CLK_6
+	{ 0x36, 0x24 }, // GIP_CLK_7
+	{ 0x37, 0x03 }, // GIP_CLK_8
+	{ 0x40, 0x02 }, // GIP_CLKA_1
+	{ 0x41, 0x03 }, // GIP_CLKA_2
+	{ 0x42, 0x04 }, // GIP_CLKA_3
+	{ 0x43, 0x05 }, // GIP_CLKA_4
+	{ 0x44, 0x11 }, // GIP_CLKA_5
+	{ 0x45, 0xe6 }, // GIP_CLKA_6
+	{ 0x46, 0xe7 }, // GIP_CLKA_7
+	{ 0x47, 0x11 }, // GIP_CLKA_8
+	{ 0x48, 0xe8 }, // GIP_CLKA_9
+	{ 0x49, 0xe9 }, // GIP_CLKA_10
+	{ 0x50, 0x06 }, // GIP_CLKB_1
+	{ 0x51, 0x07 }, // GIP_CLKB_2
+	{ 0x52, 0x08 }, // GIP_CLKB_3
+	{ 0x53, 0x09 }, // GIP_CLKB_4
+	{ 0x54, 0x11 }, // GIP_CLKB_5
+	{ 0x55, 0xea }, // GIP_CLKB_6
+	{ 0x56, 0xeb }, // GIP_CLKB_7
+	{ 0x57, 0x11 }, // GIP_CLKB_8
+	{ 0x58, 0xec }, // GIP_CLKB_9
+	{ 0x59, 0xed }, // GIP_CLKB_10
+	// Map internal GOA signals to GOA output pad
+	{ 0x82, 0x00 }, // PANELU2D3
+	{ 0x83, 0x00 }, // PANELU2D4
+	{ 0x84, 0x02 }, // PANELU2D5
+	{ 0x85, 0x00 }, // PANELU2D6
+	{ 0x86, 0x1f }, // PANELU2D7
+	{ 0x87, 0x00 }, // PANELU2D8
+	{ 0x88, 0x1f }, // PANELU2D9
+	{ 0x89, 0x0e }, // PANELU2D10
+	{ 0x8a, 0x0e }, // PANELU2D11
+	{ 0x8b, 0x10 }, // PANELU2D12
+	{ 0x8c, 0x10 }, // PANELU2D13
+	{ 0x8d, 0x0a }, // PANELU2D14
+	{ 0x8e, 0x0a }, // PANELU2D15
+	{ 0x8f, 0x0c }, // PANELU2D16
+	{ 0x90, 0x0c }, // PANELU2D17
+	{ 0x98, 0x00 }, // PANELU2D25
+	{ 0x99, 0x00 }, // PANELU2D26
+	{ 0x9a, 0x01 }, // PANELU2D27
+	{ 0x9b, 0x00 }, // PANELU2D28
+	{ 0x9c, 0x1f }, // PANELU2D29
+	{ 0x9d, 0x00 }, // PANELU2D30
+	{ 0x9e, 0x1f }, // PANELU2D31
+	{ 0x9f, 0x0d }, // PANELU2D32
+	{ 0xa0, 0x0d }, // PANELU2D33
+	{ 0xa1, 0x0f }, // PANELU2D34
+	{ 0xa2, 0x0f }, // PANELU2D35
+	{ 0xa3, 0x09 }, // PANELU2D36
+	{ 0xa4, 0x09 }, // PANELU2D37
+	{ 0xa5, 0x0b }, // PANELU2D38
+	{ 0xa6, 0x0b }, // PANELU2D39
+	// EXTC Command set enable, select page 0
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
+	// Interface Pixel Format
+	{ 0x3a, 0x77 },
+	// Display Access Control
+	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
+};
+
 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
 {
 	return container_of(panel, struct nv3052c, panel);
@@ -881,6 +1031,21 @@ static const struct drm_display_mode wl_355608_a8_mode[] = {
 	},
 };
 
+static const struct drm_display_mode ylm_lbv0345001h_v2_mode[] = {
+	{
+		.clock = 24000,
+		.hdisplay = 640,
+		.hsync_start = 640 + 84,
+		.hsync_end = 640 + 84 + 20,
+		.htotal = 640 + 84 + 20 + 26,
+		.vdisplay = 480,
+		.vsync_start = 480 + 32,
+		.vsync_end = 480 + 32 + 4,
+		.vtotal = 480 + 32 + 4 + 5,
+		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+	},
+};
+
 static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.display_modes = ltk035c5444t_modes,
 	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
@@ -914,10 +1079,22 @@ static const struct nv3052c_panel_info wl_355608_a8_panel_info = {
 	.panel_regs_len = ARRAY_SIZE(wl_355608_a8_panel_regs),
 };
 
+static const struct nv3052c_panel_info ylm_lbv0345001h_v2_panel_info = {
+	.display_modes = ylm_lbv0345001h_v2_mode,
+	.num_modes = ARRAY_SIZE(ylm_lbv0345001h_v2_mode),
+	.width_mm = 70,
+	.height_mm = 53,
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.panel_regs = ylm_lbv0345001h_v2_panel_regs,
+	.panel_regs_len = ARRAY_SIZE(ylm_lbv0345001h_v2_panel_regs),
+};
+
 static const struct spi_device_id nv3052c_ids[] = {
 	{ "ltk035c5444t", },
 	{ "fs035vg158", },
 	{ "rg35xx-plus-panel", },
+	{ "rg35xx-plus-rev6-panel", },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(spi, nv3052c_ids);
@@ -926,6 +1103,7 @@ static const struct of_device_id nv3052c_of_match[] = {
 	{ .compatible = "leadtek,ltk035c5444t", .data = &ltk035c5444t_panel_info },
 	{ .compatible = "fascontek,fs035vg158", .data = &fs035vg158_panel_info },
 	{ .compatible = "anbernic,rg35xx-plus-panel", .data = &wl_355608_a8_panel_info },
+	{ .compatible = "anbernic,rg35xx-plus-rev6-panel", .data = &ylm_lbv0345001h_v2_panel_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, nv3052c_of_match);
-- 
2.47.0

[PATCH 3/6] dt-bindings: display: panel: Add a panel for RG40XX series

[Hironori KIKUCHI]

This is a display panel used in the Anbernic RG40XX series (H and V),
a handheld gaming device from Anbernic. It is 4.00 inches in size
(diagonally) with a resolution of 640x480.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
---
 .../display/panel/anbernic,rg40xx-panel.yaml  | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml

diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml
new file mode 100644
index 00000000000..bec5363e1d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/anbernic,rg40xx-panel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Anbernic RG40XX series (YLM-LBV0400001X-V1) 4.00" 640x480 24-bit IPS LCD panel
+
+maintainers:
+  - Hironori KIKUCHI <kikuchan98@gmail.com>
+
+allOf:
+  - $ref: panel-common.yaml#
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: anbernic,rg40xx-panel
+
+  reg:
+    maxItems: 1
+
+  spi-3wire: true
+
+required:
+  - compatible
+  - reg
+  - port
+  - power-supply
+  - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        panel@0 {
+            compatible = "anbernic,rg40xx-panel";
+            reg = <0>;
+
+            spi-3wire;
+            spi-max-frequency = <3125000>;
+
+            reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
+
+            backlight = <&backlight>;
+            power-supply = <&reg_lcd>;
+
+            port {
+                endpoint {
+                    remote-endpoint = <&tcon_lcd0_out_lcd>;
+                };
+            };
+        };
+    };
-- 
2.47.0

[PATCH 4/6] drm: panel: nv3052c: Add a panel for RG40XX series

[Hironori KIKUCHI]

This is a display panel used in the Anbernic RG40XX series (H and V),
a handheld gaming device from Anbernic. It is 4.00 inches in size
(diagonally) with a resolution of 640x480.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 212 ++++++++++++++++++
 1 file changed, 212 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 166393ccfed..5a7cf6cb8be 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -779,6 +779,190 @@ static const struct nv3052c_reg ylm_lbv0345001h_v2_panel_regs[] = {
 	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
 };
 
+static const struct nv3052c_reg ylm_lbv0400001x_v1_panel_regs[] = {
+	// EXTC Command set enable, select page 1
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+	// Mostly unknown registers
+	{ 0xe3, 0x00 },
+	{ 0x0a, 0x01 }, // WRMADC_EN
+	{ 0x23, 0x00 }, // RGB interface control: DE+SYNC MODE PCLK-N
+	{ 0x25, 0x14 },
+	{ 0x28, 0x47 },
+	{ 0x29, 0x01 },
+	{ 0x2a, 0xdf },
+	{ 0x38, 0x9c }, // VCOM_ADJ1
+	{ 0x39, 0xa7 }, // VCOM_ADJ2
+	{ 0x3a, 0x47 }, // VCOM_ADJ3
+	{ 0x91, 0x77 }, // EXTPW_CTRL2
+	{ 0x92, 0x77 }, // EXTPW_CTRL3
+	{ 0x99, 0x52 }, // PUMP_CTRL2
+	{ 0x9b, 0x5b }, // PUMP_CTRL4
+	{ 0xa0, 0x55 },
+	{ 0xa1, 0x50 },
+	{ 0xa4, 0x9c },
+	{ 0xa7, 0x02 },
+	{ 0xa8, 0x01 },
+	{ 0xa9, 0x01 },
+	{ 0xaa, 0xfc },
+	{ 0xab, 0x28 },
+	{ 0xac, 0x06 },
+	{ 0xad, 0x06 },
+	{ 0xae, 0x06 },
+	{ 0xaf, 0x03 },
+	{ 0xb0, 0x08 },
+	{ 0xb1, 0x26 },
+	{ 0xb2, 0x28 },
+	{ 0xb3, 0x28 },
+	{ 0xb4, 0x03 },
+	{ 0xb5, 0x08 },
+	{ 0xb6, 0x26 },
+	{ 0xb7, 0x08 },
+	{ 0xb8, 0x26 },
+	// EXTC Command set enable, select page 2
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Set gray scale voltage to adjust gamma
+	{ 0xb0, 0x05 }, // PGAMVR0
+	{ 0xb1, 0x12 }, // PGAMVR1
+	{ 0xb2, 0x13 }, // PGAMVR2
+	{ 0xb3, 0x2c }, // PGAMVR3
+	{ 0xb4, 0x2a }, // PGAMVR4
+	{ 0xb5, 0x37 }, // PGAMVR5
+	{ 0xb6, 0x27 }, // PGAMPR0
+	{ 0xb7, 0x42 }, // PGAMPR1
+	{ 0xb8, 0x0f }, // PGAMPK0
+	{ 0xb9, 0x06 }, // PGAMPK1
+	{ 0xba, 0x12 }, // PGAMPK2
+	{ 0xbb, 0x12 }, // PGAMPK3
+	{ 0xbc, 0x13 }, // PGAMPK4
+	{ 0xbd, 0x15 }, // PGAMPK5
+	{ 0xbe, 0x1b }, // PGAMPK6
+	{ 0xbf, 0x14 }, // PGAMPK7
+	{ 0xc0, 0x1d }, // PGAMPK8
+	{ 0xc1, 0x09 }, // PGAMPK9
+	{ 0xd0, 0x02 }, // NGAMVR0
+	{ 0xd1, 0x1c }, // NGAMVR0
+	{ 0xd2, 0x1d }, // NGAMVR1
+	{ 0xd3, 0x36 }, // NGAMVR2
+	{ 0xd4, 0x34 }, // NGAMVR3
+	{ 0xd5, 0x32 }, // NGAMVR4
+	{ 0xd6, 0x25 }, // NGAMPR0
+	{ 0xd7, 0x40 }, // NGAMPR1
+	{ 0xd8, 0x0d }, // NGAMPK0
+	{ 0xd9, 0x04 }, // NGAMPK1
+	{ 0xda, 0x12 }, // NGAMPK2
+	{ 0xdb, 0x12 }, // NGAMPK3
+	{ 0xdc, 0x13 }, // NGAMPK4
+	{ 0xdd, 0x15 }, // NGAMPK5
+	{ 0xde, 0x15 }, // NGAMPK6
+	{ 0xdf, 0x0c }, // NGAMPK7
+	{ 0xe0, 0x13 }, // NGAMPK8
+	{ 0xe1, 0x07 }, // NGAMPK9
+	// EXTC Command set enable, select page 3
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
+	// Set various timing settings
+	{ 0x08, 0x0a }, // GIP_VST_9
+	{ 0x09, 0x0b }, // GIP_VST_10
+	{ 0x30, 0x00 }, // GIP_CLK_1
+	{ 0x31, 0x00 }, // GIP_CLK_2
+	{ 0x32, 0x00 }, // GIP_CLK_3
+	{ 0x33, 0x00 }, // GIP_CLK_4
+	{ 0x34, 0x61 }, // GIP_CLK_5
+	{ 0x35, 0xd4 }, // GIP_CLK_6
+	{ 0x36, 0x24 }, // GIP_CLK_7
+	{ 0x37, 0x03 }, // GIP_CLK_8
+	{ 0x40, 0x0d }, // GIP_CLKA_1
+	{ 0x41, 0x0e }, // GIP_CLKA_2
+	{ 0x42, 0x0f }, // GIP_CLKA_3
+	{ 0x43, 0x10 }, // GIP_CLKA_4
+	{ 0x44, 0x11 }, // GIP_CLKA_5
+	{ 0x45, 0xf4 }, // GIP_CLKA_6
+	{ 0x46, 0xf5 }, // GIP_CLKA_7
+	{ 0x47, 0x11 }, // GIP_CLKA_8
+	{ 0x48, 0xf6 }, // GIP_CLKA_9
+	{ 0x49, 0xf7 }, // GIP_CLKA_10
+	{ 0x50, 0x11 }, // GIP_CLKB_1
+	{ 0x51, 0x12 }, // GIP_CLKB_2
+	{ 0x52, 0x13 }, // GIP_CLKB_3
+	{ 0x53, 0x14 }, // GIP_CLKB_4
+	{ 0x54, 0x11 }, // GIP_CLKB_5
+	{ 0x55, 0xf8 }, // GIP_CLKB_6
+	{ 0x56, 0xf9 }, // GIP_CLKB_7
+	{ 0x57, 0x11 }, // GIP_CLKB_8
+	{ 0x58, 0xfa }, // GIP_CLKB_9
+	{ 0x59, 0xfb }, // GIP_CLKB_10
+	{ 0x60, 0x05 }, // GIP_CLKC_1
+	{ 0x61, 0x05 }, // GIP_CLKC_2
+	{ 0x65, 0x0a }, // GIP_CLKC_6
+	{ 0x66, 0x0a }, // GIP_CLKC_7
+	// Map internal GOA signals to GOA output pad
+	{ 0x82, 0x1e }, // PANELU2D3
+	{ 0x83, 0x1f }, // PANELU2D4
+	{ 0x84, 0x11 }, // PANELU2D5
+	{ 0x85, 0x02 }, // PANELU2D6
+	{ 0x86, 0x1e }, // PANELU2D7
+	{ 0x87, 0x1e }, // PANELU2D8
+	{ 0x88, 0x1f }, // PANELU2D9
+	{ 0x89, 0x0e }, // PANELU2D10
+	{ 0x8a, 0x0e }, // PANELU2D11
+	{ 0x8b, 0x10 }, // PANELU2D12
+	{ 0x8c, 0x10 }, // PANELU2D13
+	{ 0x8d, 0x0a }, // PANELU2D14
+	{ 0x8e, 0x0a }, // PANELU2D15
+	{ 0x8f, 0x0c }, // PANELU2D16
+	{ 0x90, 0x0c }, // PANELU2D17
+	{ 0x98, 0x1e }, // PANELU2D25
+	{ 0x99, 0x1f }, // PANELU2D26
+	{ 0x9a, 0x11 }, // PANELU2D27
+	{ 0x9b, 0x01 }, // PANELU2D28
+	{ 0x9c, 0x1e }, // PANELU2D29
+	{ 0x9d, 0x1e }, // PANELU2D30
+	{ 0x9e, 0x1f }, // PANELU2D31
+	{ 0x9f, 0x0d }, // PANELU2D32
+	{ 0xa0, 0x0d }, // PANELU2D33
+	{ 0xa1, 0x0f }, // PANELU2D34
+	{ 0xa2, 0x0f }, // PANELU2D35
+	{ 0xa3, 0x09 }, // PANELU2D36
+	{ 0xa4, 0x09 }, // PANELU2D37
+	{ 0xa5, 0x0b }, // PANELU2D38
+	{ 0xa6, 0x0b }, // PANELU2D39
+	{ 0xb2, 0x1f }, // PANELD2U3
+	{ 0xb3, 0x1e }, // PANELD2U4
+	{ 0xb4, 0x11 }, // PANELD2U5
+	{ 0xb5, 0x01 }, // PANELD2U6
+	{ 0xb6, 0x1e }, // PANELD2U7
+	{ 0xb7, 0x1e }, // PANELD2U8
+	{ 0xb8, 0x1f }, // PANELD2U9
+	{ 0xb9, 0x0b }, // PANELD2U10
+	{ 0xba, 0x0b }, // PANELD2U11
+	{ 0xbb, 0x09 }, // PANELD2U12
+	{ 0xbc, 0x09 }, // PANELD2U13
+	{ 0xbd, 0x0f }, // PANELD2U14
+	{ 0xbe, 0x0f }, // PANELD2U15
+	{ 0xbf, 0x0d }, // PANELD2U16
+	{ 0xc0, 0x0d }, // PANELD2U17
+	{ 0xc8, 0x1f }, // PANELD2U25
+	{ 0xc9, 0x1e }, // PANELD2U26
+	{ 0xca, 0x11 }, // PANELD2U27
+	{ 0xcb, 0x02 }, // PANELD2U28
+	{ 0xcc, 0x1e }, // PANELD2U29
+	{ 0xcd, 0x1e }, // PANELD2U30
+	{ 0xce, 0x1f }, // PANELD2U31
+	{ 0xcf, 0x0c }, // PANELD2U32
+	{ 0xd0, 0x0c }, // PANELD2U33
+	{ 0xd1, 0x0a }, // PANELD2U34
+	{ 0xd2, 0x0a }, // PANELD2U35
+	{ 0xd3, 0x10 }, // PANELD2U36
+	{ 0xd4, 0x10 }, // PANELD2U37
+	{ 0xd5, 0x0e }, // PANELD2U38
+	{ 0xd6, 0x0e }, // PANELD2U39
+	// EXTC Command set enable, select page 0
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
+	// Interface Pixel Format
+	{ 0x3a, 0x77 },
+	// Display Access Control
+	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
+};
+
 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
 {
 	return container_of(panel, struct nv3052c, panel);
@@ -1046,6 +1230,21 @@ static const struct drm_display_mode ylm_lbv0345001h_v2_mode[] = {
 	},
 };
 
+static const struct drm_display_mode ylm_lbv0400001x_v1_mode[] = {
+	{
+		.clock = 24000,
+		.hdisplay = 640,
+		.hsync_start = 640 + 84,
+		.hsync_end = 640 + 84 + 20,
+		.htotal = 640 + 84 + 20 + 26,
+		.vdisplay = 480,
+		.vsync_start = 480 + 20,
+		.vsync_end = 480 + 20 + 4,
+		.vtotal = 480 + 20 + 4 + 16,
+		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+	},
+};
+
 static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.display_modes = ltk035c5444t_modes,
 	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
@@ -1090,11 +1289,23 @@ static const struct nv3052c_panel_info ylm_lbv0345001h_v2_panel_info = {
 	.panel_regs_len = ARRAY_SIZE(ylm_lbv0345001h_v2_panel_regs),
 };
 
+static const struct nv3052c_panel_info ylm_lbv0400001x_v1_panel_info = {
+	.display_modes = ylm_lbv0400001x_v1_mode,
+	.num_modes = ARRAY_SIZE(ylm_lbv0400001x_v1_mode),
+	.width_mm = 81,
+	.height_mm = 61,
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.panel_regs = ylm_lbv0400001x_v1_panel_regs,
+	.panel_regs_len = ARRAY_SIZE(ylm_lbv0400001x_v1_panel_regs),
+};
+
 static const struct spi_device_id nv3052c_ids[] = {
 	{ "ltk035c5444t", },
 	{ "fs035vg158", },
 	{ "rg35xx-plus-panel", },
 	{ "rg35xx-plus-rev6-panel", },
+	{ "rg40xx-panel", },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(spi, nv3052c_ids);
@@ -1104,6 +1315,7 @@ static const struct of_device_id nv3052c_of_match[] = {
 	{ .compatible = "fascontek,fs035vg158", .data = &fs035vg158_panel_info },
 	{ .compatible = "anbernic,rg35xx-plus-panel", .data = &wl_355608_a8_panel_info },
 	{ .compatible = "anbernic,rg35xx-plus-rev6-panel", .data = &ylm_lbv0345001h_v2_panel_info },
+	{ .compatible = "anbernic,rg40xx-panel", .data = &ylm_lbv0400001x_v1_panel_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, nv3052c_of_match);
-- 
2.47.0

[PATCH 5/6] dt-bindings: display: panel: Add a panel for RG CubeXX

[Hironori KIKUCHI]

This is a display panel used in the Anbernic RG CubeXX, a handheld
gaming device from Anbernic. It is 3.95 inches in size (diagonally)
with a resolution of 720x720.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
---
 .../panel/anbernic,rgcubexx-panel.yaml        | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml

diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml
new file mode 100644
index 00000000000..47c5174fad2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/anbernic,rgcubexx-panel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Anbernic RG CubeXX (YLM-LBN0395004H-V1) 3.95" 720x720 24-bit IPS LCD panel
+
+maintainers:
+  - Hironori KIKUCHI <kikuchan98@gmail.com>
+
+allOf:
+  - $ref: panel-common.yaml#
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: anbernic,rgcubexx-panel
+
+  reg:
+    maxItems: 1
+
+  spi-3wire: true
+
+required:
+  - compatible
+  - reg
+  - port
+  - power-supply
+  - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        panel@0 {
+            compatible = "anbernic,rgcubexx-panel";
+            reg = <0>;
+
+            spi-3wire;
+            spi-max-frequency = <3125000>;
+
+            reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
+
+            backlight = <&backlight>;
+            power-supply = <&reg_lcd>;
+
+            port {
+                endpoint {
+                    remote-endpoint = <&tcon_lcd0_out_lcd>;
+                };
+            };
+        };
+    };
-- 
2.47.0

[PATCH 6/6] drm: panel: nv3052c: Add a panel for RG CubeXX

[Hironori KIKUCHI]

This is a display panel used in the Anbernic RG CubeXX, a handheld
gaming device from Anbernic. It is 3.95 inches in size (diagonally)
with a resolution of 720x720.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
---
 .../gpu/drm/panel/panel-newvision-nv3052c.c   | 198 ++++++++++++++++++
 1 file changed, 198 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
index 5a7cf6cb8be..bd5be0b5e93 100644
--- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
@@ -963,6 +963,176 @@ static const struct nv3052c_reg ylm_lbv0400001x_v1_panel_regs[] = {
 	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
 };
 
+static const struct nv3052c_reg ylm_lbn0395004h_v1_panel_regs[] = {
+	// EXTC Command set enable, select page 1
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
+	// Mostly unknown registers
+	{ 0xe3, 0x00 },
+	{ 0x0a, 0x01 }, // WRMADC_EN
+	{ 0x23, 0x00 }, // RGB interface control: DE+SYNC MODE PCLK-N
+	{ 0x25, 0x14 },
+	{ 0x29, 0x02 },
+	{ 0x2a, 0xcf },
+	{ 0x38, 0x9c }, // VCOM_ADJ1
+	{ 0x39, 0xa7 }, // VCOM_ADJ2
+	{ 0x3a, 0x5f }, // VCOM_ADJ3
+	{ 0x91, 0x77 }, // EXTPW_CTRL2
+	{ 0x92, 0x77 }, // EXTPW_CTRL3
+	{ 0x99, 0x52 }, // PUMP_CTRL2
+	{ 0x9b, 0x5b }, // PUMP_CTRL4
+	{ 0xa0, 0x55 },
+	{ 0xa1, 0x50 },
+	{ 0xa4, 0x9c },
+	{ 0xa7, 0x02 },
+	{ 0xa8, 0x01 },
+	{ 0xa9, 0x01 },
+	{ 0xaa, 0xfc },
+	{ 0xab, 0x28 },
+	{ 0xac, 0x06 },
+	{ 0xad, 0x06 },
+	{ 0xae, 0x06 },
+	{ 0xaf, 0x03 },
+	{ 0xb0, 0x08 },
+	{ 0xb1, 0x26 },
+	{ 0xb2, 0x28 },
+	{ 0xb3, 0x28 },
+	{ 0xb4, 0x03 },
+	{ 0xb5, 0x08 },
+	{ 0xb6, 0x26 },
+	{ 0xb7, 0x08 },
+	{ 0xb8, 0x26 },
+	// EXTC Command set enable, select page 2
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
+	// Set gray scale voltage to adjust gamma
+	{ 0xb0, 0x02 }, // PGAMVR0
+	{ 0xb1, 0x11 }, // PGAMVR1
+	{ 0xb2, 0x12 }, // PGAMVR2
+	{ 0xb3, 0x2e }, // PGAMVR3
+	{ 0xb4, 0x30 }, // PGAMVR4
+	{ 0xb5, 0x37 }, // PGAMVR5
+	{ 0xb6, 0x1c }, // PGAMPR0
+	{ 0xb7, 0x39 }, // PGAMPR1
+	{ 0xb8, 0x08 }, // PGAMPK0
+	{ 0xb9, 0x00 }, // PGAMPK1
+	{ 0xba, 0x12 }, // PGAMPK2
+	{ 0xbb, 0x12 }, // PGAMPK3
+	{ 0xbc, 0x14 }, // PGAMPK4
+	{ 0xbd, 0x15 }, // PGAMPK5
+	{ 0xbe, 0x16 }, // PGAMPK6
+	{ 0xbf, 0x0d }, // PGAMPK7
+	{ 0xc0, 0x15 }, // PGAMPK8
+	{ 0xc1, 0x04 }, // PGAMPK9
+	{ 0xd0, 0x05 }, // NGAMVR0
+	{ 0xd1, 0x07 }, // NGAMVR0
+	{ 0xd2, 0x08 }, // NGAMVR1
+	{ 0xd3, 0x30 }, // NGAMVR2
+	{ 0xd4, 0x2e }, // NGAMVR3
+	{ 0xd5, 0x32 }, // NGAMVR4
+	{ 0xd6, 0x1c }, // NGAMPR0
+	{ 0xd7, 0x3b }, // NGAMPR1
+	{ 0xd8, 0x10 }, // NGAMPK0
+	{ 0xd9, 0x06 }, // NGAMPK1
+	{ 0xda, 0x12 }, // NGAMPK2
+	{ 0xdb, 0x12 }, // NGAMPK3
+	{ 0xdc, 0x14 }, // NGAMPK4
+	{ 0xdd, 0x15 }, // NGAMPK5
+	{ 0xde, 0x18 }, // NGAMPK6
+	{ 0xdf, 0x0f }, // NGAMPK7
+	{ 0xe0, 0x17 }, // NGAMPK8
+	{ 0xe1, 0x0a }, // NGAMPK9
+	// EXTC Command set enable, select page 3
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
+	// Set various timing settings
+	{ 0x08, 0x09 }, // GIP_VST_9
+	{ 0x09, 0x0a }, // GIP_VST_10
+	{ 0x0a, 0x0b }, // GIP_VST_11
+	{ 0x0b, 0x0c }, // GIP_VST_12
+	{ 0x28, 0x22 }, // GIP_VEND_9
+	{ 0x2a, 0xec }, // GIP_VEND_11
+	{ 0x2b, 0xec }, // GIP_VEND_12
+	{ 0x30, 0x00 }, // GIP_CLK_1
+	{ 0x31, 0x00 }, // GIP_CLK_2
+	{ 0x32, 0x00 }, // GIP_CLK_3
+	{ 0x33, 0x00 }, // GIP_CLK_4
+	{ 0x34, 0x61 }, // GIP_CLK_5
+	{ 0x35, 0xd4 }, // GIP_CLK_6
+	{ 0x36, 0x24 }, // GIP_CLK_7
+	{ 0x37, 0x03 }, // GIP_CLK_8
+	{ 0x40, 0x0d }, // GIP_CLKA_1
+	{ 0x41, 0x0e }, // GIP_CLKA_2
+	{ 0x42, 0x0f }, // GIP_CLKA_3
+	{ 0x43, 0x10 }, // GIP_CLKA_4
+	{ 0x44, 0x22 }, // GIP_CLKA_5
+	{ 0x45, 0xe1 }, // GIP_CLKA_6
+	{ 0x46, 0xe2 }, // GIP_CLKA_7
+	{ 0x47, 0x22 }, // GIP_CLKA_8
+	{ 0x48, 0xe3 }, // GIP_CLKA_9
+	{ 0x49, 0xe4 }, // GIP_CLKA_10
+	{ 0x50, 0x11 }, // GIP_CLKB_1
+	{ 0x51, 0x12 }, // GIP_CLKB_2
+	{ 0x52, 0x13 }, // GIP_CLKB_3
+	{ 0x53, 0x14 }, // GIP_CLKB_4
+	{ 0x54, 0x22 }, // GIP_CLKB_5
+	{ 0x55, 0xe5 }, // GIP_CLKB_6
+	{ 0x56, 0xe6 }, // GIP_CLKB_7
+	{ 0x57, 0x22 }, // GIP_CLKB_8
+	{ 0x58, 0xe7 }, // GIP_CLKB_9
+	{ 0x59, 0xe8 }, // GIP_CLKB_10
+	// Map internal GOA signals to GOA output pad
+	{ 0x80, 0x05 }, // PANELU2D1
+	{ 0x81, 0x1e }, // PANELU2D2
+	{ 0x82, 0x02 }, // PANELU2D3
+	{ 0x83, 0x04 }, // PANELU2D4
+	{ 0x84, 0x1e }, // PANELU2D5
+	{ 0x85, 0x1e }, // PANELU2D6
+	{ 0x86, 0x1f }, // PANELU2D7
+	{ 0x87, 0x1f }, // PANELU2D8
+	{ 0x88, 0x0e }, // PANELU2D9
+	{ 0x89, 0x10 }, // PANELU2D10
+	{ 0x8a, 0x0a }, // PANELU2D11
+	{ 0x8b, 0x0c }, // PANELU2D12
+	{ 0x96, 0x05 }, // PANELU2D23
+	{ 0x97, 0x1e }, // PANELU2D24
+	{ 0x98, 0x01 }, // PANELU2D25
+	{ 0x99, 0x03 }, // PANELU2D26
+	{ 0x9a, 0x1e }, // PANELU2D27
+	{ 0x9b, 0x1e }, // PANELU2D28
+	{ 0x9c, 0x1f }, // PANELU2D29
+	{ 0x9d, 0x1f }, // PANELU2D30
+	{ 0x9e, 0x0d }, // PANELU2D31
+	{ 0x9f, 0x0f }, // PANELU2D32
+	{ 0xa0, 0x09 }, // PANELU2D33
+	{ 0xa1, 0x0b }, // PANELU2D34
+	{ 0xb0, 0x05 }, // PANELD2U1
+	{ 0xb1, 0x1f }, // PANELD2U2
+	{ 0xb2, 0x03 }, // PANELD2U3
+	{ 0xb3, 0x01 }, // PANELD2U4
+	{ 0xb4, 0x1e }, // PANELD2U5
+	{ 0xb5, 0x1e }, // PANELD2U6
+	{ 0xb6, 0x1f }, // PANELD2U7
+	{ 0xb7, 0x1e }, // PANELD2U8
+	{ 0xb8, 0x0b }, // PANELD2U9
+	{ 0xb9, 0x09 }, // PANELD2U10
+	{ 0xba, 0x0f }, // PANELD2U11
+	{ 0xbb, 0x0d }, // PANELD2U12
+	{ 0xc6, 0x05 }, // PANELD2U23
+	{ 0xc7, 0x1f }, // PANELD2U24
+	{ 0xc8, 0x04 }, // PANELD2U25
+	{ 0xc9, 0x02 }, // PANELD2U26
+	{ 0xca, 0x1e }, // PANELD2U27
+	{ 0xcb, 0x1e }, // PANELD2U28
+	{ 0xcc, 0x1f }, // PANELD2U29
+	{ 0xcd, 0x1e }, // PANELD2U30
+	{ 0xce, 0x0c }, // PANELD2U31
+	{ 0xcf, 0x0a }, // PANELD2U32
+	{ 0xd0, 0x10 }, // PANELD2U33
+	{ 0xd1, 0x0e }, // PANELD2U34
+	// EXTC Command set enable, select page 0
+	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
+	// Display Access Control
+	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
+};
+
 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
 {
 	return container_of(panel, struct nv3052c, panel);
@@ -1245,6 +1415,21 @@ static const struct drm_display_mode ylm_lbv0400001x_v1_mode[] = {
 	},
 };
 
+static const struct drm_display_mode ylm_lbn0395004h_v1_mode[] = {
+	{
+		.clock = 36000,
+		.hdisplay = 720,
+		.hsync_start = 720 + 28,
+		.hsync_end = 720 + 28 + 4,
+		.htotal = 720 + 28 + 4 + 42,
+		.vdisplay = 720,
+		.vsync_start = 720 + 16,
+		.vsync_end = 720 + 16 + 4,
+		.vtotal = 720 + 16 + 4 + 16,
+		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+	},
+};
+
 static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
 	.display_modes = ltk035c5444t_modes,
 	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
@@ -1300,12 +1485,24 @@ static const struct nv3052c_panel_info ylm_lbv0400001x_v1_panel_info = {
 	.panel_regs_len = ARRAY_SIZE(ylm_lbv0400001x_v1_panel_regs),
 };
 
+static const struct nv3052c_panel_info ylm_lbn0395004h_v1_panel_info = {
+	.display_modes = ylm_lbn0395004h_v1_mode,
+	.num_modes = ARRAY_SIZE(ylm_lbn0395004h_v1_mode),
+	.width_mm = 71,
+	.height_mm = 71,
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+	.panel_regs = ylm_lbn0395004h_v1_panel_regs,
+	.panel_regs_len = ARRAY_SIZE(ylm_lbn0395004h_v1_panel_regs),
+};
+
 static const struct spi_device_id nv3052c_ids[] = {
 	{ "ltk035c5444t", },
 	{ "fs035vg158", },
 	{ "rg35xx-plus-panel", },
 	{ "rg35xx-plus-rev6-panel", },
 	{ "rg40xx-panel", },
+	{ "rgcubexx-panel", },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(spi, nv3052c_ids);
@@ -1316,6 +1513,7 @@ static const struct of_device_id nv3052c_of_match[] = {
 	{ .compatible = "anbernic,rg35xx-plus-panel", .data = &wl_355608_a8_panel_info },
 	{ .compatible = "anbernic,rg35xx-plus-rev6-panel", .data = &ylm_lbv0345001h_v2_panel_info },
 	{ .compatible = "anbernic,rg40xx-panel", .data = &ylm_lbv0400001x_v1_panel_info },
+	{ .compatible = "anbernic,rgcubexx-panel", .data = &ylm_lbn0395004h_v1_panel_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, nv3052c_of_match);
-- 
2.47.0

Re: [PATCH 6/6] drm: panel: nv3052c: Add a panel for RG CubeXX

[Philippe Simons]

Tested on RG CubeXX

Tested-by: Philippe Simons <simons.philippe@gmail.com>

On 24/11/2024 09:02, Hironori KIKUCHI wrote:
> This is a display panel used in the Anbernic RG CubeXX, a handheld
> gaming device from Anbernic. It is 3.95 inches in size (diagonally)
> with a resolution of 720x720.
>
> Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
> ---
>   .../gpu/drm/panel/panel-newvision-nv3052c.c   | 198 ++++++++++++++++++
>   1 file changed, 198 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> index 5a7cf6cb8be..bd5be0b5e93 100644
> --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> @@ -963,6 +963,176 @@ static const struct nv3052c_reg ylm_lbv0400001x_v1_panel_regs[] = {
>   	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
>   };
>   
> +static const struct nv3052c_reg ylm_lbn0395004h_v1_panel_regs[] = {
> +	// EXTC Command set enable, select page 1
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
> +	// Mostly unknown registers
> +	{ 0xe3, 0x00 },
> +	{ 0x0a, 0x01 }, // WRMADC_EN
> +	{ 0x23, 0x00 }, // RGB interface control: DE+SYNC MODE PCLK-N
> +	{ 0x25, 0x14 },
> +	{ 0x29, 0x02 },
> +	{ 0x2a, 0xcf },
> +	{ 0x38, 0x9c }, // VCOM_ADJ1
> +	{ 0x39, 0xa7 }, // VCOM_ADJ2
> +	{ 0x3a, 0x5f }, // VCOM_ADJ3
> +	{ 0x91, 0x77 }, // EXTPW_CTRL2
> +	{ 0x92, 0x77 }, // EXTPW_CTRL3
> +	{ 0x99, 0x52 }, // PUMP_CTRL2
> +	{ 0x9b, 0x5b }, // PUMP_CTRL4
> +	{ 0xa0, 0x55 },
> +	{ 0xa1, 0x50 },
> +	{ 0xa4, 0x9c },
> +	{ 0xa7, 0x02 },
> +	{ 0xa8, 0x01 },
> +	{ 0xa9, 0x01 },
> +	{ 0xaa, 0xfc },
> +	{ 0xab, 0x28 },
> +	{ 0xac, 0x06 },
> +	{ 0xad, 0x06 },
> +	{ 0xae, 0x06 },
> +	{ 0xaf, 0x03 },
> +	{ 0xb0, 0x08 },
> +	{ 0xb1, 0x26 },
> +	{ 0xb2, 0x28 },
> +	{ 0xb3, 0x28 },
> +	{ 0xb4, 0x03 },
> +	{ 0xb5, 0x08 },
> +	{ 0xb6, 0x26 },
> +	{ 0xb7, 0x08 },
> +	{ 0xb8, 0x26 },
> +	// EXTC Command set enable, select page 2
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
> +	// Set gray scale voltage to adjust gamma
> +	{ 0xb0, 0x02 }, // PGAMVR0
> +	{ 0xb1, 0x11 }, // PGAMVR1
> +	{ 0xb2, 0x12 }, // PGAMVR2
> +	{ 0xb3, 0x2e }, // PGAMVR3
> +	{ 0xb4, 0x30 }, // PGAMVR4
> +	{ 0xb5, 0x37 }, // PGAMVR5
> +	{ 0xb6, 0x1c }, // PGAMPR0
> +	{ 0xb7, 0x39 }, // PGAMPR1
> +	{ 0xb8, 0x08 }, // PGAMPK0
> +	{ 0xb9, 0x00 }, // PGAMPK1
> +	{ 0xba, 0x12 }, // PGAMPK2
> +	{ 0xbb, 0x12 }, // PGAMPK3
> +	{ 0xbc, 0x14 }, // PGAMPK4
> +	{ 0xbd, 0x15 }, // PGAMPK5
> +	{ 0xbe, 0x16 }, // PGAMPK6
> +	{ 0xbf, 0x0d }, // PGAMPK7
> +	{ 0xc0, 0x15 }, // PGAMPK8
> +	{ 0xc1, 0x04 }, // PGAMPK9
> +	{ 0xd0, 0x05 }, // NGAMVR0
> +	{ 0xd1, 0x07 }, // NGAMVR0
> +	{ 0xd2, 0x08 }, // NGAMVR1
> +	{ 0xd3, 0x30 }, // NGAMVR2
> +	{ 0xd4, 0x2e }, // NGAMVR3
> +	{ 0xd5, 0x32 }, // NGAMVR4
> +	{ 0xd6, 0x1c }, // NGAMPR0
> +	{ 0xd7, 0x3b }, // NGAMPR1
> +	{ 0xd8, 0x10 }, // NGAMPK0
> +	{ 0xd9, 0x06 }, // NGAMPK1
> +	{ 0xda, 0x12 }, // NGAMPK2
> +	{ 0xdb, 0x12 }, // NGAMPK3
> +	{ 0xdc, 0x14 }, // NGAMPK4
> +	{ 0xdd, 0x15 }, // NGAMPK5
> +	{ 0xde, 0x18 }, // NGAMPK6
> +	{ 0xdf, 0x0f }, // NGAMPK7
> +	{ 0xe0, 0x17 }, // NGAMPK8
> +	{ 0xe1, 0x0a }, // NGAMPK9
> +	// EXTC Command set enable, select page 3
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
> +	// Set various timing settings
> +	{ 0x08, 0x09 }, // GIP_VST_9
> +	{ 0x09, 0x0a }, // GIP_VST_10
> +	{ 0x0a, 0x0b }, // GIP_VST_11
> +	{ 0x0b, 0x0c }, // GIP_VST_12
> +	{ 0x28, 0x22 }, // GIP_VEND_9
> +	{ 0x2a, 0xec }, // GIP_VEND_11
> +	{ 0x2b, 0xec }, // GIP_VEND_12
> +	{ 0x30, 0x00 }, // GIP_CLK_1
> +	{ 0x31, 0x00 }, // GIP_CLK_2
> +	{ 0x32, 0x00 }, // GIP_CLK_3
> +	{ 0x33, 0x00 }, // GIP_CLK_4
> +	{ 0x34, 0x61 }, // GIP_CLK_5
> +	{ 0x35, 0xd4 }, // GIP_CLK_6
> +	{ 0x36, 0x24 }, // GIP_CLK_7
> +	{ 0x37, 0x03 }, // GIP_CLK_8
> +	{ 0x40, 0x0d }, // GIP_CLKA_1
> +	{ 0x41, 0x0e }, // GIP_CLKA_2
> +	{ 0x42, 0x0f }, // GIP_CLKA_3
> +	{ 0x43, 0x10 }, // GIP_CLKA_4
> +	{ 0x44, 0x22 }, // GIP_CLKA_5
> +	{ 0x45, 0xe1 }, // GIP_CLKA_6
> +	{ 0x46, 0xe2 }, // GIP_CLKA_7
> +	{ 0x47, 0x22 }, // GIP_CLKA_8
> +	{ 0x48, 0xe3 }, // GIP_CLKA_9
> +	{ 0x49, 0xe4 }, // GIP_CLKA_10
> +	{ 0x50, 0x11 }, // GIP_CLKB_1
> +	{ 0x51, 0x12 }, // GIP_CLKB_2
> +	{ 0x52, 0x13 }, // GIP_CLKB_3
> +	{ 0x53, 0x14 }, // GIP_CLKB_4
> +	{ 0x54, 0x22 }, // GIP_CLKB_5
> +	{ 0x55, 0xe5 }, // GIP_CLKB_6
> +	{ 0x56, 0xe6 }, // GIP_CLKB_7
> +	{ 0x57, 0x22 }, // GIP_CLKB_8
> +	{ 0x58, 0xe7 }, // GIP_CLKB_9
> +	{ 0x59, 0xe8 }, // GIP_CLKB_10
> +	// Map internal GOA signals to GOA output pad
> +	{ 0x80, 0x05 }, // PANELU2D1
> +	{ 0x81, 0x1e }, // PANELU2D2
> +	{ 0x82, 0x02 }, // PANELU2D3
> +	{ 0x83, 0x04 }, // PANELU2D4
> +	{ 0x84, 0x1e }, // PANELU2D5
> +	{ 0x85, 0x1e }, // PANELU2D6
> +	{ 0x86, 0x1f }, // PANELU2D7
> +	{ 0x87, 0x1f }, // PANELU2D8
> +	{ 0x88, 0x0e }, // PANELU2D9
> +	{ 0x89, 0x10 }, // PANELU2D10
> +	{ 0x8a, 0x0a }, // PANELU2D11
> +	{ 0x8b, 0x0c }, // PANELU2D12
> +	{ 0x96, 0x05 }, // PANELU2D23
> +	{ 0x97, 0x1e }, // PANELU2D24
> +	{ 0x98, 0x01 }, // PANELU2D25
> +	{ 0x99, 0x03 }, // PANELU2D26
> +	{ 0x9a, 0x1e }, // PANELU2D27
> +	{ 0x9b, 0x1e }, // PANELU2D28
> +	{ 0x9c, 0x1f }, // PANELU2D29
> +	{ 0x9d, 0x1f }, // PANELU2D30
> +	{ 0x9e, 0x0d }, // PANELU2D31
> +	{ 0x9f, 0x0f }, // PANELU2D32
> +	{ 0xa0, 0x09 }, // PANELU2D33
> +	{ 0xa1, 0x0b }, // PANELU2D34
> +	{ 0xb0, 0x05 }, // PANELD2U1
> +	{ 0xb1, 0x1f }, // PANELD2U2
> +	{ 0xb2, 0x03 }, // PANELD2U3
> +	{ 0xb3, 0x01 }, // PANELD2U4
> +	{ 0xb4, 0x1e }, // PANELD2U5
> +	{ 0xb5, 0x1e }, // PANELD2U6
> +	{ 0xb6, 0x1f }, // PANELD2U7
> +	{ 0xb7, 0x1e }, // PANELD2U8
> +	{ 0xb8, 0x0b }, // PANELD2U9
> +	{ 0xb9, 0x09 }, // PANELD2U10
> +	{ 0xba, 0x0f }, // PANELD2U11
> +	{ 0xbb, 0x0d }, // PANELD2U12
> +	{ 0xc6, 0x05 }, // PANELD2U23
> +	{ 0xc7, 0x1f }, // PANELD2U24
> +	{ 0xc8, 0x04 }, // PANELD2U25
> +	{ 0xc9, 0x02 }, // PANELD2U26
> +	{ 0xca, 0x1e }, // PANELD2U27
> +	{ 0xcb, 0x1e }, // PANELD2U28
> +	{ 0xcc, 0x1f }, // PANELD2U29
> +	{ 0xcd, 0x1e }, // PANELD2U30
> +	{ 0xce, 0x0c }, // PANELD2U31
> +	{ 0xcf, 0x0a }, // PANELD2U32
> +	{ 0xd0, 0x10 }, // PANELD2U33
> +	{ 0xd1, 0x0e }, // PANELD2U34
> +	// EXTC Command set enable, select page 0
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
> +	// Display Access Control
> +	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
> +};
> +
>   static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
>   {
>   	return container_of(panel, struct nv3052c, panel);
> @@ -1245,6 +1415,21 @@ static const struct drm_display_mode ylm_lbv0400001x_v1_mode[] = {
>   	},
>   };
>   
> +static const struct drm_display_mode ylm_lbn0395004h_v1_mode[] = {
> +	{
> +		.clock = 36000,
> +		.hdisplay = 720,
> +		.hsync_start = 720 + 28,
> +		.hsync_end = 720 + 28 + 4,
> +		.htotal = 720 + 28 + 4 + 42,
> +		.vdisplay = 720,
> +		.vsync_start = 720 + 16,
> +		.vsync_end = 720 + 16 + 4,
> +		.vtotal = 720 + 16 + 4 + 16,
> +		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
> +	},
> +};
> +
>   static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
>   	.display_modes = ltk035c5444t_modes,
>   	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
> @@ -1300,12 +1485,24 @@ static const struct nv3052c_panel_info ylm_lbv0400001x_v1_panel_info = {
>   	.panel_regs_len = ARRAY_SIZE(ylm_lbv0400001x_v1_panel_regs),
>   };
>   
> +static const struct nv3052c_panel_info ylm_lbn0395004h_v1_panel_info = {
> +	.display_modes = ylm_lbn0395004h_v1_mode,
> +	.num_modes = ARRAY_SIZE(ylm_lbn0395004h_v1_mode),
> +	.width_mm = 71,
> +	.height_mm = 71,
> +	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> +	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> +	.panel_regs = ylm_lbn0395004h_v1_panel_regs,
> +	.panel_regs_len = ARRAY_SIZE(ylm_lbn0395004h_v1_panel_regs),
> +};
> +
>   static const struct spi_device_id nv3052c_ids[] = {
>   	{ "ltk035c5444t", },
>   	{ "fs035vg158", },
>   	{ "rg35xx-plus-panel", },
>   	{ "rg35xx-plus-rev6-panel", },
>   	{ "rg40xx-panel", },
> +	{ "rgcubexx-panel", },
>   	{ /* sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(spi, nv3052c_ids);
> @@ -1316,6 +1513,7 @@ static const struct of_device_id nv3052c_of_match[] = {
>   	{ .compatible = "anbernic,rg35xx-plus-panel", .data = &wl_355608_a8_panel_info },
>   	{ .compatible = "anbernic,rg35xx-plus-rev6-panel", .data = &ylm_lbv0345001h_v2_panel_info },
>   	{ .compatible = "anbernic,rg40xx-panel", .data = &ylm_lbv0400001x_v1_panel_info },
> +	{ .compatible = "anbernic,rgcubexx-panel", .data = &ylm_lbn0395004h_v1_panel_info },
>   	{ /* sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(of, nv3052c_of_match);

Re: [PATCH 4/6] drm: panel: nv3052c: Add a panel for RG40XX series

[Philippe Simons]

Tested on RG40XX-V

Tested-by: Philippe Simons <simons.philippe@gmail.com>

On 24/11/2024 09:02, Hironori KIKUCHI wrote:
> This is a display panel used in the Anbernic RG40XX series (H and V),
> a handheld gaming device from Anbernic. It is 4.00 inches in size
> (diagonally) with a resolution of 640x480.
>
> Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
> ---
>   .../gpu/drm/panel/panel-newvision-nv3052c.c   | 212 ++++++++++++++++++
>   1 file changed, 212 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> index 166393ccfed..5a7cf6cb8be 100644
> --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> @@ -779,6 +779,190 @@ static const struct nv3052c_reg ylm_lbv0345001h_v2_panel_regs[] = {
>   	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
>   };
>   
> +static const struct nv3052c_reg ylm_lbv0400001x_v1_panel_regs[] = {
> +	// EXTC Command set enable, select page 1
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
> +	// Mostly unknown registers
> +	{ 0xe3, 0x00 },
> +	{ 0x0a, 0x01 }, // WRMADC_EN
> +	{ 0x23, 0x00 }, // RGB interface control: DE+SYNC MODE PCLK-N
> +	{ 0x25, 0x14 },
> +	{ 0x28, 0x47 },
> +	{ 0x29, 0x01 },
> +	{ 0x2a, 0xdf },
> +	{ 0x38, 0x9c }, // VCOM_ADJ1
> +	{ 0x39, 0xa7 }, // VCOM_ADJ2
> +	{ 0x3a, 0x47 }, // VCOM_ADJ3
> +	{ 0x91, 0x77 }, // EXTPW_CTRL2
> +	{ 0x92, 0x77 }, // EXTPW_CTRL3
> +	{ 0x99, 0x52 }, // PUMP_CTRL2
> +	{ 0x9b, 0x5b }, // PUMP_CTRL4
> +	{ 0xa0, 0x55 },
> +	{ 0xa1, 0x50 },
> +	{ 0xa4, 0x9c },
> +	{ 0xa7, 0x02 },
> +	{ 0xa8, 0x01 },
> +	{ 0xa9, 0x01 },
> +	{ 0xaa, 0xfc },
> +	{ 0xab, 0x28 },
> +	{ 0xac, 0x06 },
> +	{ 0xad, 0x06 },
> +	{ 0xae, 0x06 },
> +	{ 0xaf, 0x03 },
> +	{ 0xb0, 0x08 },
> +	{ 0xb1, 0x26 },
> +	{ 0xb2, 0x28 },
> +	{ 0xb3, 0x28 },
> +	{ 0xb4, 0x03 },
> +	{ 0xb5, 0x08 },
> +	{ 0xb6, 0x26 },
> +	{ 0xb7, 0x08 },
> +	{ 0xb8, 0x26 },
> +	// EXTC Command set enable, select page 2
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 },
> +	// Set gray scale voltage to adjust gamma
> +	{ 0xb0, 0x05 }, // PGAMVR0
> +	{ 0xb1, 0x12 }, // PGAMVR1
> +	{ 0xb2, 0x13 }, // PGAMVR2
> +	{ 0xb3, 0x2c }, // PGAMVR3
> +	{ 0xb4, 0x2a }, // PGAMVR4
> +	{ 0xb5, 0x37 }, // PGAMVR5
> +	{ 0xb6, 0x27 }, // PGAMPR0
> +	{ 0xb7, 0x42 }, // PGAMPR1
> +	{ 0xb8, 0x0f }, // PGAMPK0
> +	{ 0xb9, 0x06 }, // PGAMPK1
> +	{ 0xba, 0x12 }, // PGAMPK2
> +	{ 0xbb, 0x12 }, // PGAMPK3
> +	{ 0xbc, 0x13 }, // PGAMPK4
> +	{ 0xbd, 0x15 }, // PGAMPK5
> +	{ 0xbe, 0x1b }, // PGAMPK6
> +	{ 0xbf, 0x14 }, // PGAMPK7
> +	{ 0xc0, 0x1d }, // PGAMPK8
> +	{ 0xc1, 0x09 }, // PGAMPK9
> +	{ 0xd0, 0x02 }, // NGAMVR0
> +	{ 0xd1, 0x1c }, // NGAMVR0
> +	{ 0xd2, 0x1d }, // NGAMVR1
> +	{ 0xd3, 0x36 }, // NGAMVR2
> +	{ 0xd4, 0x34 }, // NGAMVR3
> +	{ 0xd5, 0x32 }, // NGAMVR4
> +	{ 0xd6, 0x25 }, // NGAMPR0
> +	{ 0xd7, 0x40 }, // NGAMPR1
> +	{ 0xd8, 0x0d }, // NGAMPK0
> +	{ 0xd9, 0x04 }, // NGAMPK1
> +	{ 0xda, 0x12 }, // NGAMPK2
> +	{ 0xdb, 0x12 }, // NGAMPK3
> +	{ 0xdc, 0x13 }, // NGAMPK4
> +	{ 0xdd, 0x15 }, // NGAMPK5
> +	{ 0xde, 0x15 }, // NGAMPK6
> +	{ 0xdf, 0x0c }, // NGAMPK7
> +	{ 0xe0, 0x13 }, // NGAMPK8
> +	{ 0xe1, 0x07 }, // NGAMPK9
> +	// EXTC Command set enable, select page 3
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 },
> +	// Set various timing settings
> +	{ 0x08, 0x0a }, // GIP_VST_9
> +	{ 0x09, 0x0b }, // GIP_VST_10
> +	{ 0x30, 0x00 }, // GIP_CLK_1
> +	{ 0x31, 0x00 }, // GIP_CLK_2
> +	{ 0x32, 0x00 }, // GIP_CLK_3
> +	{ 0x33, 0x00 }, // GIP_CLK_4
> +	{ 0x34, 0x61 }, // GIP_CLK_5
> +	{ 0x35, 0xd4 }, // GIP_CLK_6
> +	{ 0x36, 0x24 }, // GIP_CLK_7
> +	{ 0x37, 0x03 }, // GIP_CLK_8
> +	{ 0x40, 0x0d }, // GIP_CLKA_1
> +	{ 0x41, 0x0e }, // GIP_CLKA_2
> +	{ 0x42, 0x0f }, // GIP_CLKA_3
> +	{ 0x43, 0x10 }, // GIP_CLKA_4
> +	{ 0x44, 0x11 }, // GIP_CLKA_5
> +	{ 0x45, 0xf4 }, // GIP_CLKA_6
> +	{ 0x46, 0xf5 }, // GIP_CLKA_7
> +	{ 0x47, 0x11 }, // GIP_CLKA_8
> +	{ 0x48, 0xf6 }, // GIP_CLKA_9
> +	{ 0x49, 0xf7 }, // GIP_CLKA_10
> +	{ 0x50, 0x11 }, // GIP_CLKB_1
> +	{ 0x51, 0x12 }, // GIP_CLKB_2
> +	{ 0x52, 0x13 }, // GIP_CLKB_3
> +	{ 0x53, 0x14 }, // GIP_CLKB_4
> +	{ 0x54, 0x11 }, // GIP_CLKB_5
> +	{ 0x55, 0xf8 }, // GIP_CLKB_6
> +	{ 0x56, 0xf9 }, // GIP_CLKB_7
> +	{ 0x57, 0x11 }, // GIP_CLKB_8
> +	{ 0x58, 0xfa }, // GIP_CLKB_9
> +	{ 0x59, 0xfb }, // GIP_CLKB_10
> +	{ 0x60, 0x05 }, // GIP_CLKC_1
> +	{ 0x61, 0x05 }, // GIP_CLKC_2
> +	{ 0x65, 0x0a }, // GIP_CLKC_6
> +	{ 0x66, 0x0a }, // GIP_CLKC_7
> +	// Map internal GOA signals to GOA output pad
> +	{ 0x82, 0x1e }, // PANELU2D3
> +	{ 0x83, 0x1f }, // PANELU2D4
> +	{ 0x84, 0x11 }, // PANELU2D5
> +	{ 0x85, 0x02 }, // PANELU2D6
> +	{ 0x86, 0x1e }, // PANELU2D7
> +	{ 0x87, 0x1e }, // PANELU2D8
> +	{ 0x88, 0x1f }, // PANELU2D9
> +	{ 0x89, 0x0e }, // PANELU2D10
> +	{ 0x8a, 0x0e }, // PANELU2D11
> +	{ 0x8b, 0x10 }, // PANELU2D12
> +	{ 0x8c, 0x10 }, // PANELU2D13
> +	{ 0x8d, 0x0a }, // PANELU2D14
> +	{ 0x8e, 0x0a }, // PANELU2D15
> +	{ 0x8f, 0x0c }, // PANELU2D16
> +	{ 0x90, 0x0c }, // PANELU2D17
> +	{ 0x98, 0x1e }, // PANELU2D25
> +	{ 0x99, 0x1f }, // PANELU2D26
> +	{ 0x9a, 0x11 }, // PANELU2D27
> +	{ 0x9b, 0x01 }, // PANELU2D28
> +	{ 0x9c, 0x1e }, // PANELU2D29
> +	{ 0x9d, 0x1e }, // PANELU2D30
> +	{ 0x9e, 0x1f }, // PANELU2D31
> +	{ 0x9f, 0x0d }, // PANELU2D32
> +	{ 0xa0, 0x0d }, // PANELU2D33
> +	{ 0xa1, 0x0f }, // PANELU2D34
> +	{ 0xa2, 0x0f }, // PANELU2D35
> +	{ 0xa3, 0x09 }, // PANELU2D36
> +	{ 0xa4, 0x09 }, // PANELU2D37
> +	{ 0xa5, 0x0b }, // PANELU2D38
> +	{ 0xa6, 0x0b }, // PANELU2D39
> +	{ 0xb2, 0x1f }, // PANELD2U3
> +	{ 0xb3, 0x1e }, // PANELD2U4
> +	{ 0xb4, 0x11 }, // PANELD2U5
> +	{ 0xb5, 0x01 }, // PANELD2U6
> +	{ 0xb6, 0x1e }, // PANELD2U7
> +	{ 0xb7, 0x1e }, // PANELD2U8
> +	{ 0xb8, 0x1f }, // PANELD2U9
> +	{ 0xb9, 0x0b }, // PANELD2U10
> +	{ 0xba, 0x0b }, // PANELD2U11
> +	{ 0xbb, 0x09 }, // PANELD2U12
> +	{ 0xbc, 0x09 }, // PANELD2U13
> +	{ 0xbd, 0x0f }, // PANELD2U14
> +	{ 0xbe, 0x0f }, // PANELD2U15
> +	{ 0xbf, 0x0d }, // PANELD2U16
> +	{ 0xc0, 0x0d }, // PANELD2U17
> +	{ 0xc8, 0x1f }, // PANELD2U25
> +	{ 0xc9, 0x1e }, // PANELD2U26
> +	{ 0xca, 0x11 }, // PANELD2U27
> +	{ 0xcb, 0x02 }, // PANELD2U28
> +	{ 0xcc, 0x1e }, // PANELD2U29
> +	{ 0xcd, 0x1e }, // PANELD2U30
> +	{ 0xce, 0x1f }, // PANELD2U31
> +	{ 0xcf, 0x0c }, // PANELD2U32
> +	{ 0xd0, 0x0c }, // PANELD2U33
> +	{ 0xd1, 0x0a }, // PANELD2U34
> +	{ 0xd2, 0x0a }, // PANELD2U35
> +	{ 0xd3, 0x10 }, // PANELD2U36
> +	{ 0xd4, 0x10 }, // PANELD2U37
> +	{ 0xd5, 0x0e }, // PANELD2U38
> +	{ 0xd6, 0x0e }, // PANELD2U39
> +	// EXTC Command set enable, select page 0
> +	{ 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 },
> +	// Interface Pixel Format
> +	{ 0x3a, 0x77 },
> +	// Display Access Control
> +	{ 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0
> +};
> +
>   static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
>   {
>   	return container_of(panel, struct nv3052c, panel);
> @@ -1046,6 +1230,21 @@ static const struct drm_display_mode ylm_lbv0345001h_v2_mode[] = {
>   	},
>   };
>   
> +static const struct drm_display_mode ylm_lbv0400001x_v1_mode[] = {
> +	{
> +		.clock = 24000,
> +		.hdisplay = 640,
> +		.hsync_start = 640 + 84,
> +		.hsync_end = 640 + 84 + 20,
> +		.htotal = 640 + 84 + 20 + 26,
> +		.vdisplay = 480,
> +		.vsync_start = 480 + 20,
> +		.vsync_end = 480 + 20 + 4,
> +		.vtotal = 480 + 20 + 4 + 16,
> +		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
> +	},
> +};
> +
>   static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
>   	.display_modes = ltk035c5444t_modes,
>   	.num_modes = ARRAY_SIZE(ltk035c5444t_modes),
> @@ -1090,11 +1289,23 @@ static const struct nv3052c_panel_info ylm_lbv0345001h_v2_panel_info = {
>   	.panel_regs_len = ARRAY_SIZE(ylm_lbv0345001h_v2_panel_regs),
>   };
>   
> +static const struct nv3052c_panel_info ylm_lbv0400001x_v1_panel_info = {
> +	.display_modes = ylm_lbv0400001x_v1_mode,
> +	.num_modes = ARRAY_SIZE(ylm_lbv0400001x_v1_mode),
> +	.width_mm = 81,
> +	.height_mm = 61,
> +	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> +	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> +	.panel_regs = ylm_lbv0400001x_v1_panel_regs,
> +	.panel_regs_len = ARRAY_SIZE(ylm_lbv0400001x_v1_panel_regs),
> +};
> +
>   static const struct spi_device_id nv3052c_ids[] = {
>   	{ "ltk035c5444t", },
>   	{ "fs035vg158", },
>   	{ "rg35xx-plus-panel", },
>   	{ "rg35xx-plus-rev6-panel", },
> +	{ "rg40xx-panel", },
>   	{ /* sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(spi, nv3052c_ids);
> @@ -1104,6 +1315,7 @@ static const struct of_device_id nv3052c_of_match[] = {
>   	{ .compatible = "fascontek,fs035vg158", .data = &fs035vg158_panel_info },
>   	{ .compatible = "anbernic,rg35xx-plus-panel", .data = &wl_355608_a8_panel_info },
>   	{ .compatible = "anbernic,rg35xx-plus-rev6-panel", .data = &ylm_lbv0345001h_v2_panel_info },
> +	{ .compatible = "anbernic,rg40xx-panel", .data = &ylm_lbv0400001x_v1_panel_info },
>   	{ /* sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(of, nv3052c_of_match);

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Krzysztof Kozlowski]

On 24/11/2024 09:02, Hironori KIKUCHI wrote:
> +++ b/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Anbernic RG35XX series (YLM-LBV0345001H-V2) 3.45" 640x480 24-bit IPS LCD panel
> +
> +maintainers:
> +  - Hironori KIKUCHI <kikuchan98@gmail.com>
> +
> +allOf:
> +  - $ref: panel-common.yaml#
> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    const: anbernic,rg35xx-plus-rev6-panel

Everything is the same here. Add new compatible to existing schema
respecting compatibility (fallback) or not (no fallback).


Best regards,
Krzysztof

Re: [PATCH 3/6] dt-bindings: display: panel: Add a panel for RG40XX series

[Krzysztof Kozlowski]

On 24/11/2024 09:02, Hironori KIKUCHI wrote:
> This is a display panel used in the Anbernic RG40XX series (H and V),
> a handheld gaming device from Anbernic. It is 4.00 inches in size
> (diagonally) with a resolution of 640x480.
> 
> Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
> ---
>  .../display/panel/anbernic,rg40xx-panel.yaml  | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml
> new file mode 100644
> index 00000000000..bec5363e1d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/anbernic,rg40xx-panel.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/panel/anbernic,rg40xx-panel.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Anbernic RG40XX series (YLM-LBV0400001X-V1) 4.00" 640x480 24-bit IPS LCD panel
> +
> +maintainers:
> +  - Hironori KIKUCHI <kikuchan98@gmail.com>
> +
> +allOf:
> +  - $ref: panel-common.yaml#
> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    const: anbernic,rg40xx-panel

Nope, same comments. Also for both patches, wildcards are not allowed.
Use specific number.


Best regards,
Krzysztof

Re: [PATCH 5/6] dt-bindings: display: panel: Add a panel for RG CubeXX

[Krzysztof Kozlowski]

On 24/11/2024 09:02, Hironori KIKUCHI wrote:
> This is a display panel used in the Anbernic RG CubeXX, a handheld
> gaming device from Anbernic. It is 3.95 inches in size (diagonally)
> with a resolution of 720x720.
> 
> Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
> ---
>  .../panel/anbernic,rgcubexx-panel.yaml        | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml
> new file mode 100644
> index 00000000000..47c5174fad2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/anbernic,rgcubexx-panel.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/panel/anbernic,rgcubexx-panel.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Anbernic RG CubeXX (YLM-LBN0395004H-V1) 3.95" 720x720 24-bit IPS LCD panel
> +
> +maintainers:
> +  - Hironori KIKUCHI <kikuchan98@gmail.com>
> +
> +allOf:
> +  - $ref: panel-common.yaml#
> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    const: anbernic,rgcubexx-panel

Same comments, no wildcards, don't duplicate schemas. See how other
files are doing it.

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Krzysztof Kozlowski]

On 24/11/2024 17:01, Krzysztof Kozlowski wrote:
> On 24/11/2024 09:02, Hironori KIKUCHI wrote:
>> +++ b/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
>> @@ -0,0 +1,60 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Anbernic RG35XX series (YLM-LBV0345001H-V2) 3.45" 640x480 24-bit IPS LCD panel
>> +
>> +maintainers:
>> +  - Hironori KIKUCHI <kikuchan98@gmail.com>
>> +
>> +allOf:
>> +  - $ref: panel-common.yaml#
>> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: anbernic,rg35xx-plus-rev6-panel
> 
> Everything is the same here. Add new compatible to existing schema
> respecting compatibility (fallback) or not (no fallback).

BTW, isn't this v2? Where is the changelog and proper versioning of
patches? The changes against previous version are quite unexpected. You
removed specific compatibles and went with wildcard, so this needs
thorough explanation (why standard bindings rules do not apply here).

Anyway next version *will be v3*. Please start using b4 tool.


Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Hironori KIKUCHI]

Hello Krzysztof,

Thank you for reviewing.

> no wildcards

Sorry, but I believe these are not wildcards.

As discussed previously, the integrating vendor and device name are
preferred instead of the OEM serial for unidentified OEM panels.
These compatible strings are based on the actual device names:
  "RG35XX Plus", "RG 40XXV", "RG40XX H", and "RG CubeXX"
You can refer to
https://anbernic.com/collections/handheld-game-console for the full
line-up.

Oh, regarding "rg40xx-panel", it might have been separated to
"rg40xx-v-panel" and "rg40xx-h-panel".


> don't duplicate schemas

The old schemas "leadtek,ltk035c5444t", "fascontek,fs035vg158", and
"anbernic,rg35xx-plus-panel" exist independently.
So I had to add new schemas since the new ones are not compatible with
the old ones.

Perhaps the compatibles should be like this:
  compatible = "anbernic,rg35xx-plus-panel", "newvision,nv3052c";
as some others do.

In this way, the schema files would be a single file and not be messed
up, but it would break the previously defined schemas.

How should I deal with this?
Any suggestions or advice would be greatly appreciated.


> BTW, isn't this v2? Where is the changelog and proper versioning of
> patches?

Sorry, I thought the previous version was completely rejected due to
renaming back to "wl-355608-a8".
https://lore.kernel.org/dri-devel/20241105-maybe-chamomile-7505214f737e@spud/

But yes, these are somewhat relevant, I'll post the next version as v3
with changelogs. Thanks.

Best regards,
kikuchan

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Krzysztof Kozlowski]

On 24/11/2024 20:14, Hironori KIKUCHI wrote:
> Hello Krzysztof,
> 
> Thank you for reviewing.
> 
>> no wildcards
> 
> Sorry, but I believe these are not wildcards.
> 
> As discussed previously, the integrating vendor and device name are
> preferred instead of the OEM serial for unidentified OEM panels.
> These compatible strings are based on the actual device names:
>   "RG35XX Plus", "RG 40XXV", "RG40XX H", and "RG CubeXX"
> You can refer to
> https://anbernic.com/collections/handheld-game-console for the full


Then explain this in commit msg.

> line-up.
> 
> Oh, regarding "rg40xx-panel", it might have been separated to
> "rg40xx-v-panel" and "rg40xx-h-panel".
> 
> 
>> don't duplicate schemas
> 
> The old schemas "leadtek,ltk035c5444t", "fascontek,fs035vg158", and
> "anbernic,rg35xx-plus-panel" exist independently.


So you duplicate them. I wrote: Don't duplicate.

> So I had to add new schemas since the new ones are not compatible with
> the old ones.

No, you do not have to. There is no such thing as schema compatible with
schema.


> 
> Perhaps the compatibles should be like this:
>   compatible = "anbernic,rg35xx-plus-panel", "newvision,nv3052c";
> as some others do.

We do not talk about compatibles.

> 
> In this way, the schema files would be a single file and not be messed
> up, but it would break the previously defined schemas.


What? No, it would not  break. Don't touch existing compatibles.

> 
> How should I deal with this?
> Any suggestions or advice would be greatly appreciated.

The same as with all other changes: add to existing files.

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Hironori KIKUCHI]

Hello Krzysztof,

Thank you for your reply.

> > The old schemas "leadtek,ltk035c5444t", "fascontek,fs035vg158", and
> > "anbernic,rg35xx-plus-panel" exist independently.
> So you duplicate them. I wrote: Don't duplicate.

Ok, thanks. I won't duplicate.

They are already duplicated in the tree with their own file names.
The panels I want to add are not directly relevant to them, so there
is no single file suitable for the panels.

Should I merge these files into a single file with a file name such as
`newvision,nv3052c.yaml`, taken from the driver name?

Best regards,
kikuchan

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Krzysztof Kozlowski]

On 27/11/2024 04:32, Hironori KIKUCHI wrote:
> Hello Krzysztof,
> 
> Thank you for your reply.
> 
>>> The old schemas "leadtek,ltk035c5444t", "fascontek,fs035vg158", and
>>> "anbernic,rg35xx-plus-panel" exist independently.
>> So you duplicate them. I wrote: Don't duplicate.
> 
> Ok, thanks. I won't duplicate.
> 
> They are already duplicated in the tree with their own file names.
> The panels I want to add are not directly relevant to them, so there
> is no single file suitable for the panels.
> 
> Should I merge these files into a single file with a file name such as
> `newvision,nv3052c.yaml`, taken from the driver name?
Add it to the existing anbernic.

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: display: panel: Add another panel for RG35XX Plus (Rev6)

[Chris Morgan]

On Sun, Nov 24, 2024 at 05:02:12PM +0900, Hironori KIKUCHI wrote:
> This is a display panel used in the recent revision of the Anbernic
> RG35XX Plus, a handheld gaming device from Anbernic.
> It is 3.45 inches in size (diagonally) with a resolution of 640x480.
> 
> It has the same interface (pins and connector) as the panel of the former
> revision of RG35XX Plus, but they differ in their init-sequence. So add
> it as a new panel.
> 
> Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
> ---
>  .../anbernic,rg35xx-plus-rev6-panel.yaml      | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
> new file mode 100644
> index 00000000000..b60a4cf00f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-rev6-panel.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Anbernic RG35XX series (YLM-LBV0345001H-V2) 3.45" 640x480 24-bit IPS LCD panel
> +
> +maintainers:
> +  - Hironori KIKUCHI <kikuchan98@gmail.com>
> +
> +allOf:
> +  - $ref: panel-common.yaml#
> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    const: anbernic,rg35xx-plus-rev6-panel
> +
> +  reg:
> +    maxItems: 1
> +
> +  spi-3wire: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - port
> +  - power-supply
> +  - reset-gpios
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +
> +    spi {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        panel@0 {
> +            compatible = "anbernic,rg35xx-plus-rev6-panel";
> +            reg = <0>;
> +
> +            spi-3wire;
> +            spi-max-frequency = <3125000>;
> +
> +            reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
> +
> +            backlight = <&backlight>;
> +            power-supply = <&reg_lcd>;
> +
> +            port {
> +                endpoint {
> +                    remote-endpoint = <&tcon_lcd0_out_lcd>;
> +                };
> +            };
> +        };
> +    };
> -- 
> 2.47.0
> 

Though the documentation file will likely change (to newvision,nv3052c.yaml
if I understand correctly) do we know if "anbernic,rg35xx-plus-rev6-panel" is
an acceptable compatible string for this panel? I'd like to add it to a fixup
in U-Boot but can't proceed until the string is defined.

Thank you,
Chris