From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christo Radev Subject: Re: [PATCH 1/1] ARM: dts: sunxi: Add a olinuxino-lime2-emmc Date: Wed, 4 May 2016 06:07:16 -0700 (PDT) Message-ID: <948be370-4401-43cb-862e-d4376755a75d@googlegroups.com> References: <1461827998-12192-1-git-send-email-oliver@schinagl.nl> <57285162.2000704@schinagl.nl> <5729F07C.3080308@schinagl.nl> Reply-To: christo.radev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_316_1707913696.1462367236878" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <5729F07C.3080308-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi Cc: radoslav.kolev-1W28NRE8jL9DPfheJLI6IQ@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, tsvetan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, dev-3kdeTeqwOZ9EV1b7eY7vFQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, oliver-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org List-Id: devicetree@vger.kernel.org ------=_Part_316_1707913696.1462367236878 Content-Type: multipart/alternative; boundary="----=_Part_317_1734458210.1462367236878" ------=_Part_317_1734458210.1462367236878 Content-Type: text/plain; charset=UTF-8 Hi Olliver, I have already test it a few weeks ago and definitely can say that 8-bit bus did not work on A20-Olinuxino-Lime2-eMMC with mainline kernel. See may post here . Best regards Chris On Wednesday, May 4, 2016 at 3:52:17 PM UTC+3, Olliver Schinagl wrote: > > Hey Radoslav, > > On 04-05-16 14:30, Radoslav Kolev wrote: > > 2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai >: > >> On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl > wrote: > >>>>> + bus-width = <4>; > >>>> Only 4 bits? We normally see eMMC with 8 bits. 4 bits are some kind > of > >>>> embedded SD card. > >>> On A20 as well? Our investigations so far have concluded that the A10 > and > >>> A20 have those pins not mapped out to pads. The IP does support it > however > >>> we assume. > >> You're right. My bad. First time A10/A20 sees eMMC support. > > I can't say anything about A10/A20, but I have a board with A13 and > > the same eMMC chip and it works fine in 8 bit mode. > Yep, sun5i actually brings them all out to pads, the A20 however does > not :( We first thought that the A20 would also be an 8bitter, because > the mmc IP appears to be the same as sun5i, but initial tests show it is > not. As for A10, it has older IP and it might not even support 8 bit > mode, let alone bring out the pins. > > But with A20's + eMMC being available via the lime2, others may repeat > my experiments! The lime2 is 8 bit connected. > > Olliver > > > > Regards, > > Radoslav > > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ------=_Part_317_1734458210.1462367236878 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Hi Olliver,

I have already test it a few weeks ago = and definitely can say that 8-bit bus did not work on A20-Olinuxino-Lime2-e= MMC with mainline kernel.
See may post here.
Best regards

Chris

On Wednesday, May 4, 2016 at 3:52:17 = PM UTC+3, Olliver Schinagl wrote:
Hey Radoslav,

On 04-05-16 14:30, Radoslav Kolev wrote:
> 2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai <we...-jdAy2FN1RRM@public.gmane.org>:
>> On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl <oli...@schin= agl.nl> wrote:
>>>>> + =C2=A0 =C2=A0 =C2=A0 bus-width =3D <4>;
>>>> Only 4 bits? We normally see eMMC with 8 bits. 4 bits = are some kind of
>>>> embedded SD card.
>>> On A20 as well? Our investigations so far have concluded t= hat the A10 and
>>> A20 have those pins not mapped out to pads. The IP does su= pport it however
>>> we assume.
>> You're right. My bad. First time A10/A20 sees eMMC support= .
> I can't say anything about A10/A20, but I have a board with A1= 3 and
> the same eMMC chip and it works fine in 8 bit mode.
Yep, sun5i actually brings them all out to pads, the A20 however does= =20
not :( We first thought that the A20 would also be an 8bitter, because= =20
the mmc IP appears to be the same as sun5i, but initial tests show it i= s=20
not. As for A10, it has older IP and it might not even support 8 bit=20
mode, let alone bring out the pins.

But with A20's + eMMC being available via the lime2, others may rep= eat=20
my experiments! The lime2 is 8 bit connected.

Olliver
>
> Regards,
> Radoslav

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