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Tue, 17 Mar 2020 04:09:26 -0700 Received: from xsj-pvapsmtp01 (mailhub.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 02HB9Nvv030310; Tue, 17 Mar 2020 04:09:24 -0700 Received: from [172.30.17.108] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jEA67-0005YE-MG; Tue, 17 Mar 2020 04:09:23 -0700 Subject: Re: [PATCH 0/6] soc: xilinx: vcu: provide interfaces for other drivers To: Michael Tretter , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Michal Simek , Rob Herring , Dhaval Shah , kernel@pengutronix.de, Rohit Visavalia References: <20200317094115.15896-1-m.tretter@pengutronix.de> From: Michal Simek Message-ID: <94a11283-bf63-d6b0-e7ed-7337d9c3df52@xilinx.com> Date: Tue, 17 Mar 2020 12:09:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200317094115.15896-1-m.tretter@pengutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(136003)(396003)(346002)(39860400002)(376002)(199004)(46966005)(9786002)(316002)(356004)(31696002)(8936002)(81166006)(107886003)(5660300002)(8676002)(81156014)(4326008)(36756003)(2906002)(70586007)(70206006)(26005)(54906003)(186003)(47076004)(44832011)(31686004)(336012)(426003)(2616005)(478600001);DIR:OUT;SFP:1101;SCL:1;SRVR:BYAPR02MB5957;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fb09dfea-d275-450d-73b3-08d7ca63ab8f X-MS-TrafficTypeDiagnostic: BYAPR02MB5957: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 0345CFD558 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Cfqvpi93E3Ki0PAkC3kg3pk2NRTKMIvd+EcwsbSSLXWEnF7o1D1WsSZuQ5X1d3yiRyZFxGBwPhC57Jgkz2CnqdYplvraaqwaV3wADJ586T5B/36iXZgTm9HbBDQYgvjnNdLywzaXZnGEQaIZ5d9mtuMOV9kTtncLGFgS+oSwfyg1RT0Ygdh1JQqWdB4NBlGECba8PKQS6u3M2KNBQt4NqFJMqtJIwGO41Fj+M4d0uNlQh/527dBYBanQUgxCkomcupkExUe8NP7ShxNPrIgL0A4QYraQhrd+vPaf88jwIELv0F3Vnenu2N1zz3otbEkPKLTy/ZxsoGHnrEsjJKk4Fuuz1dMxiclYVpAAfgShl8VNvJ6EI8E9BljKrGJeuFJQQRzuK6mJQ6IQMPs9Rx6ufnzRUMyKak0BZXlQAci5m+Y1QupGxkTbOtrj/AcwJw1vCD85VEyYTAnImp2xTvbnst+qlJKPnLpztPDDKnytx0Z5Iy8wjzRP8/naycBTUzJn X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2020 11:09:32.3611 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb09dfea-d275-450d-73b3-08d7ca63ab8f X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5957 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17. 03. 20 10:41, Michael Tretter wrote: > Hello, > > The Xilinx VCU is glue for integrating the Allegro DVT codec into the ZynqMP > PL infrastructure. This glue is responsible for generating the clocks for the > actual codec and provides registers for reading the codec configuration. Other > drivers, e.g. the allegro-dvt driver, need to interact or at least read > information from the xlnx_vcu driver. > > Therefore, the xlnx_vcu driver should provide its clocks for other drivers and > register the generated clocks in the clock tree. This allows other drivers to > simply get the clock rate via the usual interface. > > It is not so simple for the second register bank (called "logicoreip" in the > original binding), because there are various registers for the encoder, the > decoder and common stuff (see PG252, H.264/H.265 Video Codec Unit v1.2, p. > 14). Therefore, I decided to extract a separate binding for this register > bank, call it "xlnx,vcu-settings" and use a syscon interface that can be used > by the xlnx_vcu driver and other drivers that need this information. > > I'm not too happy with this solution, but I couldn't come up with a better > solution without inventing a new interface, which I really don't want to do > for that use case. > > I kept the behavior of the xlnx_vcu driver backwards compatible, to avoid > breaking systems that use device trees with the xlnx,vcu device tree node as > generated by Vivado, but to be able to use the register bank from other > drivers, you must use the new binding. > > Michael > > Michael Tretter (6): > soc: xilinx: vcu: drop useless success message > ARM: dts: define indexes for output clocks > soc: xilinx: vcu: implement clock provider for output clocks > dt-bindings: soc: xlnx: extract xlnx,vcu-settings to separate binding > soc: xilinx: vcu: use vcu-settings syscon registers > soc: xilinx: vcu: add missing register NUM_CORE > > .../soc/xilinx/xlnx,vcu-settings.yaml | 45 +++++ > .../bindings/soc/xilinx/xlnx,vcu.txt | 9 +- > drivers/soc/xilinx/Kconfig | 3 +- > drivers/soc/xilinx/xlnx_vcu.c | 163 ++++++++++++------ > include/dt-bindings/clock/xlnx-vcu.h | 15 ++ > include/linux/mfd/syscon/xlnx-vcu.h | 39 +++++ > 6 files changed, 216 insertions(+), 58 deletions(-) > create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu-settings.yaml > create mode 100644 include/dt-bindings/clock/xlnx-vcu.h > create mode 100644 include/linux/mfd/syscon/xlnx-vcu.h > Rohit: Please take a look at this series and also take a look at missing pieces we have in soc vendor tree. Thanks, Michal