From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B36687483 for ; Fri, 6 Dec 2024 00:18:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733444292; cv=none; b=M9iO1qwRSCksE7G9xcXfk2DC3b+YqlydXoxgr5/t0DiV+CAbbARS0npw8jm/nFZLYQ9o3krUT7BINc5C765YwicZVbrNsIQITeIcVGzgdtEfeApavqOiJuuja7wX3WGbbGjb4Vvq/rwtkUUE2sJdWsXn1RlU/BNFvBSLfpYVYQo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733444292; c=relaxed/simple; bh=Gq0Hea2MRYQsma0mjR3BrHNepL3RPWosqV5rbeP7wdY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=eA0j6Jd3yU1u+g4fO9Sr7RT8Hw1HQolHx7Biif9AUskk4i9hWlSGsC3x549TiFcfjr17ZmhNS7ki+KBhRMiOaQ/g74uM1OnKIvrru5BLp1iMscWr5avGqAkoYOoLficGTfTCA1xIhupF3LnIHZTEubfRVR8Qs4p5fNry2qQasR4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=kDDaJfX5; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kDDaJfX5" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-434a9f2da82so10489595e9.2 for ; Thu, 05 Dec 2024 16:18:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733444289; x=1734049089; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=CGAcnGwoL081zwlf2nuNQtt9U8WYH4jOf6npODFj/BU=; b=kDDaJfX50DCUutk3FM99oSyQZ1is00wCVnZwGjgZ/HmE0yRJJVnO3LEXmQqUQae4i6 NI8/6boyvpcMG6vX9c9vkh988RE0miUfQV3DKYVZmyqTIm0NIWa0n4sNLtjkg9F6pEqQ P6MlC5GrbtgWXT8jUa7nfuqXzOFh7TYIfSYArYG9HMfeUM/0LrUgpM7AgFUI9s8RaW6n 2/NxNv+3cwi9o3qupLTs1AeJr2q8EvFxuM6ZTGPge2ji/0Srfw8X4hUmti20dVAFmbwh MPzXsUOspM3LyulB/twcTlSKTbo7CJCLAhM7U43RfNuZIbt8SZa8f4QMXvueguc/6rPj +NlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733444289; x=1734049089; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CGAcnGwoL081zwlf2nuNQtt9U8WYH4jOf6npODFj/BU=; b=l74dOL5kOyU3wfJjLMoUtI6caBM24HGukZX4+1fHZ2lZYKmWIXRaJMTEgmCE2MWjyR XGnvOsYs7eBVtOsWrNbg3xMmEH3uhZt6vUypLqkMKcYGZeEn4DmKj4EzahGMNCeO3Zi8 y94PWjNS3v8bZmeXZ4DF2GldQ4JfE/86FeOQEeBhaAGybbYAozqovVovD+JfeQG6uHB0 xukfNAOmGjcDkFyzXs7UId4UQp5yZglDTkt1SC7kaT58ZCberClyB/mw21PsnWORJfoo T7TU1dODw/yXAohbFX3Obq/MHM7iWvh58lbsAfm4fgSey9+U/XaD1hXui9iiTDsVlEqk wUFg== X-Forwarded-Encrypted: i=1; AJvYcCXOV8nNRmxsfp/z9d++ap7qIp5MxLpQ0OWWj5JHVqMhlzwVK628eoH52KyG7+lsoKp/hONgVh/zzH8C@vger.kernel.org X-Gm-Message-State: AOJu0YymhfbLufXl+/6gfCZaB+0HwK3o9I6AlIQAE1VQmxSqlmfh53vN e6SHB0pj8IEzVlm9N3pSyfTOzZ+DfQXyEmZYvHFHvWOSD0W8pPY5Nr9NkjhGdwk= X-Gm-Gg: ASbGncuCQeZA/xonIs+0L1PX3buq9EDI9qsCBp7dOvtUs7B//MYMWHQG5XC1oC5jhxN MI9d3u/mk4hsZT0e/Z7HF0jma5pR9sxjGJWqjKb1WBQvqmYuIWIyqfTnC+YyogOSU8QkTkgdDeq S78lHFklvwH5mBuim4IO7vnmF+HcLxhWowKqfV8bW11czxEAjDqTs2rR/VJw0WqjwDkuXbVh6IL fyPa8sE6PX13hnTYJjthRKcRGrBsn+z4BwSewEBJi9QnG5CRkWo+jRKzEi3PE4= X-Google-Smtp-Source: AGHT+IFAX4gucoS+78NfGmbHyjHUmW+8YUgpUKEnM2Xy9lSdmOMzks/mhYVpl53glsUJdxyICIOjjg== X-Received: by 2002:a05:600c:a0b:b0:434:a734:d268 with SMTP id 5b1f17b1804b1-434ddead34cmr9526015e9.14.1733444288977; Thu, 05 Dec 2024 16:18:08 -0800 (PST) Received: from [192.168.0.40] ([176.61.106.227]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3861ecf406csm3339050f8f.3.2024.12.05.16.18.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Dec 2024 16:18:07 -0800 (PST) Message-ID: <94a753ab-9fe6-43b4-aa50-cf94a55db8f9@linaro.org> Date: Fri, 6 Dec 2024 00:18:05 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 16/16] media: qcom: camss: Add support for VFE hardware version Titan 780 To: Depeng Shao , rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vladimir.zapolskiy@linaro.org Cc: quic_eberman@quicinc.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com, Yongsheng Li References: <20241205155538.250743-1-quic_depengs@quicinc.com> <20241205155538.250743-17-quic_depengs@quicinc.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20241205155538.250743-17-quic_depengs@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Just to re-illustriate the point "[PATCH 16/16] media: qcom: camss: Add support for VFE hardware version Titan 780" You have CSID 780 + sm8550 in the CSID patch but VFE for Titan 780. Just "VFE 780" please On 05/12/2024 15:55, Depeng Shao wrote: > Add support for VFE found on SM8550 (Titan 780). This implementation is > based on the titan 480 implementation. It supports the normal and lite > VFE. > > Co-developed-by: Yongsheng Li > Signed-off-by: Yongsheng Li > Signed-off-by: Depeng Shao > --- > drivers/media/platform/qcom/camss/Makefile | 1 + > .../media/platform/qcom/camss/camss-vfe-780.c | 159 ++++++++++++++++++ > drivers/media/platform/qcom/camss/camss-vfe.c | 2 + > drivers/media/platform/qcom/camss/camss-vfe.h | 1 + > drivers/media/platform/qcom/camss/camss.c | 121 +++++++++++++ > 5 files changed, 284 insertions(+) > create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-780.c > > diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile > index 9a723e8712a2..f6db5b3b5ace 100644 > --- a/drivers/media/platform/qcom/camss/Makefile > +++ b/drivers/media/platform/qcom/camss/Makefile > @@ -17,6 +17,7 @@ qcom-camss-objs += \ > camss-vfe-4-8.o \ > camss-vfe-17x.o \ > camss-vfe-480.o \ > + camss-vfe-780.o \ > camss-vfe-gen1.o \ > camss-vfe.o \ > camss-video.o \ > diff --git a/drivers/media/platform/qcom/camss/camss-vfe-780.c b/drivers/media/platform/qcom/camss/camss-vfe-780.c > new file mode 100644 > index 000000000000..b9812d70f91b > --- /dev/null > +++ b/drivers/media/platform/qcom/camss/camss-vfe-780.c > @@ -0,0 +1,159 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550) > + * > + * Copyright (c) 2024 Qualcomm Technologies, Inc. > + */ > + > +#include > +#include > +#include > + > +#include "camss.h" > +#include "camss-vfe.h" > + > +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00) > + > +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) > +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) > + > +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC) > + > +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) > +#define WM_CFG_EN BIT(0) > +#define WM_VIR_FRM_EN BIT(1) > +#define WM_CFG_MODE BIT(16) > +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) > +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) > +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) > +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) > +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) > +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) > +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) > + > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) > +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) > +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) > + > +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) > +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) > + > +/* > + * Bus client mapping: > + * > + * Full VFE: > + * 23 = RDI0, 24 = RDI1, 25 = RDI2 > + * > + * VFE LITE: > + * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4 > + */ > +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) > + > +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) > +{ > + struct v4l2_pix_format_mplane *pix = > + &line->video_out.active_fmt.fmt.pix_mp; > + > + wm = RDI_WM(wm); > + > + /* no clock gating at bus input */ > + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); > + > + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); > + > + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, > + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); > + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), > + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); > + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, > + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); > + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); > + > + /* no dropped frames, one irq per frame */ > + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); > + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); > + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); > + > + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); > + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); > + > + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) > +{ > + wm = RDI_WM(wm); > + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); > +} > + > +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, > + struct vfe_line *line) > +{ > + wm = RDI_WM(wm); > + writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); > + > + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", > + wm, addr); > +} > + > +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, false); > +} > + > +static inline void vfe_reg_update_clear(struct vfe_device *vfe, > + enum vfe_line_id line_id) > +{ > + int port_id = line_id; > + > + camss_reg_update(vfe->camss, vfe->id, port_id, true); > +} > + > +static const struct camss_video_ops vfe_video_ops_780 = { > + .queue_buffer = vfe_queue_buffer_v2, > + .flush_buffers = vfe_flush_buffers, > +}; > + > +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) > +{ > + vfe->video_ops = vfe_video_ops_780; > +} > + > +static void vfe_global_reset(struct vfe_device *vfe) > +{ > + vfe_isr_reset_ack(vfe); > +} > + > +static irqreturn_t vfe_isr(int irq, void *dev) > +{ > + /* nop */ > + return IRQ_HANDLED; > +} > + > +static int vfe_halt(struct vfe_device *vfe) > +{ > + /* rely on vfe_disable_output() to stop the VFE */ > + return 0; > +} > + > +const struct vfe_hw_ops vfe_ops_780 = { > + .global_reset = vfe_global_reset, > + .hw_version = vfe_hw_version, > + .isr = vfe_isr, > + .pm_domain_off = vfe_pm_domain_off, > + .pm_domain_on = vfe_pm_domain_on, > + .reg_update = vfe_reg_update, > + .reg_update_clear = vfe_reg_update_clear, > + .subdev_init = vfe_subdev_init, > + .vfe_disable = vfe_disable, > + .vfe_enable = vfe_enable_v2, > + .vfe_halt = vfe_halt, > + .vfe_wm_start = vfe_wm_start, > + .vfe_wm_stop = vfe_wm_stop, > + .vfe_buf_done = vfe_buf_done, > + .vfe_wm_update = vfe_wm_update, > +}; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index 1c9b6569fbe5..c95b127a7e2e 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -344,6 +344,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > case CAMSS_845: > case CAMSS_8250: > case CAMSS_8280XP: > + case CAMSS_8550: > switch (sink_code) { > case MEDIA_BUS_FMT_YUYV8_1X16: > { > @@ -1964,6 +1965,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > case CAMSS_845: > case CAMSS_8250: > case CAMSS_8280XP: > + case CAMSS_8550: > ret = 16; > break; > default: > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h > index 977710d6655e..2a2e2d82dd51 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.h > +++ b/drivers/media/platform/qcom/camss/camss-vfe.h > @@ -242,6 +242,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; > extern const struct vfe_hw_ops vfe_ops_4_8; > extern const struct vfe_hw_ops vfe_ops_170; > extern const struct vfe_hw_ops vfe_ops_480; > +extern const struct vfe_hw_ops vfe_ops_780; > > int vfe_get(struct vfe_device *vfe); > void vfe_put(struct vfe_device *vfe); > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index c0e336f3916b..e8cc96d3d0d2 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -1823,6 +1823,125 @@ static const struct camss_subdev_resources csid_res_8550[] = { > } > }; > > +static const struct camss_subdev_resources vfe_res_8550[] = { > + /* VFE0 */ > + { > + .regulators = {}, > + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe0_fast_ahb", > + "vfe0", "cpas_vfe0", "camnoc_axi" }, > + .clock_rate = { { 0 }, > + { 80000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 466000000, 594000000, 675000000, 785000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 } }, > + .reg = { "vfe0" }, > + .interrupt = { "vfe0" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife0", > + .hw_ops = &vfe_ops_780, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE1 */ > + { > + .regulators = {}, > + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe1_fast_ahb", > + "vfe1", "cpas_vfe1", "camnoc_axi" }, > + .clock_rate = { { 0 }, > + { 80000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 466000000, 594000000, 675000000, 785000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 } }, > + .reg = { "vfe1" }, > + .interrupt = { "vfe1" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife1", > + .hw_ops = &vfe_ops_780, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE2 */ > + { > + .regulators = {}, > + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe2_fast_ahb", > + "vfe2", "cpas_vfe2", "camnoc_axi" }, > + .clock_rate = { { 0 }, > + { 80000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 466000000, 594000000, 675000000, 785000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 } }, > + .reg = { "vfe2" }, > + .interrupt = { "vfe2" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife2", > + .hw_ops = &vfe_ops_780, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE3 lite */ > + { > + .regulators = {}, > + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb", > + "vfe_lite", "cpas_ife_lite", "camnoc_axi" }, > + .clock_rate = { { 0 }, > + { 80000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 400000000, 480000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 } }, > + .reg = { "vfe_lite0" }, > + .interrupt = { "vfe_lite0" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_780, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE4 lite */ > + { > + .regulators = {}, > + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb", > + "vfe_lite", "cpas_ife_lite", "camnoc_axi" }, > + .clock_rate = { { 0 }, > + { 80000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 }, > + { 400000000, 480000000 }, > + { 300000000, 400000000 }, > + { 300000000, 400000000 } }, > + .reg = { "vfe_lite1" }, > + .interrupt = { "vfe_lite1" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_780, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > +}; > + > static const struct resources_icc icc_res_sm8550[] = { > { > .name = "ahb", > @@ -2861,11 +2980,13 @@ static const struct camss_resources sm8550_resources = { > .pd_name = "top", > .csiphy_res = csiphy_res_8550, > .csid_res = csid_res_8550, > + .vfe_res = vfe_res_8550, > .csid_wrapper_res = &csid_wrapper_res_sm8550, > .icc_res = icc_res_sm8550, > .icc_path_num = ARRAY_SIZE(icc_res_sm8550), > .csiphy_num = ARRAY_SIZE(csiphy_res_8550), > .csid_num = ARRAY_SIZE(csid_res_8550), > + .vfe_num = ARRAY_SIZE(vfe_res_8550), > .link_entities = camss_link_entities > }; > Assuming you update the title of the patch, you can add: Reviewed-by: Bryan O'Donoghue