* [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver
@ 2023-01-13 16:17 Biju Das
2023-01-13 16:17 ` [PATCH v11 1/6] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2023-01-25 19:48 ` [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
0 siblings, 2 replies; 4+ messages in thread
From: Biju Das @ 2023-01-13 16:17 UTC (permalink / raw)
To: Rob Herring, Philipp Zabel, Daniel Lezcano,
William Breathitt Gray, Thierry Reding, Uwe Kleine-König,
Krzysztof Kozlowski
Cc: Biju Das, Thomas Gleixner, devicetree, Geert Uytterhoeven,
Chris Paterson, Prabhakar Mahadev Lad, linux-renesas-soc
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
This patch series aims to add core, counter and pwm driver for
MTU3a. The core instantiates child devices using mfd api.
The 8/16/32 bit registers are mixed in each channel. The HW
specifications of the IP is described in patch#1.
Current patch set is tested for PWM mode1 on MTU3 channel
and 16 and 32 bit phase counting modes on MTU1 and MTU2 channels.
There is a plan to add clock event driver later for Power management.
Ref:
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221010145222.1047748-2-biju.das.jz@bp.renesas.com/
v10->v11:
* Added Rb tag from William Breathitt Gray for the driver patch
* Replaced count2 channel name from "combined"->"cascaded", as channels
are cascaded
* Simplified the locking by adding the helper functions
rz_mtu3_lock_if_counter_is_valid, rz_mtu3_lock_if_count_is_enabled,
and rz_mtu3_lock_if_ch0_is_enabled.
* Added the MAINTAINERS entries for the driver.
v9->v10:
* Added logs from PWM and counter
* Added Rb tag from William Breathitt Gray for sysfs counter doc
* Added helper function for rz_mtu3_count_{action,function}_read
* Added priv->lock in rz_mtu3_count_function_read and rz_mtu3_count_
direction_read.
* Added ch->is_busy check for rz_mtu3_action_read()
* Added rz_mtu3_is_ch0_enabled() for device specific sysfs variables.
* Added ch->is_busy check for device specific sysfs variables.
v8->v9:
* Added prescale/duty_cycle variables to struct rz_mtu3_pwm_chip and
cached this values in rz_mtu3_pwm_config and used this cached values
in get_state(), if PWM is disabled.
* Added return code for get_state().
* Added available blocks for external_input_phase_clock_select_available
* Removed the "This attribute" from the external_input_phase_clock_select
description, and capitalize the word "counter" from description.
* Removed the "This attribute" from the cascade_counts_enable description,
and capitalize "counts" and "counter"
* Moved these device-level configuration blocks to top of the file.
* Added count_is_enabled variable to struct rz_mtu3_cnt
* Added check for ch->is_busy and count_is_enabled before every Counter
callback to ensure we do not try to access a busy channel used by other
subsystem(eg: pwm).
* Removed id parameter from rz_mtu3_32bit_cnt_setting()
* Made definition of rz_mtu3_get_ch() in single line.
* Replaced break->return in rz_mtu3_32bit_cnt_setting(),
rz_mtu3_count_function_read() and rz_mtu3_initialize_counter()
and removed redundant return 0.
* Simplified synapse signal check for rz_mtu3_action_read().
v7->v8:
* Add locking for RMW on rz_mtu3_shared_reg_update_bit()
* Replaced enum rz_mtu3_functions with channel busy flag
* Added API for request and release a channel.
* Replaced cascade_enable->cascade_counts_enable
* Updated commit header and description
* Added external_input_phase_clock_select_available entry for driver-
specific enum attribute and created a new entry block for it.
* Add a line stating cascade_counts_enable is a boolean attribute.
* Added missing 'component_id' suffix.
* Simplified rz_mtu3_initialize_counter by calling rz_mtu3_request_
channel() and release the acquired sibling channel in case of error.
* Simplified rz_mtu3_terminate_counter by calling rz_mtu3_release_
channel().
* Removed unused ceiling and ch_id from rz_mtu3_count_write()
* Replaced the error -EINVAL->-EBUSY for rz_mtu3_is_counter_invalid()
* Avoided race between rz_mtu3_count_{read, write} with rz_mtu3_
cascade_counts_enable_set() by adding locks and moved the lock
before rz_mtu3_is_counter_invalid()
* Protected the rz_mtu3_count_ceiling_read() function with a lock
to make sure the cascade operation mode doesn't not change and
that the priv data structure accesses don't race when they are
changed in the ceiling_write() callback.
* Added lock in rz_mtu3_cascade_enable_set() to make sure the other
callbacks don't try to read the LWA state while updating LWA.
* Added lock in rz_mtu3_ext_input_phase_clock_select_set() to ensure
the other callbacks don't try to read the PHCKSEL state while updating
PHCKSEL.
* Added lock to avoid race between rz_mtu3_count_function_write() and
rz_mtu3_action_read()
* Updated rz_mtu3_action_read to return 0, if Synapse is in COUNTER_SYNAPSE
_ACTION_NONE state.
* Replaced sysfs variable cascade_enable->cascade_counts_enable
* Renamed rz_mtu3_cascade_enable_get->rz_mtu3_cascade_counts_enable_get
* Renamed rz_mtu3_cascade_enable_set->rz_mtu3_cascade_counts_enable_set
* Removed redundent ceiling assignment from rz_mtu3_count_ceiling_read()
* Removed unused ceiling and ch_id from rz_mtu3_count_write().
* Simplified rz_mtu3_pwm_request by calling rz_mtu3_request_channel()
* Simplified rz_mtu3_pwm_free by calling rz_mtu3_release_channel()
v6->v7:
* Added channel specific mutex to avoid races between child devices
(for eg: pwm and counter).
* Added rz_mtu3_shared_reg_update_bit() to update bits.
* Replaced sysfs variable "long_word_access_ctrl_mode->cascade_enable"
* Updated Kernel version in sysfs Documentation
* Updated commit description for counter driver
* Added Register descriptions
* Opimized size of cache variable by using union
* Used test_bit() in rz_mtu3_is_counter_invalid()
* Replaced val->timer_mode in rz_mtu3_count_function_{read,write}
* Added TODO comment phase3 and phase5 modes.
* replaced if-else with ternary expression in rz_mtu3_count_direction_read()
* Used switch statement in rz_mtu3_count_ceiling_read to consistent with write
* Provided default case for all switch statements.
* Add mutex lock for avoiding races with other devices and counter
* Updated comments in rz_mtu3_action_read()
* Replaced COUNTER_COMP_DEVICE_BOOL->COUNTER_COMP_DEVICE_BOOL for
cascade_enable
* Replaced RZ_MTU3_GET_HW_CH->rz_mtu3_get_hw_ch
* Added rz_mtu3_get_ch() to get channels
* used rz_mtu3_shared_reg_update_bit for cascade_enable and
selecting phase input clock.
* Added rz_mtu3_is_counter_invalid() check in rz_mtu3_count_ceiling_read()
* Added channel specific mutex lock to avoid race between counter
device and rz_mtu3_pwm_{request,free}
* Added pm_runtime_resume_and_get in rz_mtu3_pwm_enable()
* Added pm_runtime_put_sync in rz_mtu3_pwm_disable()
* Updated rz_mtu3_pwm_config()
* Updated rz_mtu3_pwm_apply()
v5->v6:
* Added Rb tag from Rob and Krzysztof for the binding patch.
* Updated commit and KConfig description for the driver patches
* Selected MFD_CORE to avoid build error if CONFIG_MFD_CORE not set.
* Improved error handling in core driver's probe().
* Fixed RZ_MTU3_GET_HW_CH Macro for argument reuse 'id' -
possible side-effects?
* Replaced SET_RUNTIME_PM_OPS->DEFINE_RUNTIME_DEV_PM_OPS and removed
__maybe_unused from suspend/resume()
* Replaced dev_get_drvdata from rz_mtu3_pwm_pm_disable()
* Sorted header files for all driver files.
v4->v5:
* Modelled as timer bindings.
* Fixed the typo in bindings.
* Moved core driver from MFD to timer
* Child devices instatiated using mfd_add_devices()
* Documented sysfs entries external_input_phase_clock_select and
long_word_access_ctrl_mode.
* Updated the Kconfig with SoC vendor name
* Introduced rz_mtu3_is_counter_invalid()
* replaced pointer to an array of struct rz_mtu3_channel with
a simple pointer to struct rz_mtu3_channel.
* Added long_word_access_ctrl_mode sysfs entry for 16-bit and
32-bit access
* Added external_input_phase_clock_select sysfs entry for
selecting input clocks.
* used preprocessor defines represent SIGNAL_{A,B,C,D}_ID instead of
signal ids.
v3->v4:
* Dropped counter and pwm compatibeles as they don't have any resources.
* Made rz-mtu3 as pwm provider.
* Updated the example and description.
* A single driver that registers both the counter and the pwm functionalities
that binds against "renesas,rz-mtu3".
* Moved PM handling from child devices to here.
* replaced include/linux/mfd/rz-mtu3.h->drivers/mfd/rz-mtu3.h
* Removed "remove" callback from mfd driver
* There is no resource associated with "rz-mtu3-counter" and "rz-mtu3-pwm"
compatible and moved the code to mfd subsystem as it binds against "rz-mtu".
* Removed struct platform_driver rz_mtu3_cnt_driver.
* Removed struct platform_driver rz_mtu3_pwm_driver.
* Updated commit description
* Updated Kconfig description
* Added macros RZ_MTU3_16_BIT_MTU{1,2}_CH for MTU1 and MTU2 channels
* Added RZ_MTU3_GET_HW_CH macro for getting channel ID.
* replaced priv->ch[id]->priv->ch[0] in rz_mtu3_count_read()
* Cached counter max values
* replaced cnt->tsr in rz_mtu3_count_direction_read()
* Added comments for RZ_MTU3_TCR_CCLR_NONE
* Replaced if with switch in rz_mtu3_initialize_counter() and
rz_mtu3_count_ceiling_write()
* Added locks in initialize, terminate and enable_read to prevent races.
* Updated rz_mtu3_action_read to take care of MTU2 signals.
* Added separate distinct array for each group of Synapse.
* Moved pm handling to parent.
v2->v3:
* Dropped counter bindings and integrated with mfd as it has only one property.
* Removed "#address-cells" and "#size-cells" as it do not have children with
unit addresses.
* Removed quotes from counter and pwm.
* Provided full path for pwm bindings.
* Updated the binding example.
* removed unwanted header files
* Added LUT for 32 bit registers as it needed for 32-bit cascade counting.
* Exported 32 bit read/write functions.
* Modelled as a counter device supporting 3 counters(2 16-bit and
32-bit)
* Add kernel-doc comments to document struct rz_mtu3_cnt
* Removed mmio variable from struct rz_mtu3_cnt
* Removed cnt local variable from rz_mtu3_count_read()
* Replaced -EINVAL->-ERANGE for out of range error conditions.
* Removed explicit cast from write functions.
* Removed local variable val from rz_mtu3_count_ceiling_read()
* Added lock for RMW for counter/ceiling updates.
* Added different synapses for counter0 and counter{1,2}
* Used ARRAY for assigning num_counts.
* Added PM runtime for managing clocks.
* Add MODULE_IMPORT_NS(COUNTER) to import the COUNTER namespace.
RFC->v2:
* replaced devm_reset_control_get->devm_reset_control_get_exclusive
* Dropped 'bindings' from the binding title
* Updated the binding example
* Added additionalProperties: false for counter bindings
* Squashed all the binding patches
* Modelled as a single counter device providing both 16-bit
and 32-bit phase counting modes
* Modelled as a single pwm device for supporting different pwm modes.
* Moved counter and pwm bindings to respective subsystems.
Logs:
root@smarc-rzg2l:/# /mtu_test.sh
#### Zero duty cycle ###
#### decrement Period ###
#### Increment Period ###
#### decrement duty cycle ###
#### Increment duty cycle ###
### Unbind the PWM driver####
### Bind the PWM driver####
Positive counting
cascade_counts_enable is 0
#### Ch0 count
0
2
8
13
18
23
28
33
38
44
50
3
9
14
19
24
29
35
39
45
#### Ch1 count
#### Select Phase clock
Phase clock MTCLKA-MTCLKB
0
5
10
15
20
4
10
14
20
3
9
14
19
3
8
14
18
3
7
13
#### Select Phase clock
Phase clock MTCLKA-MTCLKB
cascade_counts_enable is 1
#### Ch2 count
0
5
10
15
21
25
31
36
41
46
51
56
61
67
71
77
82
87
92
97
### Unbind the counter driver####
### Bind the counter driver####
### Unbind the Core driver####
### Bind the Core driver####
Read at address 0x11010538 (0xffffb1aaa538): 0x00000000
root@smarc-rzg2l:/#
Biju Das (6):
dt-bindings: timer: Document RZ/G2L MTU3a bindings
clocksource/drivers: Add Renesas RZ/G2L MTU3a core driver
Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and
external_input_phase_clock_select
counter: Add Renesas RZ/G2L MTU3a counter driver
MAINTAINERS: Add entries for Renesas RZ/G2L MTU3a counter driver
pwm: Add Renesas RZ/G2L MTU3a PWM driver
Documentation/ABI/testing/sysfs-bus-counter | 32 +
.../bindings/timer/renesas,rz-mtu3.yaml | 302 ++++++
MAINTAINERS | 8 +
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/rz-mtu3.c | 459 +++++++++
drivers/counter/Kconfig | 11 +
drivers/counter/Makefile | 1 +
drivers/counter/rz-mtu3-cnt.c | 903 ++++++++++++++++++
drivers/pwm/Kconfig | 11 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rz-mtu3.c | 486 ++++++++++
include/clocksource/rz-mtu3.h | 237 +++++
13 files changed, 2463 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
create mode 100644 drivers/clocksource/rz-mtu3.c
create mode 100644 drivers/counter/rz-mtu3-cnt.c
create mode 100644 drivers/pwm/pwm-rz-mtu3.c
create mode 100644 include/clocksource/rz-mtu3.h
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v11 1/6] dt-bindings: timer: Document RZ/G2L MTU3a bindings
2023-01-13 16:17 [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
@ 2023-01-13 16:17 ` Biju Das
2023-01-25 19:48 ` [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
1 sibling, 0 replies; 4+ messages in thread
From: Biju Das @ 2023-01-13 16:17 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Daniel Lezcano, Thomas Gleixner, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc, Krzysztof Kozlowski, Rob Herring
The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in
the Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer
channels and one 32-bit timer channel. It supports the following
functions
- Counter
- Timer
- PWM
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Ref:
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221010145222.1047748-2-biju.das.jz@bp.renesas.com/
v10->v11:
* No change
v9->v10:
* No change
v8->v9:
* No change
v7->v8:
* No change
v6->v7:
* No change
v5->v6:
* Added Rb tag from Rob and Krzysztof.
v4->v5:
* Modelled as timer bindings.
* Fixed the typo.
v3->v4:
* Dropped counter and pwm compatibeles as they don't have any resources.
* Made rz-mtu3 as pwm provider.
* Updated the example and description.
v2->v3:
* Dropped counter bindings and integrated with mfd as it has only one property.
* Removed "#address-cells" and "#size-cells" as it do not have children with
unit addresses.
* Removed quotes from counter and pwm.
* Provided full path for pwm bindings.
* Updated the example.
v1->v2:
* Modelled counter and pwm as a single device that handles
multiple channels.
* Moved counter and pwm bindings to respective subsystems
* Dropped 'bindings' from MFD binding title.
* Updated the example
* Changed the compatible names.
---
.../bindings/timer/renesas,rz-mtu3.yaml | 302 ++++++++++++++++++
1 file changed, 302 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
new file mode 100644
index 000000000000..bffdab0b0185
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -0,0 +1,302 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ This hardware block consists of eight 16-bit timer channels and one
+ 32- bit timer channel. It supports the following specifications:
+ - Pulse input/output: 28 lines max.
+ - Pulse input 3 lines
+ - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
+ for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
+ (when LWA = 1))
+ - Operating frequency Up to 100 MHz
+ - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
+ - Waveform output on compare match
+ - Input capture function (noise filter setting available)
+ - Counter-clearing operation
+ - Simultaneous writing to multiple timer counters (TCNT)
+ (excluding MTU8).
+ - Simultaneous clearing on compare match or input capture
+ (excluding MTU8).
+ - Simultaneous input and output to registers in synchronization with
+ counter operations (excluding MTU8).
+ - Up to 12-phase PWM output in combination with synchronous operation
+ (excluding MTU8)
+ - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
+ - Buffer operation specifiable
+ - [MTU1, MTU2]
+ - Phase counting mode can be specified independently
+ - 32-bit phase counting mode can be specified for interlocked operation
+ of MTU1 and MTU2 (when TMDR3.LWA = 1)
+ - Cascade connection operation available
+ - [MTU3, MTU4, MTU6, and MTU7]
+ - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
+ negative signals in six phases (12 phases in total) can be output in
+ complementary PWM and reset-synchronized PWM operation.
+ - In complementary PWM mode, values can be transferred from buffer
+ registers to temporary registers at crests and troughs of the timer-
+ counter values or when the buffer registers (TGRD registers in MTU4
+ and MTU7) are written to.
+ - Double-buffering selectable in complementary PWM mode.
+ - [MTU3 and MTU4]
+ - Through interlocking with MTU0, a mode for driving AC synchronous
+ motors (brushless DC motors) by using complementary PWM output and
+ reset-synchronized PWM output is settable and allows the selection
+ of two types of waveform output (chopping or level).
+ - [MTU5]
+ - Capable of operation as a dead-time compensation counter.
+ - [MTU0/MTU5, MTU1, MTU2, and MTU8]
+ - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
+ through interlocked operation with MTU0/MTU5 and MTU8.
+ - Interrupt-skipping function
+ - In complementary PWM mode, interrupts on crests and troughs of counter
+ values and triggers to start conversion by the A/D converter can be
+ skipped.
+ - Interrupt sources: 43 sources.
+ - Buffer operation:
+ - Automatic transfer of register data (transfer from the buffer
+ register to the timer register).
+ - Trigger generation
+ - A/D converter start triggers can be generated
+ - A/D converter start request delaying function enables A/D converter
+ to be started with any desired timing and to be synchronized with
+ PWM output.
+ - Low power consumption function
+ - The MTU3a can be placed in the module-stop state.
+
+ There are two phase counting modes. 16-bit phase counting mode in which
+ MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
+ counting mode in which MTU1 and MTU2 are cascaded.
+
+ In phase counting mode, the phase difference between two external input
+ clocks is detected and the corresponding TCNT is incremented or
+ decremented.
+ The below counters are supported
+ count0 - MTU1 16-bit phase counting
+ count1 - MTU2 16-bit phase counting
+ count2 - MTU1+ MTU2 32-bit phase counting
+
+ The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
+ complementary PWM mode{1,2,3}.
+
+ In complementary PWM mode, six positive-phase and six negative-phase PWM
+ waveforms (12 phases in total) with dead time can be output by
+ combining MTU{3,4} and MTU{6,7}.
+
+ The below pwm channels are supported in pwm mode 1.
+ pwm0 - MTU0.MTIOC0A PWM mode 1
+ pwm1 - MTU0.MTIOC0C PWM mode 1
+ pwm2 - MTU1.MTIOC1A PWM mode 1
+ pwm3 - MTU2.MTIOC2A PWM mode 1
+ pwm4 - MTU3.MTIOC3A PWM mode 1
+ pwm5 - MTU3.MTIOC3C PWM mode 1
+ pwm6 - MTU4.MTIOC4A PWM mode 1
+ pwm7 - MTU4.MTIOC4C PWM mode 1
+ pwm8 - MTU6.MTIOC6A PWM mode 1
+ pwm9 - MTU6.MTIOC6C PWM mode 1
+ pwm10 - MTU7.MTIOC7A PWM mode 1
+ pwm11 - MTU7.MTIOC7C PWM mode 1
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
+ - renesas,r9a07g054-mtu3 # RZ/V2L
+ - const: renesas,rz-mtu3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: MTU0.TGRA input capture/compare match
+ - description: MTU0.TGRB input capture/compare match
+ - description: MTU0.TGRC input capture/compare match
+ - description: MTU0.TGRD input capture/compare match
+ - description: MTU0.TCNT overflow
+ - description: MTU0.TGRE compare match
+ - description: MTU0.TGRF compare match
+ - description: MTU1.TGRA input capture/compare match
+ - description: MTU1.TGRB input capture/compare match
+ - description: MTU1.TCNT overflow
+ - description: MTU1.TCNT underflow
+ - description: MTU2.TGRA input capture/compare match
+ - description: MTU2.TGRB input capture/compare match
+ - description: MTU2.TCNT overflow
+ - description: MTU2.TCNT underflow
+ - description: MTU3.TGRA input capture/compare match
+ - description: MTU3.TGRB input capture/compare match
+ - description: MTU3.TGRC input capture/compare match
+ - description: MTU3.TGRD input capture/compare match
+ - description: MTU3.TCNT overflow
+ - description: MTU4.TGRA input capture/compare match
+ - description: MTU4.TGRB input capture/compare match
+ - description: MTU4.TGRC input capture/compare match
+ - description: MTU4.TGRD input capture/compare match
+ - description: MTU4.TCNT overflow/underflow
+ - description: MTU5.TGRU input capture/compare match
+ - description: MTU5.TGRV input capture/compare match
+ - description: MTU5.TGRW input capture/compare match
+ - description: MTU6.TGRA input capture/compare match
+ - description: MTU6.TGRB input capture/compare match
+ - description: MTU6.TGRC input capture/compare match
+ - description: MTU6.TGRD input capture/compare match
+ - description: MTU6.TCNT overflow
+ - description: MTU7.TGRA input capture/compare match
+ - description: MTU7.TGRB input capture/compare match
+ - description: MTU7.TGRC input capture/compare match
+ - description: MTU7.TGRD input capture/compare match
+ - description: MTU7.TCNT overflow/underflow
+ - description: MTU8.TGRA input capture/compare match
+ - description: MTU8.TGRB input capture/compare match
+ - description: MTU8.TGRC input capture/compare match
+ - description: MTU8.TGRD input capture/compare match
+ - description: MTU8.TCNT overflow
+ - description: MTU8.TCNT underflow
+
+ interrupt-names:
+ items:
+ - const: tgia0
+ - const: tgib0
+ - const: tgic0
+ - const: tgid0
+ - const: tgiv0
+ - const: tgie0
+ - const: tgif0
+ - const: tgia1
+ - const: tgib1
+ - const: tgiv1
+ - const: tgiu1
+ - const: tgia2
+ - const: tgib2
+ - const: tgiv2
+ - const: tgiu2
+ - const: tgia3
+ - const: tgib3
+ - const: tgic3
+ - const: tgid3
+ - const: tgiv3
+ - const: tgia4
+ - const: tgib4
+ - const: tgic4
+ - const: tgid4
+ - const: tgiv4
+ - const: tgiu5
+ - const: tgiv5
+ - const: tgiw5
+ - const: tgia6
+ - const: tgib6
+ - const: tgic6
+ - const: tgid6
+ - const: tgiv6
+ - const: tgia7
+ - const: tgib7
+ - const: tgic7
+ - const: tgid7
+ - const: tgiv7
+ - const: tgia8
+ - const: tgib8
+ - const: tgic8
+ - const: tgid8
+ - const: tgiv8
+ - const: tgiu8
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mtu3: timer@10001200 {
+ compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
+ reg = <0x10001200 0xb00>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
+ "tgif0",
+ "tgia1", "tgib1", "tgiv1", "tgiu1",
+ "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
+ "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
+ "tgiu5", "tgiv5", "tgiw5",
+ "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
+ "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
+ "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
+ clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+ #pwm-cells = <2>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver
2023-01-13 16:17 [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
2023-01-13 16:17 ` [PATCH v11 1/6] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
@ 2023-01-25 19:48 ` Biju Das
2023-01-26 10:44 ` Daniel Lezcano
1 sibling, 1 reply; 4+ messages in thread
From: Biju Das @ 2023-01-25 19:48 UTC (permalink / raw)
To: Biju Das, Rob Herring, Philipp Zabel, Daniel Lezcano,
William Breathitt Gray, Thierry Reding, Uwe Kleine-König,
Krzysztof Kozlowski
Cc: Thomas Gleixner, devicetree@vger.kernel.org, Geert Uytterhoeven,
Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc@vger.kernel.org
Hi Daniel,
Gentle ping.
The core driver and binding patches [1] and [2] is blocking[3], [4] and [5].
Does these patches have to go via counter tree as it is the first user and
we have dependency between subsystems for this IP?
[1] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#m79afdee83fd64dfbeb27fd888361a0d6d6a26ad5
[2] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#m4d0dfa4d2700c2d6669da3289d68bcb9ce7dac71
[3] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#mb8d4b7ad8e23e795bfde15a33c28b5c0348654bc
[4] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#me3bcc56cef9cf78868e38158f8b870fa9cceff8f
[5] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#m1821926505123cd75f0b981e496d4e044cf875c3
Cheers,
Biju
> Subject: [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver
>
> The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in the
> Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer channels and
> one 32-bit timer channel. It supports the following functions
> - Counter
> - Timer
> - PWM
>
> This patch series aims to add core, counter and pwm driver for MTU3a. The
> core instantiates child devices using mfd api.
>
> The 8/16/32 bit registers are mixed in each channel. The HW specifications
> of the IP is described in patch#1.
>
> Current patch set is tested for PWM mode1 on MTU3 channel and 16 and 32 bit
> phase counting modes on MTU1 and MTU2 channels.
>
> There is a plan to add clock event driver later for Power management.
>
> Ref:
>
https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221010145222.1047748-2-biju.das.jz@bp.renesas.com/
> v10->v11:
> * Added Rb tag from William Breathitt Gray for the driver patch
> * Replaced count2 channel name from "combined"->"cascaded", as channels
> are cascaded
> * Simplified the locking by adding the helper functions
> rz_mtu3_lock_if_counter_is_valid, rz_mtu3_lock_if_count_is_enabled,
> and rz_mtu3_lock_if_ch0_is_enabled.
> * Added the MAINTAINERS entries for the driver.
> v9->v10:
> * Added logs from PWM and counter
> * Added Rb tag from William Breathitt Gray for sysfs counter doc
> * Added helper function for rz_mtu3_count_{action,function}_read
> * Added priv->lock in rz_mtu3_count_function_read and rz_mtu3_count_
> direction_read.
> * Added ch->is_busy check for rz_mtu3_action_read()
> * Added rz_mtu3_is_ch0_enabled() for device specific sysfs variables.
> * Added ch->is_busy check for device specific sysfs variables.
> v8->v9:
> * Added prescale/duty_cycle variables to struct rz_mtu3_pwm_chip and
> cached this values in rz_mtu3_pwm_config and used this cached values
> in get_state(), if PWM is disabled.
> * Added return code for get_state().
> * Added available blocks for external_input_phase_clock_select_available
> * Removed the "This attribute" from the external_input_phase_clock_select
> description, and capitalize the word "counter" from description.
> * Removed the "This attribute" from the cascade_counts_enable description,
> and capitalize "counts" and "counter"
> * Moved these device-level configuration blocks to top of the file.
> * Added count_is_enabled variable to struct rz_mtu3_cnt
> * Added check for ch->is_busy and count_is_enabled before every Counter
> callback to ensure we do not try to access a busy channel used by other
> subsystem(eg: pwm).
> * Removed id parameter from rz_mtu3_32bit_cnt_setting()
> * Made definition of rz_mtu3_get_ch() in single line.
> * Replaced break->return in rz_mtu3_32bit_cnt_setting(),
> rz_mtu3_count_function_read() and rz_mtu3_initialize_counter()
> and removed redundant return 0.
> * Simplified synapse signal check for rz_mtu3_action_read().
> v7->v8:
> * Add locking for RMW on rz_mtu3_shared_reg_update_bit()
> * Replaced enum rz_mtu3_functions with channel busy flag
> * Added API for request and release a channel.
> * Replaced cascade_enable->cascade_counts_enable
> * Updated commit header and description
> * Added external_input_phase_clock_select_available entry for driver-
> specific enum attribute and created a new entry block for it.
> * Add a line stating cascade_counts_enable is a boolean attribute.
> * Added missing 'component_id' suffix.
> * Simplified rz_mtu3_initialize_counter by calling rz_mtu3_request_
> channel() and release the acquired sibling channel in case of error.
> * Simplified rz_mtu3_terminate_counter by calling rz_mtu3_release_
> channel().
> * Removed unused ceiling and ch_id from rz_mtu3_count_write()
> * Replaced the error -EINVAL->-EBUSY for rz_mtu3_is_counter_invalid()
> * Avoided race between rz_mtu3_count_{read, write} with rz_mtu3_
> cascade_counts_enable_set() by adding locks and moved the lock
> before rz_mtu3_is_counter_invalid()
> * Protected the rz_mtu3_count_ceiling_read() function with a lock
> to make sure the cascade operation mode doesn't not change and
> that the priv data structure accesses don't race when they are
> changed in the ceiling_write() callback.
> * Added lock in rz_mtu3_cascade_enable_set() to make sure the other
> callbacks don't try to read the LWA state while updating LWA.
> * Added lock in rz_mtu3_ext_input_phase_clock_select_set() to ensure
> the other callbacks don't try to read the PHCKSEL state while updating
> PHCKSEL.
> * Added lock to avoid race between rz_mtu3_count_function_write() and
> rz_mtu3_action_read()
> * Updated rz_mtu3_action_read to return 0, if Synapse is in COUNTER_SYNAPSE
> _ACTION_NONE state.
> * Replaced sysfs variable cascade_enable->cascade_counts_enable
> * Renamed rz_mtu3_cascade_enable_get->rz_mtu3_cascade_counts_enable_get
> * Renamed rz_mtu3_cascade_enable_set->rz_mtu3_cascade_counts_enable_set
> * Removed redundent ceiling assignment from rz_mtu3_count_ceiling_read()
> * Removed unused ceiling and ch_id from rz_mtu3_count_write().
> * Simplified rz_mtu3_pwm_request by calling rz_mtu3_request_channel()
> * Simplified rz_mtu3_pwm_free by calling rz_mtu3_release_channel()
> v6->v7:
> * Added channel specific mutex to avoid races between child devices
> (for eg: pwm and counter).
> * Added rz_mtu3_shared_reg_update_bit() to update bits.
> * Replaced sysfs variable "long_word_access_ctrl_mode->cascade_enable"
> * Updated Kernel version in sysfs Documentation
> * Updated commit description for counter driver
> * Added Register descriptions
> * Opimized size of cache variable by using union
> * Used test_bit() in rz_mtu3_is_counter_invalid()
> * Replaced val->timer_mode in rz_mtu3_count_function_{read,write}
> * Added TODO comment phase3 and phase5 modes.
> * replaced if-else with ternary expression in
> rz_mtu3_count_direction_read()
> * Used switch statement in rz_mtu3_count_ceiling_read to consistent with
> write
> * Provided default case for all switch statements.
> * Add mutex lock for avoiding races with other devices and counter
> * Updated comments in rz_mtu3_action_read()
> * Replaced COUNTER_COMP_DEVICE_BOOL->COUNTER_COMP_DEVICE_BOOL for
> cascade_enable
> * Replaced RZ_MTU3_GET_HW_CH->rz_mtu3_get_hw_ch
> * Added rz_mtu3_get_ch() to get channels
> * used rz_mtu3_shared_reg_update_bit for cascade_enable and
> selecting phase input clock.
> * Added rz_mtu3_is_counter_invalid() check in rz_mtu3_count_ceiling_read()
> * Added channel specific mutex lock to avoid race between counter
> device and rz_mtu3_pwm_{request,free}
> * Added pm_runtime_resume_and_get in rz_mtu3_pwm_enable()
> * Added pm_runtime_put_sync in rz_mtu3_pwm_disable()
> * Updated rz_mtu3_pwm_config()
> * Updated rz_mtu3_pwm_apply()
> v5->v6:
> * Added Rb tag from Rob and Krzysztof for the binding patch.
> * Updated commit and KConfig description for the driver patches
> * Selected MFD_CORE to avoid build error if CONFIG_MFD_CORE not set.
> * Improved error handling in core driver's probe().
> * Fixed RZ_MTU3_GET_HW_CH Macro for argument reuse 'id' -
> possible side-effects?
> * Replaced SET_RUNTIME_PM_OPS->DEFINE_RUNTIME_DEV_PM_OPS and removed
> __maybe_unused from suspend/resume()
> * Replaced dev_get_drvdata from rz_mtu3_pwm_pm_disable()
> * Sorted header files for all driver files.
> v4->v5:
> * Modelled as timer bindings.
> * Fixed the typo in bindings.
> * Moved core driver from MFD to timer
> * Child devices instatiated using mfd_add_devices()
> * Documented sysfs entries external_input_phase_clock_select and
> long_word_access_ctrl_mode.
> * Updated the Kconfig with SoC vendor name
> * Introduced rz_mtu3_is_counter_invalid()
> * replaced pointer to an array of struct rz_mtu3_channel with
> a simple pointer to struct rz_mtu3_channel.
> * Added long_word_access_ctrl_mode sysfs entry for 16-bit and
> 32-bit access
> * Added external_input_phase_clock_select sysfs entry for
> selecting input clocks.
> * used preprocessor defines represent SIGNAL_{A,B,C,D}_ID instead of
> signal ids.
> v3->v4:
> * Dropped counter and pwm compatibeles as they don't have any resources.
> * Made rz-mtu3 as pwm provider.
> * Updated the example and description.
> * A single driver that registers both the counter and the pwm
> functionalities
> that binds against "renesas,rz-mtu3".
> * Moved PM handling from child devices to here.
> * replaced include/linux/mfd/rz-mtu3.h->drivers/mfd/rz-mtu3.h
> * Removed "remove" callback from mfd driver
> * There is no resource associated with "rz-mtu3-counter" and "rz-mtu3-pwm"
> compatible and moved the code to mfd subsystem as it binds against "rz-
> mtu".
> * Removed struct platform_driver rz_mtu3_cnt_driver.
> * Removed struct platform_driver rz_mtu3_pwm_driver.
> * Updated commit description
> * Updated Kconfig description
> * Added macros RZ_MTU3_16_BIT_MTU{1,2}_CH for MTU1 and MTU2 channels
> * Added RZ_MTU3_GET_HW_CH macro for getting channel ID.
> * replaced priv->ch[id]->priv->ch[0] in rz_mtu3_count_read()
> * Cached counter max values
> * replaced cnt->tsr in rz_mtu3_count_direction_read()
> * Added comments for RZ_MTU3_TCR_CCLR_NONE
> * Replaced if with switch in rz_mtu3_initialize_counter() and
> rz_mtu3_count_ceiling_write()
> * Added locks in initialize, terminate and enable_read to prevent races.
> * Updated rz_mtu3_action_read to take care of MTU2 signals.
> * Added separate distinct array for each group of Synapse.
> * Moved pm handling to parent.
> v2->v3:
> * Dropped counter bindings and integrated with mfd as it has only one
> property.
> * Removed "#address-cells" and "#size-cells" as it do not have children
> with
> unit addresses.
> * Removed quotes from counter and pwm.
> * Provided full path for pwm bindings.
> * Updated the binding example.
> * removed unwanted header files
> * Added LUT for 32 bit registers as it needed for 32-bit cascade counting.
> * Exported 32 bit read/write functions.
> * Modelled as a counter device supporting 3 counters(2 16-bit and
> 32-bit)
> * Add kernel-doc comments to document struct rz_mtu3_cnt
> * Removed mmio variable from struct rz_mtu3_cnt
> * Removed cnt local variable from rz_mtu3_count_read()
> * Replaced -EINVAL->-ERANGE for out of range error conditions.
> * Removed explicit cast from write functions.
> * Removed local variable val from rz_mtu3_count_ceiling_read()
> * Added lock for RMW for counter/ceiling updates.
> * Added different synapses for counter0 and counter{1,2}
> * Used ARRAY for assigning num_counts.
> * Added PM runtime for managing clocks.
> * Add MODULE_IMPORT_NS(COUNTER) to import the COUNTER namespace.
>
> RFC->v2:
> * replaced devm_reset_control_get->devm_reset_control_get_exclusive
> * Dropped 'bindings' from the binding title
> * Updated the binding example
> * Added additionalProperties: false for counter bindings
> * Squashed all the binding patches
> * Modelled as a single counter device providing both 16-bit
> and 32-bit phase counting modes
> * Modelled as a single pwm device for supporting different pwm modes.
> * Moved counter and pwm bindings to respective subsystems.
>
> Logs:
> root@smarc-rzg2l:/# /mtu_test.sh
> #### Zero duty cycle ###
> #### decrement Period ###
> #### Increment Period ###
> #### decrement duty cycle ###
> #### Increment duty cycle ###
> ### Unbind the PWM driver####
> ### Bind the PWM driver####
> Positive counting
> cascade_counts_enable is 0
> #### Ch0 count
> 0
> 2
> 8
> 13
> 18
> 23
> 28
> 33
> 38
> 44
> 50
> 3
> 9
> 14
> 19
> 24
> 29
> 35
> 39
> 45
> #### Ch1 count
> #### Select Phase clock
> Phase clock MTCLKA-MTCLKB
> 0
> 5
> 10
> 15
> 20
> 4
> 10
> 14
> 20
> 3
> 9
> 14
> 19
> 3
> 8
> 14
> 18
> 3
> 7
> 13
> #### Select Phase clock
> Phase clock MTCLKA-MTCLKB
> cascade_counts_enable is 1
> #### Ch2 count
> 0
> 5
> 10
> 15
> 21
> 25
> 31
> 36
> 41
> 46
> 51
> 56
> 61
> 67
> 71
> 77
> 82
> 87
> 92
> 97
> ### Unbind the counter driver####
> ### Bind the counter driver####
> ### Unbind the Core driver####
> ### Bind the Core driver####
> Read at address 0x11010538 (0xffffb1aaa538): 0x00000000 root@smarc-rzg2l:/#
>
> Biju Das (6):
> dt-bindings: timer: Document RZ/G2L MTU3a bindings
> clocksource/drivers: Add Renesas RZ/G2L MTU3a core driver
> Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and
> external_input_phase_clock_select
> counter: Add Renesas RZ/G2L MTU3a counter driver
> MAINTAINERS: Add entries for Renesas RZ/G2L MTU3a counter driver
> pwm: Add Renesas RZ/G2L MTU3a PWM driver
>
> Documentation/ABI/testing/sysfs-bus-counter | 32 +
> .../bindings/timer/renesas,rz-mtu3.yaml | 302 ++++++
> MAINTAINERS | 8 +
> drivers/clocksource/Kconfig | 11 +
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/rz-mtu3.c | 459 +++++++++
> drivers/counter/Kconfig | 11 +
> drivers/counter/Makefile | 1 +
> drivers/counter/rz-mtu3-cnt.c | 903 ++++++++++++++++++
> drivers/pwm/Kconfig | 11 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-rz-mtu3.c | 486 ++++++++++
> include/clocksource/rz-mtu3.h | 237 +++++
> 13 files changed, 2463 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/renesas,rz-
> mtu3.yaml
> create mode 100644 drivers/clocksource/rz-mtu3.c create mode 100644
> drivers/counter/rz-mtu3-cnt.c create mode 100644 drivers/pwm/pwm-rz-mtu3.c
> create mode 100644 include/clocksource/rz-mtu3.h
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver
2023-01-25 19:48 ` [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
@ 2023-01-26 10:44 ` Daniel Lezcano
0 siblings, 0 replies; 4+ messages in thread
From: Daniel Lezcano @ 2023-01-26 10:44 UTC (permalink / raw)
To: Biju Das, Rob Herring, Philipp Zabel, William Breathitt Gray,
Thierry Reding, Uwe Kleine-König, Krzysztof Kozlowski
Cc: Thomas Gleixner, devicetree@vger.kernel.org, Geert Uytterhoeven,
Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc@vger.kernel.org
On 25/01/2023 20:48, Biju Das wrote:
> Hi Daniel,
>
> Gentle ping.
Yeah, sorry for the delay.
> The core driver and binding patches [1] and [2] is blocking[3], [4] and [5].
>
> Does these patches have to go via counter tree as it is the first user and
> we have dependency between subsystems for this IP?
I am reviewing the patch for now.
The simplest way is I create an immutable branch based on v6.2-rc1 with
these two patches and then I merge it back to the timers/next branch.
From your side, you merge this immutable branch.
I'll take care of it ASAP, so you won't be blocked anymore.
> [1] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#m79afdee83fd64dfbeb27fd888361a0d6d6a26ad5
>
> [2] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#m4d0dfa4d2700c2d6669da3289d68bcb9ce7dac71
>
> [3] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#mb8d4b7ad8e23e795bfde15a33c28b5c0348654bc
>
> [4] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#me3bcc56cef9cf78868e38158f8b870fa9cceff8f
>
> [5] https://lore.kernel.org/linux-renesas-soc/20230113161753.1073706-1-biju.das.jz@bp.renesas.com/T/#m1821926505123cd75f0b981e496d4e044cf875c3
>
> Cheers,
> Biju
>
>> Subject: [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver
>>
>> The RZ/G2L multi-function timer pulse unit 3 (MTU3a) is embedded in the
>> Renesas RZ/G2L family SoC's. It consists of eight 16-bit timer channels and
>> one 32-bit timer channel. It supports the following functions
>> - Counter
>> - Timer
>> - PWM
>>
>> This patch series aims to add core, counter and pwm driver for MTU3a. The
>> core instantiates child devices using mfd api.
>>
>> The 8/16/32 bit registers are mixed in each channel. The HW specifications
>> of the IP is described in patch#1.
>>
>> Current patch set is tested for PWM mode1 on MTU3 channel and 16 and 32 bit
>> phase counting modes on MTU1 and MTU2 channels.
>>
>> There is a plan to add clock event driver later for Power management.
>>
>> Ref:
>>
> https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221010145222.1047748-2-biju.das.jz@bp.renesas.com/
>
>> v10->v11:
>> * Added Rb tag from William Breathitt Gray for the driver patch
>> * Replaced count2 channel name from "combined"->"cascaded", as channels
>> are cascaded
>> * Simplified the locking by adding the helper functions
>> rz_mtu3_lock_if_counter_is_valid, rz_mtu3_lock_if_count_is_enabled,
>> and rz_mtu3_lock_if_ch0_is_enabled.
>> * Added the MAINTAINERS entries for the driver.
>> v9->v10:
>> * Added logs from PWM and counter
>> * Added Rb tag from William Breathitt Gray for sysfs counter doc
>> * Added helper function for rz_mtu3_count_{action,function}_read
>> * Added priv->lock in rz_mtu3_count_function_read and rz_mtu3_count_
>> direction_read.
>> * Added ch->is_busy check for rz_mtu3_action_read()
>> * Added rz_mtu3_is_ch0_enabled() for device specific sysfs variables.
>> * Added ch->is_busy check for device specific sysfs variables.
>> v8->v9:
>> * Added prescale/duty_cycle variables to struct rz_mtu3_pwm_chip and
>> cached this values in rz_mtu3_pwm_config and used this cached values
>> in get_state(), if PWM is disabled.
>> * Added return code for get_state().
>> * Added available blocks for external_input_phase_clock_select_available
>> * Removed the "This attribute" from the external_input_phase_clock_select
>> description, and capitalize the word "counter" from description.
>> * Removed the "This attribute" from the cascade_counts_enable description,
>> and capitalize "counts" and "counter"
>> * Moved these device-level configuration blocks to top of the file.
>> * Added count_is_enabled variable to struct rz_mtu3_cnt
>> * Added check for ch->is_busy and count_is_enabled before every Counter
>> callback to ensure we do not try to access a busy channel used by other
>> subsystem(eg: pwm).
>> * Removed id parameter from rz_mtu3_32bit_cnt_setting()
>> * Made definition of rz_mtu3_get_ch() in single line.
>> * Replaced break->return in rz_mtu3_32bit_cnt_setting(),
>> rz_mtu3_count_function_read() and rz_mtu3_initialize_counter()
>> and removed redundant return 0.
>> * Simplified synapse signal check for rz_mtu3_action_read().
>> v7->v8:
>> * Add locking for RMW on rz_mtu3_shared_reg_update_bit()
>> * Replaced enum rz_mtu3_functions with channel busy flag
>> * Added API for request and release a channel.
>> * Replaced cascade_enable->cascade_counts_enable
>> * Updated commit header and description
>> * Added external_input_phase_clock_select_available entry for driver-
>> specific enum attribute and created a new entry block for it.
>> * Add a line stating cascade_counts_enable is a boolean attribute.
>> * Added missing 'component_id' suffix.
>> * Simplified rz_mtu3_initialize_counter by calling rz_mtu3_request_
>> channel() and release the acquired sibling channel in case of error.
>> * Simplified rz_mtu3_terminate_counter by calling rz_mtu3_release_
>> channel().
>> * Removed unused ceiling and ch_id from rz_mtu3_count_write()
>> * Replaced the error -EINVAL->-EBUSY for rz_mtu3_is_counter_invalid()
>> * Avoided race between rz_mtu3_count_{read, write} with rz_mtu3_
>> cascade_counts_enable_set() by adding locks and moved the lock
>> before rz_mtu3_is_counter_invalid()
>> * Protected the rz_mtu3_count_ceiling_read() function with a lock
>> to make sure the cascade operation mode doesn't not change and
>> that the priv data structure accesses don't race when they are
>> changed in the ceiling_write() callback.
>> * Added lock in rz_mtu3_cascade_enable_set() to make sure the other
>> callbacks don't try to read the LWA state while updating LWA.
>> * Added lock in rz_mtu3_ext_input_phase_clock_select_set() to ensure
>> the other callbacks don't try to read the PHCKSEL state while updating
>> PHCKSEL.
>> * Added lock to avoid race between rz_mtu3_count_function_write() and
>> rz_mtu3_action_read()
>> * Updated rz_mtu3_action_read to return 0, if Synapse is in COUNTER_SYNAPSE
>> _ACTION_NONE state.
>> * Replaced sysfs variable cascade_enable->cascade_counts_enable
>> * Renamed rz_mtu3_cascade_enable_get->rz_mtu3_cascade_counts_enable_get
>> * Renamed rz_mtu3_cascade_enable_set->rz_mtu3_cascade_counts_enable_set
>> * Removed redundent ceiling assignment from rz_mtu3_count_ceiling_read()
>> * Removed unused ceiling and ch_id from rz_mtu3_count_write().
>> * Simplified rz_mtu3_pwm_request by calling rz_mtu3_request_channel()
>> * Simplified rz_mtu3_pwm_free by calling rz_mtu3_release_channel()
>> v6->v7:
>> * Added channel specific mutex to avoid races between child devices
>> (for eg: pwm and counter).
>> * Added rz_mtu3_shared_reg_update_bit() to update bits.
>> * Replaced sysfs variable "long_word_access_ctrl_mode->cascade_enable"
>> * Updated Kernel version in sysfs Documentation
>> * Updated commit description for counter driver
>> * Added Register descriptions
>> * Opimized size of cache variable by using union
>> * Used test_bit() in rz_mtu3_is_counter_invalid()
>> * Replaced val->timer_mode in rz_mtu3_count_function_{read,write}
>> * Added TODO comment phase3 and phase5 modes.
>> * replaced if-else with ternary expression in
>> rz_mtu3_count_direction_read()
>> * Used switch statement in rz_mtu3_count_ceiling_read to consistent with
>> write
>> * Provided default case for all switch statements.
>> * Add mutex lock for avoiding races with other devices and counter
>> * Updated comments in rz_mtu3_action_read()
>> * Replaced COUNTER_COMP_DEVICE_BOOL->COUNTER_COMP_DEVICE_BOOL for
>> cascade_enable
>> * Replaced RZ_MTU3_GET_HW_CH->rz_mtu3_get_hw_ch
>> * Added rz_mtu3_get_ch() to get channels
>> * used rz_mtu3_shared_reg_update_bit for cascade_enable and
>> selecting phase input clock.
>> * Added rz_mtu3_is_counter_invalid() check in rz_mtu3_count_ceiling_read()
>> * Added channel specific mutex lock to avoid race between counter
>> device and rz_mtu3_pwm_{request,free}
>> * Added pm_runtime_resume_and_get in rz_mtu3_pwm_enable()
>> * Added pm_runtime_put_sync in rz_mtu3_pwm_disable()
>> * Updated rz_mtu3_pwm_config()
>> * Updated rz_mtu3_pwm_apply()
>> v5->v6:
>> * Added Rb tag from Rob and Krzysztof for the binding patch.
>> * Updated commit and KConfig description for the driver patches
>> * Selected MFD_CORE to avoid build error if CONFIG_MFD_CORE not set.
>> * Improved error handling in core driver's probe().
>> * Fixed RZ_MTU3_GET_HW_CH Macro for argument reuse 'id' -
>> possible side-effects?
>> * Replaced SET_RUNTIME_PM_OPS->DEFINE_RUNTIME_DEV_PM_OPS and removed
>> __maybe_unused from suspend/resume()
>> * Replaced dev_get_drvdata from rz_mtu3_pwm_pm_disable()
>> * Sorted header files for all driver files.
>> v4->v5:
>> * Modelled as timer bindings.
>> * Fixed the typo in bindings.
>> * Moved core driver from MFD to timer
>> * Child devices instatiated using mfd_add_devices()
>> * Documented sysfs entries external_input_phase_clock_select and
>> long_word_access_ctrl_mode.
>> * Updated the Kconfig with SoC vendor name
>> * Introduced rz_mtu3_is_counter_invalid()
>> * replaced pointer to an array of struct rz_mtu3_channel with
>> a simple pointer to struct rz_mtu3_channel.
>> * Added long_word_access_ctrl_mode sysfs entry for 16-bit and
>> 32-bit access
>> * Added external_input_phase_clock_select sysfs entry for
>> selecting input clocks.
>> * used preprocessor defines represent SIGNAL_{A,B,C,D}_ID instead of
>> signal ids.
>> v3->v4:
>> * Dropped counter and pwm compatibeles as they don't have any resources.
>> * Made rz-mtu3 as pwm provider.
>> * Updated the example and description.
>> * A single driver that registers both the counter and the pwm
>> functionalities
>> that binds against "renesas,rz-mtu3".
>> * Moved PM handling from child devices to here.
>> * replaced include/linux/mfd/rz-mtu3.h->drivers/mfd/rz-mtu3.h
>> * Removed "remove" callback from mfd driver
>> * There is no resource associated with "rz-mtu3-counter" and "rz-mtu3-pwm"
>> compatible and moved the code to mfd subsystem as it binds against "rz-
>> mtu".
>> * Removed struct platform_driver rz_mtu3_cnt_driver.
>> * Removed struct platform_driver rz_mtu3_pwm_driver.
>> * Updated commit description
>> * Updated Kconfig description
>> * Added macros RZ_MTU3_16_BIT_MTU{1,2}_CH for MTU1 and MTU2 channels
>> * Added RZ_MTU3_GET_HW_CH macro for getting channel ID.
>> * replaced priv->ch[id]->priv->ch[0] in rz_mtu3_count_read()
>> * Cached counter max values
>> * replaced cnt->tsr in rz_mtu3_count_direction_read()
>> * Added comments for RZ_MTU3_TCR_CCLR_NONE
>> * Replaced if with switch in rz_mtu3_initialize_counter() and
>> rz_mtu3_count_ceiling_write()
>> * Added locks in initialize, terminate and enable_read to prevent races.
>> * Updated rz_mtu3_action_read to take care of MTU2 signals.
>> * Added separate distinct array for each group of Synapse.
>> * Moved pm handling to parent.
>> v2->v3:
>> * Dropped counter bindings and integrated with mfd as it has only one
>> property.
>> * Removed "#address-cells" and "#size-cells" as it do not have children
>> with
>> unit addresses.
>> * Removed quotes from counter and pwm.
>> * Provided full path for pwm bindings.
>> * Updated the binding example.
>> * removed unwanted header files
>> * Added LUT for 32 bit registers as it needed for 32-bit cascade counting.
>> * Exported 32 bit read/write functions.
>> * Modelled as a counter device supporting 3 counters(2 16-bit and
>> 32-bit)
>> * Add kernel-doc comments to document struct rz_mtu3_cnt
>> * Removed mmio variable from struct rz_mtu3_cnt
>> * Removed cnt local variable from rz_mtu3_count_read()
>> * Replaced -EINVAL->-ERANGE for out of range error conditions.
>> * Removed explicit cast from write functions.
>> * Removed local variable val from rz_mtu3_count_ceiling_read()
>> * Added lock for RMW for counter/ceiling updates.
>> * Added different synapses for counter0 and counter{1,2}
>> * Used ARRAY for assigning num_counts.
>> * Added PM runtime for managing clocks.
>> * Add MODULE_IMPORT_NS(COUNTER) to import the COUNTER namespace.
>>
>> RFC->v2:
>> * replaced devm_reset_control_get->devm_reset_control_get_exclusive
>> * Dropped 'bindings' from the binding title
>> * Updated the binding example
>> * Added additionalProperties: false for counter bindings
>> * Squashed all the binding patches
>> * Modelled as a single counter device providing both 16-bit
>> and 32-bit phase counting modes
>> * Modelled as a single pwm device for supporting different pwm modes.
>> * Moved counter and pwm bindings to respective subsystems.
>>
>> Logs:
>> root@smarc-rzg2l:/# /mtu_test.sh
>> #### Zero duty cycle ###
>> #### decrement Period ###
>> #### Increment Period ###
>> #### decrement duty cycle ###
>> #### Increment duty cycle ###
>> ### Unbind the PWM driver####
>> ### Bind the PWM driver####
>> Positive counting
>> cascade_counts_enable is 0
>> #### Ch0 count
>> 0
>> 2
>> 8
>> 13
>> 18
>> 23
>> 28
>> 33
>> 38
>> 44
>> 50
>> 3
>> 9
>> 14
>> 19
>> 24
>> 29
>> 35
>> 39
>> 45
>> #### Ch1 count
>> #### Select Phase clock
>> Phase clock MTCLKA-MTCLKB
>> 0
>> 5
>> 10
>> 15
>> 20
>> 4
>> 10
>> 14
>> 20
>> 3
>> 9
>> 14
>> 19
>> 3
>> 8
>> 14
>> 18
>> 3
>> 7
>> 13
>> #### Select Phase clock
>> Phase clock MTCLKA-MTCLKB
>> cascade_counts_enable is 1
>> #### Ch2 count
>> 0
>> 5
>> 10
>> 15
>> 21
>> 25
>> 31
>> 36
>> 41
>> 46
>> 51
>> 56
>> 61
>> 67
>> 71
>> 77
>> 82
>> 87
>> 92
>> 97
>> ### Unbind the counter driver####
>> ### Bind the counter driver####
>> ### Unbind the Core driver####
>> ### Bind the Core driver####
>> Read at address 0x11010538 (0xffffb1aaa538): 0x00000000 root@smarc-rzg2l:/#
>>
>> Biju Das (6):
>> dt-bindings: timer: Document RZ/G2L MTU3a bindings
>> clocksource/drivers: Add Renesas RZ/G2L MTU3a core driver
>> Documentation: ABI: sysfs-bus-counter: add cascade_counts_enable and
>> external_input_phase_clock_select
>> counter: Add Renesas RZ/G2L MTU3a counter driver
>> MAINTAINERS: Add entries for Renesas RZ/G2L MTU3a counter driver
>> pwm: Add Renesas RZ/G2L MTU3a PWM driver
>>
>> Documentation/ABI/testing/sysfs-bus-counter | 32 +
>> .../bindings/timer/renesas,rz-mtu3.yaml | 302 ++++++
>> MAINTAINERS | 8 +
>> drivers/clocksource/Kconfig | 11 +
>> drivers/clocksource/Makefile | 1 +
>> drivers/clocksource/rz-mtu3.c | 459 +++++++++
>> drivers/counter/Kconfig | 11 +
>> drivers/counter/Makefile | 1 +
>> drivers/counter/rz-mtu3-cnt.c | 903 ++++++++++++++++++
>> drivers/pwm/Kconfig | 11 +
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-rz-mtu3.c | 486 ++++++++++
>> include/clocksource/rz-mtu3.h | 237 +++++
>> 13 files changed, 2463 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/renesas,rz-
>> mtu3.yaml
>> create mode 100644 drivers/clocksource/rz-mtu3.c create mode 100644
>> drivers/counter/rz-mtu3-cnt.c create mode 100644 drivers/pwm/pwm-rz-mtu3.c
>> create mode 100644 include/clocksource/rz-mtu3.h
>>
>> --
>> 2.25.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-01-26 10:44 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-01-13 16:17 [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
2023-01-13 16:17 ` [PATCH v11 1/6] dt-bindings: timer: Document RZ/G2L MTU3a bindings Biju Das
2023-01-25 19:48 ` [PATCH v11 0/6] Add RZ/G2L MTU3a Core, Counter and pwm driver Biju Das
2023-01-26 10:44 ` Daniel Lezcano
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