From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEF9AC4332F for ; Fri, 23 Dec 2022 03:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235805AbiLWDLj (ORCPT ); Thu, 22 Dec 2022 22:11:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235912AbiLWDLi (ORCPT ); Thu, 22 Dec 2022 22:11:38 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1C4111A08; Thu, 22 Dec 2022 19:11:34 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 60A3C24E023; Fri, 23 Dec 2022 11:11:32 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 23 Dec 2022 11:11:32 +0800 Received: from [192.168.125.65] (183.27.97.120) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 23 Dec 2022 11:11:31 +0800 Message-ID: <94c90f3f-0ca7-7cfb-4d4f-8f90e3300e16@starfivetech.com> Date: Fri, 23 Dec 2022 11:12:34 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Content-Language: en-US To: Conor Dooley CC: , , "Palmer Dabbelt" , Rob Herring , "Krzysztof Kozlowski" , Paul Walmsley , Albert Ou , Ben Dooks , Daniel Lezcano , "Thomas Gleixner" , Marc Zyngier , Stephen Boyd , Michael Turquette , "Philipp Zabel" , Linus Walleij , Emil Renner Berthing , References: <20221220011247.35560-1-hal.feng@starfivetech.com> <20221220011247.35560-8-hal.feng@starfivetech.com> From: Hal Feng In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [183.27.97.120] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 20 Dec 2022 21:26:07 +0000, Conor Dooley wrote: > On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote: > > From: Emil Renner Berthing > > > > Add a minimal device tree for StarFive JH7110 VisionFive 2 board > > which has version A and version B. Support booting and basic > > clock/reset/pinctrl/uart drivers. > > > > Signed-off-by: Emil Renner Berthing > > Co-developed-by: Jianlong Huang > > Signed-off-by: Jianlong Huang > > Co-developed-by: Hal Feng > > Signed-off-by: Hal Feng > > --- > > arch/riscv/boot/dts/starfive/Makefile | 1 + > > .../jh7110-starfive-visionfive-2-va.dts | 13 ++ > > .../jh7110-starfive-visionfive-2-vb.dts | 13 ++ > > .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++ > > 4 files changed, 138 insertions(+) > > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts > > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts > > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > > index 0ea1bc15ab30..79e925a4a227 100644 > > --- a/arch/riscv/boot/dts/starfive/Makefile > > +++ b/arch/riscv/boot/dts/starfive/Makefile > > @@ -1,2 +1,3 @@ > > # SPDX-License-Identifier: GPL-2.0 > > dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb > > +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb > > Could you rebase on top of v6.2-rc1 when you submit your next version Sure. > squash this in please (unless Emil hates it): > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > index c38a9ade7f48..b3744420253a 100644 > --- a/arch/riscv/boot/dts/starfive/Makefile > +++ b/arch/riscv/boot/dts/starfive/Makefile > @@ -1,3 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb > -dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb > +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb > +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb > +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-vb.dtb > > I'd rather have more, but easier to read lines than long ones. I'm fine with this change. If no objection, I will modify it. Best regards, Hal > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > new file mode 100644 > > index 000000000000..c60280b89c73 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > @@ -0,0 +1,111 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (C) 2022 StarFive Technology Co., Ltd. > > + * Copyright (C) 2022 Emil Renner Berthing > > + */ > > + > > +/dts-v1/; > > +#include "jh7110.dtsi" > > +#include "jh7110-pinfunc.h" > > +#include > > + > > +/ { > > + aliases { > > + serial0 = &uart0; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + cpus { > > + timebase-frequency = <4000000>; > > + }; > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0x0 0x40000000 0x1 0x0>; > > Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR? The VisionFive 2 board only has 4GB version and 8GB version now. Before linux startup, we will change this property in dtb through u-boot to make sure the board can boot up with the correct memory size. Best regards, Hal > > Anyways, I can't review this as I've got neither board nor > documentation, so with the above stuff sorted out: > Acked-by: Conor Dooley > I'll not apply it until the clock binding header is in my tree.