From mboxrd@z Thu Jan 1 00:00:00 1970 From: icenowy-h8G6r0blFSE@public.gmane.org Subject: Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 Date: Wed, 23 Aug 2017 23:13:04 +0800 Message-ID: <9554c7524c8608e1eceafe762a487c11@aosc.io> References: <20170822061742.40869-1-icenowy@aosc.io> <20170822200521.nadkb4335mcc5ah2@flea.home> <20170823143532.owocqyq3tehsahhg@flea.home> Reply-To: icenowy-h8G6r0blFSE@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20170823143532.owocqyq3tehsahhg-YififvaboMKzQB+pC5nmwQ@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: Chen-Yu Tsai , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org =E5=9C=A8 2017-08-23 22:35=EF=BC=8CMaxime Ripard =E5=86=99=E9=81=93=EF=BC= =9A > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icenowy-h8G6r0blFSE@public.gmane.org wrote: >> > > + reg =3D <0x01c0f000 0x1000>; >> > > + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; >> > > + clock-names =3D "ahb", "mmc"; >> > > + resets =3D <&ccu RST_BUS_MMC0>; >> > > + reset-names =3D "ahb"; >> > > + pinctrl-0 =3D <&mmc0_pins>; >> > > + pinctrl-names =3D "default"; >> > > + interrupts =3D ; >> > > + max-frequency =3D <150000000>; >> > >> > have you tested that frequency? >>=20 >> I think the frequency should be kept here, although my cards cannot >> reach this frequency. >>=20 >> The numbers are same as the corresponding controllers in A64. >>=20 >> Maybe I should add a comment saying it's educated guess? >=20 > I'd rather have it tested by someone, and then add the proper > frequencies. It took quite a while to figure out how these modes were > supposed to be working on the A64, so it's not obvious that they're > just going to work. Should I add my results here? MMC0: 25MHz MMC1: 50MHz MMC2: 52MHz MMC3: not wired :-( I think it's conservative enough and works well ;-) >=20 >> > > + gic: interrupt-controller@1c81000 { >> > > + compatible =3D "arm,gic-400"; >> > > + reg =3D <0x01c81000 0x1000>, >> > > + <0x01c82000 0x1000>, >> > > + <0x01c84000 0x2000>, >> > > + <0x01c86000 0x2000>; >> > > + interrupt-controller; >> > > + #interrupt-cells =3D <3>; >> > > + interrupts =3D > > > IRQ_TYPE_LEVEL_HIGH)>; >> > > + }; >> > > + }; >> > > + >> > > + timer { >> > > + compatible =3D "arm,armv7-timer"; >> > > + interrupts =3D > > > IRQ_TYPE_LEVEL_LOW)>, >> > > + , >> > > + , >> > > + ; >> > >> > Those masks are wrong. >>=20 >> I compared it with other sun8i SoCs' device tree. >>=20 >> Where's wrong? >=20 > It's supposed to be a mask of the CPUs in your system. Since you just > have one of them, it shouldn't be 4. R40 has 4 cores... Or I didn't understand this? >=20 > Maxime --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout.