From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E035DEE57E1 for ; Fri, 8 Sep 2023 08:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238537AbjIHINq (ORCPT ); Fri, 8 Sep 2023 04:13:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233303AbjIHINp (ORCPT ); Fri, 8 Sep 2023 04:13:45 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4F2A1BDD for ; Fri, 8 Sep 2023 01:13:40 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-9a64619d8fbso221542166b.0 for ; Fri, 08 Sep 2023 01:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694160819; x=1694765619; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=RWZM8Q/uIy8my/IXpdHmpbEduZUYWK8mH9X8KWk+rE4=; b=IXQ+dqqFkd/ASkI/zwtTA6zuPxiuprT7OFtt7KR0IrEnpqKMOUKuuEQ2CXNyjjKlbp i2sUakTjkTnJnFAJ1XHuNESG7ko191imx/iqeZAPlfAWNW+NYtkGE/XKMDYRdpRFFpZP YjYsDwu7ij73CGKz6NcDxDTzSMSYL4PiBtqMfaVw6q/h/Z3EjXPDUGxOGgq87bWHWi/L 27bhJv7QH3I6uNaCgc7NIS7P7+RgbWZ/QNs2KsFbHVM1pMTMu/U8k7ONWWGOeEPGfCOP 5YTJsQuWU3Leg/04UDAIVRcTwFPEFY4y8pnKdOMoZmve7+ulDG+MC7t+iBDhAZ5QoWy1 pWkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694160819; x=1694765619; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=RWZM8Q/uIy8my/IXpdHmpbEduZUYWK8mH9X8KWk+rE4=; b=bnIZodvylgSZLkE3sMxlWOgP8/Aa9nB/R8EdHS+j33J5O6YluFJyIcRqXIGDNSY8Zd E7busBY39/WM76YDdR2iTGV4Lwai5tbYxpbYWivbwyGbjAPBc2v0aWAO9rHT0ail/4tg f2zzjMPVwG0q4zCb/X9eHEm89BJjg8WRDt4GMY5Q7j8cZPzc0vR4lXcjNix4VnXLRK/C /08L5YcXwgXEl2DqvMQihppE9DT7IsPtMchu7qWBoDd81B2GMwJACtk2LGPwwDAzljmr MBTdLrnyebENS6G5ES0jfvWJvVLwKwBgXpX6AoSa4MgWHnn1QYgCJwcuOP2Uh85XfuNK nXqQ== X-Gm-Message-State: AOJu0YwTcWqEfl2JaPOhVgpznQdDdvNbQpgV9mPdpLGekDIREUn5Rhss xzLWh7L5LE/Nxht9kyHXvLJ9aA== X-Google-Smtp-Source: AGHT+IFlgUgFFWJP4twtv7eegf3o5nfvQzIkS3a6S8h2RTjkRlbK3B/juMDPxfbjjDget6fljmxQVA== X-Received: by 2002:a17:906:300f:b0:9a1:b43b:73a0 with SMTP id 15-20020a170906300f00b009a1b43b73a0mr1224993ejz.20.1694160819243; Fri, 08 Sep 2023 01:13:39 -0700 (PDT) Received: from [192.168.1.20] ([178.197.214.188]) by smtp.gmail.com with ESMTPSA id z20-20020a170906241400b009829d2e892csm695713eja.15.2023.09.08.01.13.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Sep 2023 01:13:38 -0700 (PDT) Message-ID: <9626f079-22f3-5327-5a45-23e5dfcda5c6@linaro.org> Date: Fri, 8 Sep 2023 10:13:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH 6/6] arm64: dts: qcom: add uart console support for SM4450 Content-Language: en-US To: Tengfei Fan , agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org Cc: robimarko@gmail.com, quic_gurus@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_tsoni@quicinc.com, quic_shashim@quicinc.com, quic_kaushalk@quicinc.com, quic_tdas@quicinc.com, quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com, kernel@quicinc.com, quic_bjorande@quicinc.com References: <20230908065847.28382-1-quic_tengfan@quicinc.com> <20230908065847.28382-7-quic_tengfan@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <20230908065847.28382-7-quic_tengfan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/09/2023 08:58, Tengfei Fan wrote: > Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes > which helps SM4450 boot to shell with console on boards with this SoC. > > Signed-off-by: Tengfei Fan > --- > arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 14 +- > arch/arm64/boot/dts/qcom/sm4450.dtsi | 258 ++++++++++++++++++++++++ > 2 files changed, 270 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts > index 00a1c81ca397..bb8c58fb4267 100644 > --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts > +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts > @@ -10,9 +10,19 @@ > model = "Qualcomm Technologies, Inc. SM4450 QRD"; > compatible = "qcom,sm4450-qrd", "qcom,sm4450"; > > - aliases { }; > + aliases { > + serial0 = &uart7; > + }; > > chosen { > - bootargs = "console=hvc0"; > + stdout-path = "serial0:115200n8"; Wait, what? You told me you cannot use serial and stdout-path! https://lore.kernel.org/all/f0f94ea9-94b1-ccd1-0a43-3cb119fc5d94@quicinc.com/ > }; > }; > + > +&qupv3_id_0 { > + status = "okay"; > +}; > + > +&uart7 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi > index 2395b1d655a2..3af7255fca35 100644 > --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi > @@ -7,6 +7,8 @@ > #include > #include > #include > +#include > +#include > #include > > / { > @@ -262,6 +264,26 @@ > }; > }; > > + firmware { > + scm: scm { > + compatible = "qcom,scm-sm4450", "qcom,scm"; > + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; > + #reset-cells = <1>; > + }; > + }; > + > + clk_virt: interconnect-0 { > + compatible = "qcom,sm4450-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-1 { > + compatible = "qcom,sm4450-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > memory@a0000000 { > device_type = "memory"; > /* We expect the bootloader to fill in the size */ > @@ -387,12 +409,118 @@ > clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; > }; > > + qupv3_id_0: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x00ac0000 0x0 0x2000>; > + ranges; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + iommus = <&apps_smmu 0x163 0x0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; > + interconnect-names = "qup-core"; > + #address-cells = <2>; > + #size-cells = <2>; > + status = "disabled"; > + > + uart7: serial@a88000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0 0x00a88000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; > + status = "disabled"; > + }; > + }; > + > + aggre1_noc: interconnect@16e0000 { > + tible = "qcom,sm4450-aggre1-noc"; > + reg = <0 0x016e0000 0 0x1c080>; > + #interconnect-cells = <2>; > + clocks = <&gcc GCC_SDCC2_AHB_CLK>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre2_noc: interconnect@1700000 { > + compatible = "qcom,sm4450-aggre2-noc"; > + reg = <0 0x01700000 0 0x31080>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + clocks = <&rpmhcc RPMH_IPA_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; > + }; > + > + cnoc2: interconnect@1500000 { Keep order by unit address. > + compatible = "qcom,sm4450-cnoc2"; > + reg = <0 0x1500000 0 0x6200>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + ... > + > intc: interrupt-controller@17200000 { > compatible = "arm,gic-v3"; > reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ > @@ -480,4 +711,31 @@ > , > ; > }; > + > + tlmm: pinctrl@f100000 { You did not test it... This node cannot be here and tools will tell you this. No need for review from us - tools are doing this. It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). > + compatible = "qcom,sm4450-tlmm"; > + reg = <0 0x0f100000 0 0x300000>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 137>; > + wakeup-parent = <&pdc>; > + > + qup_uart7_rx: qup-uart7-rx-state { > + pins = "gpio22"; > + function = "qup1_se2_l2"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart7_tx: qup-uart7-tx-state { > + pins = "gpio22"; > + function = "qup1_se2_l2"; > + drive-strength = <2>; > + bias-disable; > + }; > + }; > + Stray blank line. > }; Best regards, Krzysztof