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Date: Fri, 17 Oct 2025 16:55:25 +0200
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Subject: Re: [PATCH 25/39] dt-bindings: display: bridge: Document NXP i.MX95
 pixel interleaver support
To: Frank Li <Frank.li@nxp.com>
Cc: dri-devel@lists.freedesktop.org, Abel Vesa <abelvesa@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>, Fabio Estevam <festevam@gmail.com>,
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References: <20251011170213.128907-1-marek.vasut@mailbox.org>
 <20251011170213.128907-26-marek.vasut@mailbox.org>
 <aO1LkIAfErQhQ58j@lizhi-Precision-Tower-5810>
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From: Marek Vasut <marek.vasut@mailbox.org>
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On 10/13/25 8:57 PM, Frank Li wrote:

Hello Frank,

>> +  fsl,syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description: |
>> +      A phandle which points to Control and Status Registers (CSR) module.
> 
> Need justify why not standard interface such as clock, phy, reset ...

Because this is neither clock, nor reset nor anything else. This is 
really only a remote register which controls the pixel interleaving. 
Therefore, syscon.

>> +
>> +  ports:
>> +    $ref: /schemas/graph.yaml#/properties/ports
>> +
>> +    properties:
>> +      port@0:
>> +        $ref: /schemas/graph.yaml#/properties/port
> 
> video-interfaces.yaml?
No, because none of the properties in video-interfaces.yaml are 
applicable to this port as far as I can tell.

The rest is fixed, thanks !