* [PATCH v4 01/16] dt-bindings: clock: convert rockchip,px30-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 02/16] dt-bindings: clock: convert rockchip,rk3036-cru.txt " Johan Jonker
` (16 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,px30-cru.txt to YAML.
Changes against original bindings:
Use compatible string: "rockchip,px30-pmucru"
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
Changed V2:
add allOf:if:then: constraining
---
.../bindings/clock/rockchip,px30-cru.txt | 70 ----------
.../bindings/clock/rockchip,px30-cru.yaml | 120 ++++++++++++++++++
2 files changed, 120 insertions(+), 70 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
deleted file mode 100644
index 55e78cdde..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-* Rockchip PX30 Clock and Reset Unit
-
-The PX30 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
-- compatible: CRU should be "rockchip,px30-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed
- in clock-names
-- clock-names: Should contain the following:
- - "xin24m" for both PMUCRU and CRU
- - "gpll" for CRU (sourced from PMUCRU)
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing, pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "i2sx_clkin" - external I2S clock - optional,
- - "gmac_clkin" - external GMAC clock - optional
-
-Example: Clock controller node:
-
- pmucru: clock-controller@ff2bc000 {
- compatible = "rockchip,px30-pmucru";
- reg = <0x0 0xff2bc000 0x0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- cru: clock-controller@ff2b0000 {
- compatible = "rockchip,px30-cru";
- reg = <0x0 0xff2b0000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@ff030000 {
- compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff030000 0x0 0x100>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
new file mode 100644
index 000000000..c88e7e3db
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip PX30 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The PX30 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-cru
+ - rockchip,px30-pmucru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,px30-cru
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+ items:
+ enum:
+ - xin24m
+ - xin32k
+ - gpll
+ - gmac_clkin
+ - i2sx_clkin
+
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/px30-cru.h>
+
+ pmucru: clock-controller@ff2bc000 {
+ compatible = "rockchip,px30-pmucru";
+ reg = <0xff2bc000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff2b0000 {
+ compatible = "rockchip,px30-cru";
+ reg = <0xff2b0000 0x1000>;
+ clocks = <&xin24m>, <&pmucru PLL_GPLL>;
+ clock-names = "xin24m", "gpll";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 02/16] dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
2022-04-02 14:36 ` [PATCH v4 01/16] dt-bindings: clock: convert rockchip,px30-cru.txt to YAML Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 03/16] dt-bindings: clock: convert rockchip,rk3188-cru.txt " Johan Jonker
` (15 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3036-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
---
.../bindings/clock/rockchip,rk3036-cru.txt | 56 -------------
.../bindings/clock/rockchip,rk3036-cru.yaml | 80 +++++++++++++++++++
2 files changed, 80 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
deleted file mode 100644
index 20df350b9..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-* Rockchip RK3036 Clock and Reset Unit
-
-The RK3036 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3036-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "ext_i2s" - external I2S clock - optional,
- - "rmii_clkin" - external EMAC clock - optional
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3036-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@20060000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x20060000 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml
new file mode 100644
index 000000000..121b298a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3036 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3036 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3036-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ enum:
+ - xin24m
+ - ext_i2s
+ - rmii_clkin
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3036-cru";
+ reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 03/16] dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
2022-04-02 14:36 ` [PATCH v4 01/16] dt-bindings: clock: convert rockchip,px30-cru.txt to YAML Johan Jonker
2022-04-02 14:36 ` [PATCH v4 02/16] dt-bindings: clock: convert rockchip,rk3036-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 04/16] dt-bindings: clock: convert rockchip,rk3228-cru.txt " Johan Jonker
` (14 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3188-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
Changed V3:
add Rockchip maintainer on her request
fix yamllint line too long
Changed V2:
change clocks maxItems
add clock-names
use clock-controller node name
remove assigned-xxx
---
.../bindings/clock/rockchip,rk3188-cru.txt | 61 -------------
.../bindings/clock/rockchip,rk3188-cru.yaml | 86 +++++++++++++++++++
2 files changed, 86 insertions(+), 61 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
deleted file mode 100644
index 7f368530a..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Rockchip RK3188/RK3066 Clock and Reset Unit
-
-The RK3188/RK3066 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
- "rockchip,rk3066a-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
-dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
-Similar macros exist for the reset sources in these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "xin27m" - 27mhz crystal input on rk3066 - optional,
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_cif0" - external camera clock - optional,
- - "ext_rmii" - external RMII clock - optional,
- - "ext_jtag" - externalJTAG clock - optional
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3188-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10124000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10124000 0x400>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <1>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml
new file mode 100644
index 000000000..ff849c729
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3188/RK3066 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
+ dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
+ Similar macros exist for the reset sources in these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3066a-cru
+ - rockchip,rk3188-cru
+ - rockchip,rk3188a-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 7
+
+ clock-names:
+ minItems: 1
+ maxItems: 7
+ items:
+ enum:
+ - xin24m
+ - xin27m
+ - xin32k
+ - ext_cif0
+ - ext_hsadc
+ - ext_jtag
+ - ext_rmii
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3188-cru";
+ reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 04/16] dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (2 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 03/16] dt-bindings: clock: convert rockchip,rk3188-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 05/16] dt-bindings: clock: convert rockchip,rk3288-cru.txt " Johan Jonker
` (13 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3228-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
---
.../bindings/clock/rockchip,rk3228-cru.txt | 58 -------------
.../bindings/clock/rockchip,rk3228-cru.yaml | 82 +++++++++++++++++++
2 files changed, 82 insertions(+), 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
deleted file mode 100644
index f32304812..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Rockchip RK3228 Clock and Reset Unit
-
-The RK3228 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3228-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_gmac" - external GMAC clock - optional
- - "ext_hsadc" - external HSADC clock - optional
- - "phy_50m_out" - output clock of the pll in the mac phy
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3228-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10110000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10110000 0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml
new file mode 100644
index 000000000..0a91c5dc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3228 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3228 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3228-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+ items:
+ enum:
+ - xin24m
+ - ext_i2s
+ - ext_gmac
+ - ext_hsadc
+ - phy_50m_out
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3228-cru";
+ reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 05/16] dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (3 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 04/16] dt-bindings: clock: convert rockchip,rk3228-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 06/16] dt-bindings: clock: convert rockchip,rk3308-cru.txt " Johan Jonker
` (12 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3288-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
Changed V2:
add Rockchip maintainer on her request
fix yamllint line too long
restyle
---
.../bindings/clock/rockchip,rk3288-cru.txt | 67 -------------
.../bindings/clock/rockchip,rk3288-cru.yaml | 93 +++++++++++++++++++
2 files changed, 93 insertions(+), 67 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
deleted file mode 100644
index bf3a9ec19..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Rockchip RK3288 Clock and Reset Unit
-
-The RK3288 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-A revision of this SoC is available: rk3288w. The clock tree is a bit
-different so another dt-compatible is available. Noticed that it is only
-setting the difference but there is no automatic revision detection. This
-should be performed by bootloaders.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
- case of this revision of Rockchip rk3288.
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_edp_24m" - external display port clock - optional,
- - "ext_vip" - external VIP clock - optional,
- - "ext_isp" - external ISP clock - optional,
- - "ext_jtag" - external JTAG clock - optional
-
-Example: Clock controller node:
-
- cru: cru@20000000 {
- compatible = "rockchip,rk3188-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10124000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10124000 0x400>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <1>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml
new file mode 100644
index 000000000..558e5a094
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3288 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3288 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+
+ A revision of this SoC is available: rk3288w. The clock tree is a bit
+ different so another dt-compatible is available. Noticed that it is only
+ setting the difference but there is no automatic revision detection. This
+ should be performed by boot loaders.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3288-cru
+ - rockchip,rk3288w-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 8
+
+ clock-names:
+ minItems: 1
+ maxItems: 8
+ items:
+ enum:
+ - xin24m
+ - xin32k
+ - ext_i2s
+ - ext_hsadc
+ - ext_edp_24m
+ - ext_vip
+ - ext_isp
+ - ext_jtag
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3288-cru";
+ reg = <0xff760000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 06/16] dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (4 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 05/16] dt-bindings: clock: convert rockchip,rk3288-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 07/16] dt-bindings: clock: convert rockchip,rk3328-cru.txt " Johan Jonker
` (11 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3308-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
---
.../bindings/clock/rockchip,rk3308-cru.txt | 60 -------------
.../bindings/clock/rockchip,rk3308-cru.yaml | 86 +++++++++++++++++++
2 files changed, 86 insertions(+), 60 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt
deleted file mode 100644
index 9b151c5b0..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-* Rockchip RK3308 Clock and Reset Unit
-
-The RK3308 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: CRU should be "rockchip,rk3308-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing, pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
- "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
- "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
- - "mac_clkin" - external MAC clock - optional
-
-Example: Clock controller node:
-
- cru: clock-controller@ff500000 {
- compatible = "rockchip,rk3308-cru";
- reg = <0x0 0xff500000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@ff0a0000 {
- compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff0a0000 0x0 0x100>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml
new file mode 100644
index 000000000..01f2d1690
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3308 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3308 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3308-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 9
+
+ clock-names:
+ minItems: 1
+ maxItems: 9
+ items:
+ enum:
+ - xin24m
+ - xin32k
+ - mac_clkin
+ - mclk_i2s0_2ch_in
+ - mclk_i2s1_2ch_in
+ - mclk_i2s0_8ch_in
+ - mclk_i2s1_8ch_in
+ - mclk_i2s2_8ch_in
+ - mclk_i2s3_8ch_in
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff500000 {
+ compatible = "rockchip,rk3308-cru";
+ reg = <0xff500000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 07/16] dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (5 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 06/16] dt-bindings: clock: convert rockchip,rk3308-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 08/16] dt-bindings: clock: convert rockchip,rk3368-cru.txt " Johan Jonker
` (10 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3328-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
---
.../bindings/clock/rockchip,rk3328-cru.txt | 58 -------------
.../bindings/clock/rockchip,rk3328-cru.yaml | 82 +++++++++++++++++++
2 files changed, 82 insertions(+), 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
deleted file mode 100644
index 904ae682e..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Rockchip RK3328 Clock and Reset Unit
-
-The RK3328 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3328-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "clkin_i2s" - external I2S clock - optional,
- - "gmac_clkin" - external GMAC clock - optional
- - "phy_50m_out" - output clock of the pll in the mac phy
- - "hdmi_phy" - output clock of the hdmi phy pll - optional
-
-Example: Clock controller node:
-
- cru: clock-controller@ff440000 {
- compatible = "rockchip,rk3328-cru";
- reg = <0x0 0xff440000 0x0 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@ff120000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff120000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml
new file mode 100644
index 000000000..965f67be3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3328 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3328 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3328-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 5
+
+ clock-names:
+ minItems: 1
+ maxItems: 5
+ items:
+ enum:
+ - xin24m
+ - clkin_i2s
+ - gmac_clkin
+ - hdmi_phy
+ - phy_50m_out
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff440000 {
+ compatible = "rockchip,rk3328-cru";
+ reg = <0xff440000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 08/16] dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (6 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 07/16] dt-bindings: clock: convert rockchip,rk3328-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 09/16] dt-bindings: clock: convert rockchip,rv1108-cru.txt " Johan Jonker
` (9 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rk3368-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
---
.../bindings/clock/rockchip,rk3368-cru.txt | 61 -------------
.../bindings/clock/rockchip,rk3368-cru.yaml | 86 +++++++++++++++++++
2 files changed, 86 insertions(+), 61 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt
deleted file mode 100644
index 7c8bbcfed..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Rockchip RK3368 Clock and Reset Unit
-
-The RK3368 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3368-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing, pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_gmac" - external GMAC clock - optional
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_isp" - external ISP clock - optional,
- - "ext_jtag" - external JTAG clock - optional
- - "ext_vip" - external VIP clock - optional,
- - "usbotg_out" - output clock of the pll in the otg phy
-
-Example: Clock controller node:
-
- cru: clock-controller@ff760000 {
- compatible = "rockchip,rk3368-cru";
- reg = <0x0 0xff760000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10124000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x10124000 0x400>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <1>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml
new file mode 100644
index 000000000..b09d169c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3368 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RK3368 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3368-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 9
+
+ clock-names:
+ minItems: 1
+ maxItems: 9
+ items:
+ enum:
+ - xin24m
+ - xin32k
+ - ext_i2s
+ - ext_gmac
+ - ext_hsadc
+ - ext_isp
+ - ext_jtag
+ - ext_vip
+ - usbotg_out
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3368-cru";
+ reg = <0xff760000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 09/16] dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (7 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 08/16] dt-bindings: clock: convert rockchip,rk3368-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 10/16] ARM: dts: rockchip: add clocks property to Rockchip cru nodes Johan Jonker
` (8 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Convert rockchip,rv1108-cru.txt to YAML.
Changes against original bindings:
Add clocks and clock-names because the device has to have
at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
add more clocks
add clocks to example
add clocks requirement
---
.../bindings/clock/rockchip,rv1108-cru.txt | 59 -------------
.../bindings/clock/rockchip,rv1108-cru.yaml | 83 +++++++++++++++++++
2 files changed, 83 insertions(+), 59 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt
deleted file mode 100644
index 161326a4f..000000000
--- a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Rockchip RV1108 Clock and Reset Unit
-
-The RV1108 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rv1108-cru"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changeable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "ext_vip" - external VIP clock - optional
- - "ext_i2s" - external I2S clock - optional
- - "ext_gmac" - external GMAC clock - optional
- - "hdmiphy" - external clock input derived from HDMI PHY - optional
- - "usbphy" - external clock input derived from USB PHY - optional
-
-Example: Clock controller node:
-
- cru: cru@20200000 {
- compatible = "rockchip,rv1108-cru";
- reg = <0x20200000 0x1000>;
- rockchip,grf = <&grf>;
-
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller:
-
- uart0: serial@10230000 {
- compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
- reg = <0x10230000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cru SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml
new file mode 100644
index 000000000..abbfdfae8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1108 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RV1108 clock controller generates and supplies clocks to various
+ controllers within the SoC and also implements a reset controller for SoC
+ peripherals.
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All available clocks are defined as
+ preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
+ used in device tree sources. Similar macros exist for the reset sources in
+ these files.
+ There are several clocks that are generated outside the SoC. It is expected
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rv1108-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+
+ clock-names:
+ minItems: 1
+ maxItems: 6
+ items:
+ enum:
+ - xin24m
+ - ext_gmac
+ - ext_i2s
+ - ext_vip
+ - hdmiphy
+ - usbphy
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@20200000 {
+ compatible = "rockchip,rv1108-cru";
+ reg = <0x20200000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 10/16] ARM: dts: rockchip: add clocks property to Rockchip cru nodes
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (8 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 09/16] dt-bindings: clock: convert rockchip,rv1108-cru.txt " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 11/16] arm64: " Johan Jonker
` (7 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Add clocks and clock-names to the Rockchip cru nodes, because
the device has to have at least one input clock.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
combine patches
---
arch/arm/boot/dts/rk3036.dtsi | 2 ++
arch/arm/boot/dts/rk3066a.dtsi | 3 ++-
arch/arm/boot/dts/rk3188.dtsi | 3 ++-
arch/arm/boot/dts/rk322x.dtsi | 2 ++
arch/arm/boot/dts/rk3288.dtsi | 2 ++
arch/arm/boot/dts/rv1108.dtsi | 2 ++
6 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index ba2b8891b..3894b8d2e 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -330,6 +330,8 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3036-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index c25b9695d..de9915d94 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -202,8 +202,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
-
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index a94321e90..cdd4a0bd5 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -195,8 +195,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
-
#clock-cells = <1>;
#reset-cells = <1>;
};
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 5868eb512..2547f46fe 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -484,6 +484,8 @@
cru: clock-controller@110e0000 {
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 26b9bbe31..487b0e03d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -862,6 +862,8 @@
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3288-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 448254906..eceaa940b 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -456,6 +456,8 @@
cru: clock-controller@20200000 {
compatible = "rockchip,rv1108-cru";
reg = <0x20200000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 11/16] arm64: dts: rockchip: add clocks property to Rockchip cru nodes
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (9 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 10/16] ARM: dts: rockchip: add clocks property to Rockchip cru nodes Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 12/16] arm64: dts: rockchip: rk3399: use generic node name for pmucru Johan Jonker
` (6 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Add clocks and clock-names to the Rockchip cru node, because
the device has to have at least one input clock.
With the addition of new properties also sort the node properties
a little bit where needed.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
combine patches
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++--
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 1cbe21261..2dfa67f1c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -745,10 +745,11 @@
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- rockchip,grf = <&grf>;
-
assigned-clocks = <&cru SCLK_RTC32K>;
assigned-clock-rates = <32768>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index b822533dc..9c76c288b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -758,6 +758,8 @@
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index c99da9032..4f0b5feaa 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -747,6 +747,8 @@
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 88f26d89e..ce1cc42ff 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1416,6 +1416,8 @@
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -1426,6 +1428,8 @@
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 12/16] arm64: dts: rockchip: rk3399: use generic node name for pmucru
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (10 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 11/16] arm64: " Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 13/16] arm64: dts: rockchip: fix compatible string rk3328 cru node Johan Jonker
` (5 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
The node names should be generic, so fix this for the rk3399 pmucru node
and rename it to "clock-controller".
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index ce1cc42ff..56af1a1d6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1413,7 +1413,7 @@
clock-names = "apb_pclk";
};
- pmucru: pmu-clock-controller@ff750000 {
+ pmucru: clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
clocks = <&xin24m>;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 13/16] arm64: dts: rockchip: fix compatible string rk3328 cru node
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (11 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 12/16] arm64: dts: rockchip: rk3399: use generic node name for pmucru Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 16:53 ` Krzysztof Kozlowski
2022-04-02 14:36 ` [PATCH v4 14/16] dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml Johan Jonker
` (4 subsequent siblings)
17 siblings, 1 reply; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
The rockchip,rk3328-cru.txt file was converted to YAML.
A DT test of the rk3328 cru node gives notifications regarding
the compatible string. Bring it in line with the binding by
removing some unused fall back strings.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 9c76c288b..8ceac0388 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -756,7 +756,7 @@
};
cru: clock-controller@ff440000 {
- compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
+ compatible = "rockchip,rk3328-cru";
reg = <0x0 0xff440000 0x0 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 13/16] arm64: dts: rockchip: fix compatible string rk3328 cru node
2022-04-02 14:36 ` [PATCH v4 13/16] arm64: dts: rockchip: fix compatible string rk3328 cru node Johan Jonker
@ 2022-04-02 16:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-02 16:53 UTC (permalink / raw)
To: Johan Jonker, heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
On 02/04/2022 16:36, Johan Jonker wrote:
> The rockchip,rk3328-cru.txt file was converted to YAML.
> A DT test of the rk3328 cru node gives notifications regarding
> the compatible string. Bring it in line with the binding by
> removing some unused fall back strings.
I explained to you on your v1, syscon is not a fallback compatible.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> index 9c76c288b..8ceac0388 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> @@ -756,7 +756,7 @@
> };
>
> cru: clock-controller@ff440000 {
> - compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
Please do not resend the same patch without changes and without
finishing the discussion. This looks wrong (and external references you
gave support this). What does this resend means? Discussion is over?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 14/16] dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (12 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 13/16] arm64: dts: rockchip: fix compatible string rk3328 cru node Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 14:36 ` [PATCH v4 15/16] dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml Johan Jonker
` (3 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
With the rk3399 cru YAML conversion the original text author was
somehow added as a maintainer, but who's currently no longer involved
on the subject. Replace this position with the Rockchip clock maintainer
on her request.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
.../devicetree/bindings/clock/rockchip,rk3399-cru.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
index 72b286a1b..5ee686938 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RK3399 Clock and Reset Unit
maintainers:
- - Xing Zheng <zhengxing@rock-chips.com>
+ - Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v4 15/16] dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (13 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 14/16] dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 16:55 ` Krzysztof Kozlowski
2022-04-02 14:36 ` [PATCH v4 16/16] dt-bindings: clock: fix some conversion clock issues for rockchip,rk3399-cru.yaml Johan Jonker
` (2 subsequent siblings)
17 siblings, 1 reply; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
The node names should be generic, so fix this for the pmucru node example
in the rockchip,rk3399-cru.yaml file and rename it to "clock-controller".
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
.../devicetree/bindings/clock/rockchip,rk3399-cru.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
index 5ee686938..e91147c84 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
@@ -77,7 +77,7 @@ additionalProperties: false
examples:
- |
- pmucru: pmu-clock-controller@ff750000 {
+ pmucru: clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0xff750000 0x1000>;
#clock-cells = <1>;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 15/16] dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml
2022-04-02 14:36 ` [PATCH v4 15/16] dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml Johan Jonker
@ 2022-04-02 16:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-02 16:55 UTC (permalink / raw)
To: Johan Jonker, heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
On 02/04/2022 16:36, Johan Jonker wrote:
> The node names should be generic, so fix this for the pmucru node example
> in the rockchip,rk3399-cru.yaml file and rename it to "clock-controller".
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> .../devicetree/bindings/clock/rockchip,rk3399-cru.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
You received here the tag, there were no changes in the patch, yet you
ignored it.
This raises my concern that for all other patches you also ignored my tags.
Please resend with collecting appropriate tags from all reviewers. For
places you discard the tag, please mention it in each patch changelog
(under ---).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 16/16] dt-bindings: clock: fix some conversion clock issues for rockchip,rk3399-cru.yaml
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (14 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 15/16] dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml Johan Jonker
@ 2022-04-02 14:36 ` Johan Jonker
2022-04-02 16:45 ` [PATCH v4 00/16] Convert Rockchip clk Krzysztof Kozlowski
2022-04-02 16:59 ` Krzysztof Kozlowski
17 siblings, 0 replies; 21+ messages in thread
From: Johan Jonker @ 2022-04-02 14:36 UTC (permalink / raw)
To: heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
With the YAML conversion somehow "assigned-xxx" properties where added.
If a proper clock is added to the cru node these properties are no longer
needed, so removed them.
With the conversion of rockchip,rk3399-cru.txt a table with external clocks
was copied. Include these clocks into the schema.
Add clocks and clocks-names to example and make them a requirement.
Reorder/restyle so that this file is line with the other Rockchip
CRU bindings.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
.../bindings/clock/rockchip,rk3399-cru.yaml | 55 ++++++++++---------
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
index e91147c84..4574727da 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml
@@ -20,15 +20,8 @@ description: |
used in device tree sources. Similar macros exist for the reset sources in
these files.
There are several clocks that are generated outside the SoC. It is expected
- that they are defined using standard clock bindings with following
- clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "clkin_gmac" - external GMAC clock - optional,
- - "clkin_i2s" - external I2S clock - optional,
- - "pclkin_cif" - external ISP clock - optional,
- - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
- - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
+ that they are defined using standard clock bindings with the
+ clock-output-names defined in this schema.
properties:
compatible:
@@ -39,37 +32,41 @@ properties:
reg:
maxItems: 1
- "#clock-cells":
- const: 1
-
- "#reset-cells":
- const: 1
-
clocks:
minItems: 1
+ maxItems: 7
- assigned-clocks:
- minItems: 1
- maxItems: 64
-
- assigned-clock-parents:
+ clock-names:
minItems: 1
- maxItems: 64
-
- assigned-clock-rates:
- minItems: 1
- maxItems: 64
+ maxItems: 7
+ items:
+ enum:
+ - xin24m
+ - xin32k
+ - clkin_gmac
+ - clkin_i2s
+ - clk_usbphy0_480m
+ - clk_usbphy1_480m
+ - pclkin_cif
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
- description: >
- phandle to the syscon managing the "general register files". It is used
+ description:
+ Phandle to the syscon managing the "general register files". It is used
for GRF muxes, if missing any muxes present in the GRF will not be
available.
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
required:
- compatible
- reg
+ - clocks
+ - clock-names
- "#clock-cells"
- "#reset-cells"
@@ -80,6 +77,8 @@ examples:
pmucru: clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0xff750000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -87,6 +86,8 @@ examples:
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0xff760000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 00/16] Convert Rockchip clk
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (15 preceding siblings ...)
2022-04-02 14:36 ` [PATCH v4 16/16] dt-bindings: clock: fix some conversion clock issues for rockchip,rk3399-cru.yaml Johan Jonker
@ 2022-04-02 16:45 ` Krzysztof Kozlowski
2022-04-02 16:59 ` Krzysztof Kozlowski
17 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-02 16:45 UTC (permalink / raw)
To: Johan Jonker, heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
On 02/04/2022 16:36, Johan Jonker wrote:
> Combined serie of previously converted Rockchip clk bindings.
>
> Changed V4:
> combine dts patches
> add more clocks
> add clocks to example
> add clocks requirement
>
I think I reviewed most of them and gave you tags, but I do not see any
tags. Did you remove them because of some change?
See also:
https://elixir.bootlin.com/linux/v5.13/source/Documentation/process/submitting-patches.rst#L543
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 00/16] Convert Rockchip clk
2022-04-02 14:36 [PATCH v4 00/16] Convert Rockchip clk Johan Jonker
` (16 preceding siblings ...)
2022-04-02 16:45 ` [PATCH v4 00/16] Convert Rockchip clk Krzysztof Kozlowski
@ 2022-04-02 16:59 ` Krzysztof Kozlowski
17 siblings, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-02 16:59 UTC (permalink / raw)
To: Johan Jonker, heiko, zhangqing
Cc: robh+dt, krzk+dt, mturquette, sboyd, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
On 02/04/2022 16:36, Johan Jonker wrote:
> Combined serie of previously converted Rockchip clk bindings.
>
> Changed V4:
> combine dts patches
> add more clocks
Why adding more clocks? The discussion whether to do it did not finish.
You merged all your patches into one series, but this makes impossible
to compare them with your previous submission:
b4 diff ...
Analyzing 20 messages in the thread
ERROR: Could not auto-find previous revision
Run "b4 am -T" manually, then "b4 diff -m mbx1 mbx2"
Please provide links to previous versions on lore, so we can check what
changed.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread