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Thu, 25 Jan 2024 11:01:13 -0800 (PST) Received: from [192.168.2.107] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id l8-20020a5d5608000000b003392bcd6c48sm13097531wrv.79.2024.01.25.11.01.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jan 2024 11:01:12 -0800 (PST) Message-ID: <96f9306f-3445-484b-bd3c-82e708681f1b@linaro.org> Date: Thu, 25 Jan 2024 19:01:10 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/28] spi: dt-bindings: samsung: add samsung,spi-fifosize property Content-Language: en-US To: Mark Brown Cc: andi.shyti@kernel.org, arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com References: <20240125145007.748295-1-tudor.ambarus@linaro.org> <20240125145007.748295-6-tudor.ambarus@linaro.org> <7ef86704-3e40-4d39-a69d-a30719c96660@sirena.org.uk> <1c58deef-bc0f-4889-bf40-54168ce9ff7c@linaro.org> <55af5d4a-7bc9-4ae7-88c5-5acae4666450@sirena.org.uk> From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/25/24 17:45, Mark Brown wrote: > On Thu, Jan 25, 2024 at 05:30:53PM +0000, Tudor Ambarus wrote: >> On 1/25/24 17:26, Mark Brown wrote: > >>> OK, so just the compatible is enough information then? > >> For gs101, yes. All the gs101 SPI instances are configured with 64 bytes >> FIFO depths. So instead of specifying the FIFO depth for each SPI node, >> we can infer the FIFO depth from the compatible. > > But this is needed for other SoCs? This change is scattered through a There are SoCs that have multiple instances of the SPI IP, and they configure them with different FIFO depths. See "samsung,exynosautov9-spi" for example: SPI0, SPI1, and SPI6 are configured by the SoC to use 256 bytes FIFO depths, while all the other 8 SPI instances use 64 bytes FIFOs. I tried to explain the entire logic of the series in another reply, see it here: https://lore.kernel.org/linux-arm-kernel/40ba9481-4aea-4a72-87bd-c2db319be069@linaro.org/T/#u > very large series which does multiple things so it's a bit difficult to > follow what's going on here. Sorry, I was afraid that this might happen. I agree, I'll split tomorrow this patch set in 3 smaller sets: 1/ dumb cleaning patches 2/ heavy lifting cleaning patches 3/ gs101 addition