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([2001:a61:3456:4e01:6ae:b55a:bd1d:57fc]) by smtp.gmail.com with ESMTPSA id y7-20020a5d6147000000b003330b55b941sm1117877wrt.77.2023.11.30.02.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 02:20:33 -0800 (PST) Message-ID: <971eb35068639ec404669ea5320c8183ea71a7d0.camel@gmail.com> Subject: Re: [PATCH v2 2/2] hwmon: ltc4282: add support for the LTC4282 chip From: Nuno =?ISO-8859-1?Q?S=E1?= To: Linus Walleij Cc: nuno.sa@analog.com, linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jean Delvare , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Bartosz Golaszewski , Andy Shevchenko Date: Thu, 30 Nov 2023 11:20:32 +0100 In-Reply-To: References: <20231124-ltc4282-support-v2-0-952bf926f83c@analog.com> <20231124-ltc4282-support-v2-2-952bf926f83c@analog.com> <6384831c05b8ceeaf4a16cf9229770252989b762.camel@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 (3.48.4-1.fc38) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2023-11-29 at 21:55 +0100, Linus Walleij wrote: > On Wed, Nov 29, 2023 at 5:08=E2=80=AFPM Nuno S=C3=A1 wrote: >=20 > > Cool, I actually thought that having the direction + get/set stuff woul= d be weird > > given the fact that we can only PULL_LOW or HIGH_Z the pins. >=20 > There are several drivers in the kernel that implement .set_config(), > it's existing and should be enabled if it has uses. >=20 Yeah, it might make sense to support it specially for the input case. AFAIC= T, if I use the .set_config() (but from a quick look I think we will need to add su= pport for it in gpiolib for the high-z configuration), then I can't use the gpio_regm= ap stuff. As the driver stands I don't think I could do it anyways because setting gp= io2-3 and alert requires to write 0 on the register rather than 1. But again, I'm sti= ll very suspicious about the whole thing. The datasheet states: "GPIO1-GPIO3 and ALERT all have comparators monitoring the voltage on these pins with a threshold of 1.28V even when the pins are configured as outputs." But we can't really set the direction for gpio2-3 and the alert pins (only = getting the level and setting it as PULL_LOW or HIGH_Z. gpio1 is the only one where= we can configure it as input or open drain ouput. Bah, I'll try to see if someone = internally can shed some light on this. =20 > As Andy points out: when the driver reaches a certain complexity, > such as a huge table of muxable pins (that need to be configured to > a certain muxing from device tree), and numerous complicated > pin config options (also needing to be set up from device tree), > it may be worth to implement a separate pin control driver that > act as "backend" for the GPIO driver. >=20 > I think a separate pin control driver would be overkill in this case, > it's a PWM driver with some smallish GPIO portions AFAICT, > but you get to decide. >=20 Agreed, the chip only supports 4 pins and it is an optional feature. The ma= in usage for the chip iis to act as an hot swap controller (which maps into hwmon). - Nuno S=C3=A1