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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id j12-20020a05620a288c00b006b640efe6dasm7179583qkp.132.2022.10.20.05.29.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Oct 2022 05:29:03 -0700 (PDT) Message-ID: <972db8bd-e45a-47b1-c2c4-008c279c6b59@linaro.org> Date: Thu, 20 Oct 2022 08:29:02 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH 1/2] dt-bindings: PCI: qcom: Add SC8280XP/SA8540P interconnects Content-Language: en-US To: Johan Hovold Cc: Johan Hovold , Stanimir Varbanov , Lorenzo Pieralisi , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Krishna chaitanya chundru , quic_vbadigan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221017112449.2146-1-johan+linaro@kernel.org> <20221017112449.2146-2-johan+linaro@kernel.org> <010b6de2-5df6-77c9-2f04-43f2edc89ff2@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 20/10/2022 03:57, Johan Hovold wrote: > On Wed, Oct 19, 2022 at 10:37:31AM -0400, Krzysztof Kozlowski wrote: >> On 17/10/2022 07:24, Johan Hovold wrote: >>> Add the missing SC8280XP/SA8540P "pcie-mem" and "cpu-pcie" interconnect >>> paths to the bindings. >>> >>> Fixes: 76d777ae045e ("dt-bindings: PCI: qcom: Add SC8280XP to binding") >>> Fixes: 76c4207f4085 ("dt-bindings: PCI: qcom: Add SA8540P to binding") >>> Signed-off-by: Johan Hovold >>> --- >>> .../devicetree/bindings/pci/qcom,pcie.yaml | 25 +++++++++++++++++++ >>> 1 file changed, 25 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> index 22a2aac4c23f..a55434f95edd 100644 >>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> @@ -62,6 +62,12 @@ properties: >>> minItems: 3 >>> maxItems: 12 >>> >>> + interconnects: >>> + maxItems: 2 >>> + >>> + interconnect-names: >>> + maxItems: 2 >>> + >>> resets: >>> minItems: 1 >>> maxItems: 12 >>> @@ -629,6 +635,25 @@ allOf: >>> items: >>> - const: pci # PCIe core reset >>> >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,pcie-sa8540p >>> + - qcom,pcie-sc8280xp >>> + then: >>> + properties: >>> + interconnects: >>> + maxItems: 2 >> >> No need for this. >> >>> + interconnect-names: >>> + items: >>> + - const: pcie-mem >>> + - const: cpu-pcie >>> + required: >>> + - interconnects >>> + - interconnect-names >> >> else: >> ?? >> >> Otherwise, you allow any names for other variants. > > Are you suggesting something like moving the names to the common > constraints for now: > > interconnects: > maxItems: 2 > > interconnect-names: > items: > - const: pcie-mem > - const: cpu-pcie > > and then in the allOf: > > - if: > properties: > compatible: > contains: > enum: > - qcom,pcie-sa8540p > - qcom,pcie-sc8280xp > then: > required: > - interconnects > - interconnect-names > else: > properties: > interconnects: false > interconnect-names: false > > This way we'd catch anyone adding interconnects to a DTS without first > updating the bindings, but it also seems to go against the idea of > bindings fully describing the hardware by saying that no other platforms > have interconnects (when they actually do even if we don't describe it > just yet). You can add a comment to the else like "TODO: Not described yet". I would prefer to have specific but incomplete bindings, instead of loose one which later might cause people adding whatever names they like. > Or should we do the above but without the else clause to have some > constraints in place on the names at least? This would work as well if you think the names are applicable for other devices. Best regards, Krzysztof