From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leonard Crestez Subject: [PATCH 2/7] dt-bindings: devfreq: Add bindings for generic imx buses Date: Mon, 12 Aug 2019 21:49:46 +0300 Message-ID: <97b0bff95ddb85b06ef3d2f8079faa36562a956d.1565633880.git.leonard.crestez@nxp.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: In-Reply-To: References: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Stephen Boyd , MyungJoo Ham , Kyungmin Park , Rob Herring Cc: Dong Aisheng , =?UTF-8?q?Artur=20=C5=9Awigo=C5=84?= , Abel Vesa , Saravana Kannan , Anson Huang , linux-arm-kernel@lists.infradead.org, Viresh Kumar , Michael Turquette , linux-pm@vger.kernel.org, linux-imx@nxp.com, Krzysztof Kozlowski , Chanwoo Choi , Will Deacon , Alexandre Bailon , kernel@pengutronix.de, Fabio Estevam , Mark Rutland , Shawn Guo , Georgi Djakov , devicetree@vger.kernel.org, Jacky Bai List-Id: devicetree@vger.kernel.org Add initial dt bindings for the interconnects inside i.MX chips. Multiple external IPs are involved but SOC integration means the software controllable interfaces are very similar. This is initially only for imx8mm but add an "fsl,imx8m-nic" fallback similar to exynos-bus. Signed-off-by: Leonard Crestez --- .../devicetree/bindings/devfreq/imx.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml new file mode 100644 index 000000000000..0e2ee3a5205e --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/imx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and sometimes + voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied for + normal world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris + FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + compatible: + contains: + enum: + - fsl,imx8m-noc + - fsl,imx8m-nic + + reg: + maxItems: 1 + description: GPV area + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +examples: + - | + #include + noc: noc@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + operating-points-v2 = <&noc_opp_table>; + }; -- 2.17.1