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Tue, 07 Jul 2026 09:36:14 -0700 (PDT) X-Received: by 2002:a17:90b:4ec5:b0:37e:1609:b304 with SMTP id 98e67ed59e1d1-38756801500mr5684047a91.1.1783442173406; Tue, 07 Jul 2026 09:36:13 -0700 (PDT) Received: from [192.168.29.166] ([49.43.234.127]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3118389d9bcsm2524489eec.20.2026.07.07.09.36.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jul 2026 09:36:12 -0700 (PDT) Message-ID: <97b205e8-5ab7-4205-b1dc-cbcb0497987d@oss.qualcomm.com> Date: Tue, 7 Jul 2026 22:06:05 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 11/11] arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm To: Konrad Dybcio , Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Georgi Djakov , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Anurag Pateriya References: <20260702-shikra-dt-m1-v5-0-f911ac92720c@oss.qualcomm.com> <20260702-shikra-dt-m1-v5-11-f911ac92720c@oss.qualcomm.com> <9c1aab59-14b2-4811-b778-8e96645bd65b@oss.qualcomm.com> Content-Language: en-US From: Komal Bajaj In-Reply-To: <9c1aab59-14b2-4811-b778-8e96645bd65b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: MBREdICyEakOPVJofw5XBuueZ0mPqfXH X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDE2MiBTYWx0ZWRfX7JEE8vzylNw8 DfE+CKyRlxSEHjtzU+/YgTr4lkXqF2if/rP+jwa2U96zclCHFMPJV3Q2lwyC03nPkb7IXl42KeP SsemUGNUxRI37QRpi70DofEtmFsf5FM= X-Authority-Analysis: v=2.4 cv=SZfHsPRu c=1 sm=1 tr=0 ts=6a4d2afe cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fIivk1FRtaL8gRNK6azaIA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=TqdALn-mf9RdMn6JgEsA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: MBREdICyEakOPVJofw5XBuueZ0mPqfXH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDE2MiBTYWx0ZWRfX1xq8JVgxBwg0 ssfPcUmG1Dkze0syOJS89mrQfajDtH0Mm6eVjo/J9uDmXBjyMNocx3RgCjdpqBidMg0drMMTlxf jStrK183jJsupnOoCdA74M1V/Hzg+9DBmCvBZVVotslnj5/J3Xi3FRKPPT1LKM53eDcN2O9MBhd 3zWiiFq1dSkPNRx/gVWb3I5eRfQ7qvBQAt1VtGhCNe7+cczA+f+VOpiWcO6VyHhu+wZCvOeTsdv hh7g38FyUiglSJhkNfzhijAxl8+G1+9uxtiSuBd8jBRBAKaW/srwWNRSGngz4vt4nu56SZYPpOB sNcuJZ/kEhmAfvB8V6pqa7uh/qpPz7kO3v2IghJM58WgAi/sB8pi7fQdIZTMKU0q9PcKCAKB3IT L1Yk8bgt9FIAiwmbNXExYUp+KHuZ/dkDjchmzdM/bF6lVX/Fo+zQ0DGiLgMU01L8D0tptyEhXd3 B4tNWXVga2FGH2ktliQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_04,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070162 On 7/2/2026 4:25 PM, Konrad Dybcio wrote: > On 7/2/26 11:50 AM, Komal Bajaj wrote: >> Add gpio-reserved-ranges property to the tlmm node for all three >> Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs used by the >> SoC internally and not available for general use. > These are generally added to prevent non-secure access upon TLMM > probe, i.e. the board won't boot if some of them are not protected. > > I assume the proposed set contains both ones that are _absolutely > forbidden_ for Linux to touch, but also ones that are dedicated to > some specific purpose that Linux _shouldn't_ touch. Yes, some GPIOs are reserved for secure-world use and are therefore not accessible from the non-secure world. I will update the commit message accordingly. > > Please add comments, like in glymur-crd.dtsi: > > gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ > <10 2>, /* OOB UART */ > <44 4>; /* Security SPI (TPM) */ > > explaining what these pins are. Sure, will add this info. Thanks Komal > > If any of them are boot-critical, squash this into the introductory > change > > Konrad