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([2600:8803:e7e4:500:8e86:179b:44b8:cc2b]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-65724cb873dsm5554288eaf.4.2025.11.18.09.46.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Nov 2025 09:46:01 -0800 (PST) Message-ID: <97c6b55d-9505-4091-8f0b-317dcbd70838@baylibre.com> Date: Tue, 18 Nov 2025 11:46:00 -0600 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] dt-bindings: iio: adc: adi,ad7380: add spi-buses property To: Rob Herring Cc: Mark Brown , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org References: <20251107-spi-add-multi-bus-support-v2-0-8a92693314d9@baylibre.com> <20251107-spi-add-multi-bus-support-v2-5-8a92693314d9@baylibre.com> <20251118155905.GB3236324-robh@kernel.org> Content-Language: en-US From: David Lechner In-Reply-To: <20251118155905.GB3236324-robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/18/25 9:59 AM, Rob Herring wrote: > On Fri, Nov 07, 2025 at 02:52:51PM -0600, David Lechner wrote: >> Add spi-buses property to describe how many SDO lines are wired up on >> the ADC. These chips are simultaneous sampling ADCs and have one SDO >> line per channel, either 2 or 4 total depending on the part number. >> >> Signed-off-by: David Lechner >> --- >> .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml >> index b91bfb16ed6bc6c605880f81050250d1ed9c307a..9ef46cdb047d45d088e0fbc345f58c5b09083385 100644 >> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml >> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml >> @@ -62,6 +62,10 @@ properties: >> spi-cpol: true >> spi-cpha: true >> >> + spi-data-buses: >> + minItems: 1 >> + maxItems: 4 >> + > > As the property is not required, what's the default? spi-perepheral-props.yaml defines: default: [0] Do I need to repeat that here? > >> vcc-supply: >> description: A 3V to 3.6V supply that powers the chip. >> >> @@ -245,6 +249,22 @@ allOf: >> patternProperties: >> "^channel@[0-3]$": false >> >> + # 2-channel chip can only have up to 2 buses >> + - if: >> + properties: >> + compatible: >> + enum: >> + - adi,ad7380 >> + - adi,ad7381 >> + - adi,ad7386 >> + - adi,ad7387 >> + - adi,ad7388 >> + - adi,ad7389 >> + then: >> + properties: >> + spi-data-buses: >> + maxItems: 2 >> + >> examples: >> - | >> #include >> @@ -260,6 +280,7 @@ examples: >> spi-cpol; >> spi-cpha; >> spi-max-frequency = <80000000>; >> + spi-data-buses = <0>, <1>; >> >> interrupts = <27 IRQ_TYPE_EDGE_FALLING>; >> interrupt-parent = <&gpio0>; >> @@ -284,6 +305,7 @@ examples: >> spi-cpol; >> spi-cpha; >> spi-max-frequency = <80000000>; >> + spi-data-buses = <0>, <1>, <2>, <3>; > > An example that doesn't look like a 1 to 1 mapping would be better. > Otherwise, it still looks to me like you could just define the bus > width. I'm not sure we could do that on this chip since it doesn't have the possibility of more than one line per channel. I can add a patch with a binding for a different chip though that can have such an example. > >> >> interrupts = <27 IRQ_TYPE_EDGE_FALLING>; >> interrupt-parent = <&gpio0>; >> >> -- >> 2.43.0 >>