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Sun, 16 Nov 2025 23:10:40 -0600 Received: from [172.24.233.20] (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5AH5AZq11909410; Sun, 16 Nov 2025 23:10:36 -0600 Message-ID: <97ed4be2-c9ab-4829-9886-683a183337cd@ti.com> Date: Mon, 17 Nov 2025 10:40:35 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: display: ti,am65x-dss: Add am62p dss compatible To: Conor Dooley CC: , , , , , , , , , , , , , , , , , References: <20251114064336.3683731-1-s-jain1@ti.com> <20251114064336.3683731-2-s-jain1@ti.com> <20251114-vanilla-pork-f3854bd230f2@spud> Content-Language: en-US From: Swamil Jain In-Reply-To: <20251114-vanilla-pork-f3854bd230f2@spud> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|BN0PR10MB5063:EE_ X-MS-Office365-Filtering-Correlation-Id: b51d22e1-4c2c-4b06-0b54-08de2597a8a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 05:10:43.1397 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b51d22e1-4c2c-4b06-0b54-08de2597a8a4 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5063 Hi Conor, On 11/14/25 23:28, Conor Dooley wrote: > On Fri, Nov 14, 2025 at 12:13:34PM +0530, Swamil Jain wrote: >> TI's AM62P SoC contains two instances of the TI Keystone Display >> SubSystem (DSS), each with two video ports and two video planes. These >> instances support up to three independent video streams through OLDI, >> DPI, and DSI interfaces. >> >> DSS0 (first instance) supports: >> - Two OLDI transmitters on video port 1, configurable in dual-link or >> single-link mode. >> - DPI output on video port 2. >> >> DSS1 (second instance) supports: >> - One OLDI transmitter on video port 1 (single-link mode only). >> - DSI controller output on video port 2. >> >> The two OLDI transmitters can be configured in clone mode to drive a >> pair of identical OLDI single-link displays. DPI outputs from >> DSS0 VP2, DSS1 VP1, and DSS1 VP2 are multiplexed, allowing only one >> DPI output at a time. >> >> Add the compatible string "ti,am62p-dss" and update related >> description accordingly. >> >> AM62P has different power domains for DSS and OLDI compared to other >> Keystone SoCs. Therefore, add 'minItems' and set to 1 and update the >> 'maxItems' field in the power-domains property to 3 for the >> "ti,am62p-dss" compatible entry to reflect this hardware difference. >> >> Signed-off-by: Swamil Jain >> --- >> .../bindings/display/ti/ti,am65x-dss.yaml | 127 +++++++++++++++++- >> 1 file changed, 126 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> index 361e9cae6896..8bd188e7f09b 100644 >> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >> @@ -24,6 +24,19 @@ description: | >> DPI signals are also routed internally to DSI Tx controller present within the >> SoC. Due to clocking limitations only one of the interface i.e. either DSI or >> DPI can be used at once. >> + The AM62P has two instances of TI Keystone Display SubSystem, each with two >> + video ports and two video planes. These instances can support up to 3 >> + independent video streams through OLDI, DPI, and DSI interfaces. >> + DSS0 (first instance) supports: >> + - Two OLDI TXes on video port 1, configurable in dual-link or >> + single link clone mode >> + - DPI output on video port 2 >> + DSS1 (second instance) supports: >> + - One OLDI TX on video port 1 (single-link mode only) >> + - DSI controller output on video port 2 >> + The two OLDI TXes can be configured in clone mode to drive a pair of >> + identical OLDI single-link displays. DPI outputs from DSS0 VP2, DSS1 VP1, >> + and DSS1 VP2 are muxed, allowing only one DPI output at a time. >> >> properties: >> compatible: >> @@ -31,6 +44,7 @@ properties: >> - ti,am625-dss >> - ti,am62a7-dss >> - ti,am62l-dss >> + - ti,am62p-dss >> - ti,am65x-dss >> >> reg: >> @@ -81,7 +95,8 @@ properties: >> maxItems: 1 >> >> power-domains: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 3 >> description: phandle to the associated power domain >> >> dma-coherent: >> @@ -347,3 +362,113 @@ examples: > > I don't think you need a new 15 line example to add 2 power domains when > everything else remains the same. Sure, added it for reference, yeah, I also think it is not required. Ok, will drop this example. > > Please also restrict the power domains by compatible. I'm not sure > reading this binding if the new device can function with 1 power domain, > but your binding permits that as well as not being clear that other > devices only need one. Ack, will restrict the power domains by compatible. Regards, Swamil. > > pw-bot: changes-requested > > Cheers, > Conor. > >> }; >> }; >> }; >> + >> + - | >> + #include >> + #include >> + #include >> + >> + dss0: dss@30200000 { >> + compatible = "ti,am62p-dss"; >> + reg = <0x30200000 0x1000>, /* common */ >> + <0x30202000 0x1000>, /* vidl1 */ >> + <0x30206000 0x1000>, /* vid */ >> + <0x30207000 0x1000>, /* ovr1 */ >> + <0x30208000 0x1000>, /* ovr2 */ >> + <0x3020a000 0x1000>, /* vp1: Used for OLDI */ >> + <0x3020b000 0x1000>, /* vp2: Used as DPI Out */ >> + <0x30201000 0x1000>; /* common1 */ >> + reg-names = "common", "vidl1", "vid", >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>, >> + <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>, >> + <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 186 6>, >> + <&dss0_vp1_clk>, >> + <&k3_clks 186 2>; >> + clock-names = "fck", "vp1", "vp2"; >> + interrupts = ; >> + >> + oldi-transmitters { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + oldi0_am62p: oldi@0 { >> + reg = <0>; >> + clocks = <&k3_clks 186 0>; >> + clock-names = "serial"; >> + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + oldi0_am62p_in: endpoint { >> + remote-endpoint = <&dpi0_am62p_out0>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + oldi0_am62p_out: endpoint { >> + remote-endpoint = <&panel0_in>; >> + }; >> + }; >> + }; >> + }; >> + >> + oldi1_am62p: oldi@1 { >> + reg = <1>; >> + clocks = <&k3_clks 186 0>; >> + clock-names = "serial"; >> + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + oldi1_am62p_in: endpoint { >> + remote-endpoint = <&dpi0_am62p_out1>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + oldi1_am62p_out: endpoint { >> + remote-endpoint = <&panel1_in>; >> + }; >> + }; >> + }; >> + }; >> + }; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0>; >> + dpi0_am62p_out0: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&oldi0_am62p_in>; >> + }; >> + dpi0_am62p_out1: endpoint@1 { >> + reg = <1>; >> + remote-endpoint = <&oldi1_am62p_in>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dpi1_am62p_out: endpoint { >> + remote-endpoint = <&dpi_bridge>; >> + }; >> + }; >> + }; >> + };